JPH07175832A - Cad system for integrated circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of virtual wiring simulation by improving the accuracy of wiring capacity of each wiring in a logic circuit used for the virtual wiring simulation. CONSTITUTION:The logic circuit is inputted at every hierarchical block by a logic circuit input processing means 14. A temporary arrangement wiring means 15 performs temporary arrangement wiring on the logic circuit inputted at every hierarchical block. The wiring capacity of the wiring can be found from the wiring length of each wiring based on the temporary arrangement wiring. Since the wiring capacity can be found from the wiring length compared with a conventional method to find the wiring capacity from the number of branching, the accuracy of the wiring capacity can be improved.

Description

Detailed Description of the Invention

[0001]

INDUSTRIAL APPLICABILITY The present invention enables the input of a logic circuit to be designed into an integrated circuit and enables the logic circuit to be designed before the completion of the actual placement and wiring of the logic circuit in the integrated circuit. The present invention relates to a CAD device for integrated circuit design capable of performing virtual wiring simulation for verifying the operation of a circuit, and in particular, improves the accuracy of the wiring capacitance of each wiring in a logic circuit to be used for virtual wiring simulation. The present invention relates to a CAD (computer aided design) device for designing an integrated circuit, which can improve the accuracy of the virtual wiring simulation and further reduce the difference between the virtual wiring simulation and the actual wiring simulation.

[0002]

2. Description of the Related Art Due to widespread use of computer devices and advances in software technology, for example, EWS
A CAD device using a computer device such as an (engineering workstation) has been widely used for designing a logic circuit incorporated in an integrated circuit or the like.

In such a CAD device for integrated circuit design, for example, based on the concept of hierarchical design, for example, a hierarchical block is defined by a set of adjacent logic circuit elements, and the block corresponding to the hierarchical block is defined. Design logic circuits sequentially using symbols. In the logic circuit designed in this way, information about the logic gate actually used is stored in, for example, the instance table. In addition, information about wirings used for connecting the logic gates, input terminals, and output terminals used is written in, for example, a net table.

Some CAD devices for designing such integrated circuits are equipped with a logic simulator for simulating the designed logic circuit on a computer device. This logic simulator is to operate the logic circuit in a simulated manner based on the logic of the logic circuit and the like based on the circuit information indicating the logic circuit input in the CAD device for integrated circuit design itself. .

In such a simulated operation, the speed at which a signal propagates through the wiring in the logic circuit is important. Such signal propagation speed generally depends on the wiring capacitance of the wiring.

Among the logic simulators, the one called "virtual wiring simulation", in particular, finds such a wiring capacity simply and uses it. For example, in such a virtual wiring simulation, the wiring capacitance of each wiring is uniformly obtained from the number of branches of each wiring.

On the other hand, among the logic simulators, the one that performs what is called real wiring simulation completes the design of the actual layout and wiring on the integrated circuit relating to the logic circuit under design, and then the actual wiring simulation on the integrated circuit. The wiring capacitance applied to each wiring is calculated based on the actual length of each wiring. For example, for each wiring, the extension of the length of the wiring, including the branched one, is obtained, and the total wiring capacity of the wiring is obtained, for example, according to the capacity per unit length. Further, in the actual simulation in this actual wiring simulation, the logic circuit designed based on the speed of the signal propagating through the wiring in accordance with the wiring capacitance thus obtained is designed on the computer device. Operate in a simulated manner.

[0008]

However, in the virtual wiring simulator, the wiring capacitance is simply obtained. Therefore, accompanying this, the speed of the signal propagating through the wiring being simulated may be different from the actual speed. In particular,
This error may become so large that it cannot be ignored. Therefore, even if no error occurs in the virtual wiring simulation, an error may occur in the actual wiring simulation.

If an error not found in the virtual wiring simulation stage is found in the actual wiring simulation in a later step in the design step, the design TAT (turn around time) becomes longer. There is a fear.

Such an actual wiring simulation is performed in a later step than the virtual wiring simulation because of the fact that the actual placement and wiring is performed in this way. For example, in terms of shortening the TAT of the design work, it is desirable that the error of the designed logic circuit is found at an earlier stage. Therefore, usually, an effort is made to find an error in a target logic circuit in the stage of the virtual wiring simulation.

The present invention has been made to solve the above-mentioned conventional problems, and improves the accuracy of the wiring capacitance of each wiring in the logic circuit to be used for the virtual wiring simulation, thereby improving the virtual capacity. An object of the present invention is to provide a CAD device for integrated circuit design, which can improve the accuracy of wiring simulation and further reduce the difference between the virtual wiring simulation and the actual wiring simulation.

[0012]

According to the present invention, it is possible to input a logic circuit to be designed into an integrated circuit, and before the completion of the design of actual placement and wiring for the logic circuit in the integrated circuit, CAD for integrated circuit design capable of virtual wiring simulation for verifying operation of the logic circuit
In the device, in a form that can be distinguished for each hierarchical block,
Logic circuit information storage means for storing circuit information indicating the input logic circuit together with input status information including at least information indicating completion / non-completion of input for each hierarchical block; and the hierarchical block to be input. After the declaration is input in advance, the input of the hierarchical block is accepted, the inputted circuit information is written in the logical circuit information storage means in a form that can be distinguished as the hierarchical block, and the input of the logical circuit of the hierarchical block is input. At the time of completion, this completion is declared and input, and the logic circuit input processing means for writing the input status information of the hierarchical block based on the completion declaration input also to the logic circuit information storage means and the input completion declaration input Temporary placement that performs the temporary placement and routing of the hierarchical block that has already been performed and outputs the result as temporary placement and routing information. Line means and the wiring capacity calculation means for calculating the wiring capacity of the wiring in the logic circuit using the temporary placement wiring information, and the virtual wiring simulation by using the wiring capacity calculated by the wiring capacity calculation means. A virtual wiring simulation means for performing at least a part of the logic circuit input processing means and at least a part of the temporary placement and wiring means in a single processing system, and the virtual placement and wiring means. The above object is achieved by performing the processing as a background processing for the processing performed by the logic circuit input processing means.

[0013]

As described above, from the viewpoint of obtaining more sufficient simulation accuracy, the wiring capacitance based on the actual wiring length after the actual placement and wiring is used instead of the wiring capacitance simply obtained for the simulation. It is preferable. However, the processing required for such actual placement and wiring is relatively large and time-consuming. Therefore, in the past, even if the actual wiring simulation was performed, the virtual wiring simulation using the wiring capacitance that was simply obtained was performed before this.

Against this background, in the present invention, the method of determining the wiring capacitance used in the virtual wiring simulation is described as the real wiring while suppressing the deterioration of the workability of the design using the CAD device for integrated circuit design. We are trying to make it closer to the method of obtaining the wiring capacitance used in the simulation.

For this reason, first, in the present invention, the input of the logic circuit to be designed into the integrated circuit using the CAD device for designing the integrated circuit is generally performed sequentially for each hierarchical block. It focuses on the fact that it is a thing. That is, even if all the designed logic circuits to be built into an integrated circuit are not input, if attention is paid to each hierarchical block, there is an input completion at each time point. Is.

Further, with respect to the placement and routing process for the designed logic circuit in the integrated circuit as described above, even if the placement and routing process takes a relatively long time, if it is performed in each hierarchical block unit. The present invention focuses on the fact that the amount of processing required for the placement and wiring can be markedly suppressed and the processing time can be shortened.

The conventional layout and wiring of the designed logic circuit is performed for the layout of the entire integrated circuit in which the logic circuit is built. On the other hand, in the present invention, the integrated circuit layout is first simply divided into areas (hereinafter referred to as placement / wiring areas) assigned to each hierarchical block. Further, placement and routing (hereinafter referred to as temporary placement and routing) for obtaining the wiring capacity used in the virtual wiring simulation is performed for each such placement and routing area or for each hierarchical block.

In particular, such temporary placement and wiring is carried out as a background process for the process related to the input of the designed logic circuit which progresses stepwise. Therefore, in the present invention, it is possible to perform the temporary placement wiring in parallel while suppressing the processing amount of the temporary placement wiring and further suppressing the input work efficiency of the designed logic circuit. Further, in the virtual wiring simulation according to the present invention, the wiring capacitance based on the temporary placement wiring is used, and thus the accuracy of the obtained wiring capacitance can be improved as compared with the conventional case. Therefore, according to the present invention,
It is possible to further improve the accuracy of the virtual wiring simulation.

FIG. 1 is a block diagram showing the gist of the present invention.

As shown in FIG. 1, in the CAD device for designing an integrated circuit of the present invention, the logic circuit information storage means 16, the logic circuit input processing means 14, the temporary placement and wiring means 15, and the wiring capacity calculating means. 17 and a virtual wiring simulation means 18 are provided.

First, the logic circuit information storage means 16
The circuit information indicating the input logic circuit is stored together with the input status information including at least information indicating completion / non-completion of the input for each hierarchical block in a form that can be distinguished for each hierarchical block. The circuit information may use, for example, the instance table or the net table as described above.

The logic circuit input processing means 14, after declaring and inputting the hierarchical block to be input in advance, accepts the input of the hierarchical block and outputs the input circuit information in a form that can be distinguished as the hierarchical block. Write to the logic circuit information storage means 16. Further, the logic circuit input processing means 14 declares the completion when the input of the logic circuit of the hierarchical block being input is completed, and inputs the status information of the hierarchical block based on the declaration input of the completion. Also, the logic circuit information storage means 1
Write to 6.

The logic circuit input processing means 14 displays a logic circuit which has already been input, for example, on a graphic display, and an input operator refers to the logic circuit and inputs new logic gates in order. It may be something like. The present invention does not specifically limit the logic circuit input processing means 14, and for example, a conventionally used one may be partially modified and used. As described above, the logic circuit input processing means 14, in particular, inputs the declaration of the hierarchical block to be input,
The feature is that the declaration input of the completion of the input of the hierarchical block being input is performed.

The virtual wiring means 15 performs temporary placement and wiring of the hierarchical block for each hierarchical block, which is input by using the logic circuit input processing means 14 and whose input is completed. Is.
Whether or not the input of the logic circuit of each hierarchical block is completed is performed by referring to the input status information of the logic circuit information storage means 16 written by the logic circuit input processing means 14. Also, the temporary placement and wiring means 15
The temporary placement and routing performed in (1) is basically similar to the conventional placement and routing performed for the entire integrated circuit layout. This temporary placement and wiring performed by this temporary placement and wiring means 15 is
In that it is performed for each hierarchical block for which logic circuit input has been completed,
Further, it is different from the conventional placement and routing in that it is performed for a limited area on the integrated circuit layout corresponding to the hierarchical block.

The wiring capacity calculation means 17 uses the temporary placement wiring information output from the temporary placement wiring means 15 to obtain the wiring capacitance of the wiring in the logic circuit. After the temporary placement and routing by the temporary placement and routing means 15, for the hierarchical block for which the temporary placement and routing has been completed, the length of the wiring in the logic circuit is more strictly determined.
Therefore, if the wiring capacitance of the wiring is obtained according to such a wiring length, the accuracy can be further improved as compared with the conventional wiring capacitance obtained simply by the number of branching of the wiring.

Further, when the wiring capacitance is obtained in this way, the virtual wiring simulation is performed by the temporary wiring simulation means 18 using the obtained wiring capacitance.

In the present invention, at least a part of the logic circuit input processing means 14 and at least a part of the temporary placement and wiring means 15 are realized by a single processing system. For example, a CPU (central processing) that executes the processing performed by the logic circuit input processing means 14.
unit) and the CPU that executes the processing performed by the temporary placement and wiring means 15 are the same.

Further, in the present invention, a single processing system is used as described above, and the processing performed by the temporary placement and wiring means 15 is used as background processing for the processing performed by the logic circuit input processing means 14. I am trying to do it. Therefore, when inputting the logic circuit designed by the logic circuit input processing means 14, the processing relating to this input is prioritized and the processing relating to the temporary placement and wiring means 15 is interrupted. Is unlikely to decrease. On the other hand, when the input related to the logic circuit input processing means 14 is not performed, the temporary placement and routing by the temporary placement and routing means 15 can be performed on the hierarchical block that has already been input.

As described above, according to the present invention, at least a part of the logic circuit input processing means 14 and at least a part of the temporary placement and wiring means 15 are formed into a single processing system, which is required. It is possible to further reduce the size of the hardware used, and it is also possible to suppress a decrease in processing speed that accompanies such a reduction in the size of the hardware.

[0030]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a flow chart showing the overall processing of the CAD device for integrated circuit design of the embodiment to which the present invention is applied.

In FIG. 2, first, at step 110, a hierarchical structure of a designed logic circuit to be built into the integrated circuit is constructed. For example, as shown in the hierarchical structure tree of FIG. 3, the division of each circuit portion in the logic circuit into the hierarchical blocks, the vertical relationship between the hierarchical blocks, and the like are determined.

For example, in FIG. 3, the entire logic circuit built in the integrated circuit is a hierarchical block A. The hierarchical block A is divided into a hierarchical block B and a hierarchical block C. Further, the hierarchical block B is divided into a hierarchical block D, a hierarchical block E and a hierarchical block F. On the other hand, the hierarchical block C is divided into a hierarchical block G and a hierarchical block H.

In FIG. 2, the step 112 is continued.
Now, predict the number of logic gates for each hierarchical block. The number of logic gates is based on a basic 2-input AND logic gate as a unit, and indicates the circuit scale of each hierarchical block.

For example, in the logic circuit shown in the hierarchical structure tree of FIG. 3, the hierarchical blocks D to H are 300 gates, 200 gates, 100 gates, and 200 gates, respectively.
There are 100 gates. Therefore, since the hierarchical block B is a combination of the hierarchical blocks D to F, it has 700 gates for convenience. For the hierarchical block C, the hierarchical blocks G and H
Since it is a combination of the above, there are 400 gates for convenience. Since the hierarchical block A is a combination of the hierarchical blocks B and C, it has a total of 1100 gates.

In step 112, the connection strength between the hierarchical blocks is determined. For example, what is shown in the hierarchical structure tree of FIG. 3, that is, the hierarchical blocks A to
For those configured with H, the interblock connection strength as shown in FIG. 4 is determined. In the table of four columns in FIG. 4, the connection strengths between the respective hierarchical blocks are indicated by "1" to "10". "10" has the strongest connection strength.

For example, in the first column, the hierarchical block D
, The connection strength between each of the hierarchical blocks E to H is shown, and the connection strength is "6", "4", respectively.
It is "1" and "2". Also, in the second column, the connection strength between the hierarchical block E and the hierarchical blocks F to H is shown, which are "3", "1", respectively.
It is “1”. The third column shows the connection strengths of the hierarchical blocks G and H to the hierarchical block F, which are "3" and "1", respectively. In the fourth column, the connection strength between the hierarchical block G and the hierarchical block H is shown and is “6”.

Subsequently, in step 114 of FIG. 2, for each hierarchical block determined in step 110, respective placement and routing areas in the integrated circuit are determined. For example, in the case of the hierarchical blocks A to H as shown in FIG. 3, the placement and wiring area of each hierarchical block A to H is determined as shown in FIG. 5, for example. In FIG. 5, the relative relationship of the arrangement positions of the hierarchical blocks D to H in the integrated circuit is determined based on the connection strength between hierarchical blocks of FIG. For example, for the hierarchical block G, the hierarchical block F
Is higher than the connection strength “1” with the hierarchical block D and the connection strength “1” with the hierarchical block E. Are located adjacent to each other.

The processing performed in step 114 and the processing performed up to step 114 will be described later in more detail with reference to FIG.

Subsequently, in step 116, the input for each hierarchical block of the designed logic circuit to be built into the integrated circuit, the temporary placement wiring for each hierarchical block, and the hierarchical block to which the temporary placement wiring is made are related. The layout and wiring area is optimized, and finally, the wiring capacitance of each wiring regarding the hierarchical block for which the temporary placement and wiring has been completed is extracted. Further, the extraction result of the wiring capacity is the virtual wiring capacity file 118.
Written to.

The processing performed in this step 116 will be described later in detail with reference to the flowcharts of FIGS.

Subsequently, in step 122, the step 1 written in the virtual wiring capacitance file 118 is performed.
The virtual wiring simulation is performed using the wiring capacitance of each wiring extracted in 16. This step 122
In this virtual wiring simulation carried out in 1., since the wiring capacitance having a higher accuracy than the conventional one is used, the simulation accuracy can be further improved as compared with the conventional virtual wiring simulation.

FIG. 6 is a block diagram showing a data file relating to the layout / wiring area determination processing of the hierarchical block performed in this embodiment and the relationship between the respective processing.

In FIG. 6, reference numerals 142, 152,
Both 154 and 156 are data files.
The block diagram file of 142 is the above-mentioned 1 of FIG.
It is input at 10. Also, reference numeral 1 in FIG.
The process of extracting block connection information 44 is performed in step 110 of FIG. By this block connection information extraction processing, the data of the block connection information file indicated by reference numeral 154 can be obtained.

Further, by the other processing performed in the step 112 in FIG. 2, the gate number file for each hierarchical block indicated by reference numeral 152 in FIG. 6 and the reference numeral 15
The data of the connection strength file between hierarchical blocks shown by 6 is obtained.

When the data of the files shown by the reference numerals 152, 154 and 156 are obtained, the processing corresponding to the step 114 in FIG. 2, that is, the processing shown by the reference numerals 162, 164 and 166 in FIG. 6 is performed. Done.

Specifically, the placement / wiring area determination processing indicated by the reference numeral 162 is based on the data of the hierarchical block gate number file indicated by the reference numeral 152, and the area of each hierarchical block is determined in proportion to the number of gates. To decide. Further, the placement and wiring position determination processing indicated by the reference numeral 164 is based on the data of the block connection information file indicated by the reference numeral 154 and the data of the inter-block connection strength file indicated by the reference numeral 156, and each hierarchical block Determine the relative positional relationship between the. Further, after completion of the processes indicated by the reference numerals 162 and 164, the reference numeral 1
In the placement and routing area decision processing indicated by 66, the absolute placement position of each hierarchical block on the integrated circuit is decided.

FIGS. 7 to 10 are flow charts showing the processing of the part to which the present invention is applied, which is performed in this embodiment as a whole.

7 to 10, the circuit diagram input for each hierarchical block and the placement and wiring for each hierarchical block (hereinafter referred to as P & R) shown in step 116 of FIG. 2 are performed.
Called. P & R: place and route) processing, optimization processing of the placement and routing area after P & R of each hierarchical block, and processing of extracting wiring capacitance after P & R for each hierarchical block.

7 to 10, the circuit diagram of a certain hierarchical block α is first input, and after this is completed, another hierarchical block β is input, as an example. .

First, in step 210 of FIG. 7,
In order to input the logic circuit of the hierarchical block α, it is declared that the hierarchical block α is to be input, and then logical gates and the like are sequentially input. After this, in step 212,
After completing the input of all the logic circuits of the hierarchical block α, the completion is declared and input. In accordance with this declaration input, in the following step 214, the input logic circuit diagram of the hierarchical block α is stored in a storage device (corresponding to the logic circuit information storage means 16 in FIG. 1).

At this stage, the logic circuit for the hierarchical block α has been decided. Therefore, in the following step 216, P & R for the hierarchical block α is performed.
To start. This P & started at step 216
R is performed as a background process of subsequent logic circuit diagram input. For example, the following step 21
It is performed in parallel with processing such as 8, 232 or 252, and
In some cases, this background processing is temporarily stopped when the CPU processing time is congested.

In step 218 of FIG. 7, the next input is the logic circuit diagram correction input for the hierarchical block α which has been once input, or the logical input for another hierarchical block, for example, the hierarchical block β. Determine if it is a circuit diagram input. In the case of the logical circuit diagram modification input for the hierarchical block α, the process proceeds to the following step 232. On the other hand, if the input is the logic circuit diagram for another hierarchical block β, the process proceeds to step 252 of FIG.

First, in step 232, in order to input the logic circuit of the hierarchical block α again, a declarative input for inputting the hierarchical block α is made, and then the logical circuit for the hierarchical block α is inputted or modified. Perform sequentially.

Immediately after the declaration input for inputting the hierarchical block α in step 232, the P & R for the hierarchical block α is stopped as shown in step 234. This is again the hierarchical block α
This is because the P & R for this hierarchical block α started in step 216 becomes meaningless because of the correction of the above.

After the step 232, when all the inputs and modifications of the logic circuit to the hierarchical block α are completed, the completion declaration is input in step 236. After the step 236, the process branches to the front of the step 210.

On the other hand, the process branches from step 218,
In the step 252 of FIG. 8, a declaration input for starting the input of the hierarchical block β is made to input the logic circuit of the hierarchical block β this time. After that, the input of the logic circuit of the hierarchical block β, for example, the input of the logic gate is sequentially performed. Immediately after the declaration is input in the step 252, the step 2 is executed in the step 256.
Pause the P & R started at 16. This is to prevent the CPU occupancy of the P & R performed as the background processing from deteriorating the reaction of the CPU with respect to the input made in and after step 252.

After the step 252, when the input of the logic circuits of the hierarchical block β which is sequentially performed is completed, the completion declaration is input in step 258. Also, after this declaration input in step 258, step 2
At 59, P & R suspended at step 256 above
To restart. That is, P & with respect to the hierarchical block α
It is the restart of R.

In the following step 262, it is determined whether or not all the inputs to the logic circuit for the hierarchical block β have been completed. That is, when the logic circuit input of the hierarchical block β is not completed, the series of processes from step 252 is performed. On the other hand, if the input of all the hierarchical blocks β is completed, then step 268 is performed.

In step 268, it is determined whether or not the P & R of the hierarchical block α which is being performed in the background processing is completed. If it is determined in step 268 that the processing has not ended, then step 28 in FIG.
Go to 2. On the other hand, if it is determined that the processing is completed, then the process proceeds to step 292 of FIG.

Next, in the step 282 of FIG. 9,
When it is determined in step 262 that the input of the circuit diagram of the hierarchical block β has been completed, the input termination process of the input logical circuit diagram of the hierarchical block β is performed. Specifically, this input end processing is to save the logic circuit diagram of the hierarchical block β for which all inputs have been completed together with the input status of this completion.

Thereafter, in the following step 284, the P & R of the hierarchical block α is completed. When all the P & R processing of the hierarchical block α is completed, the following step 28
At 6, the placement and routing area is optimized. The processing performed in step 286 will be described later in detail with reference to FIGS.

After this step 286, step 288
Then, it is determined whether or not the input processing or P & R of all the hierarchical blocks of the entire integrated circuit including the inputted hierarchical block α and the inputted hierarchical block β has been completed. If it is determined that all are completed, then the process branches to the front of step 296 in FIG. On the other hand, when it is determined that there is something that has not been completed, the step 21 in FIG.
Fork 6 ahead.

In the step 292 of FIG. 10, which is branched from the step 268 of FIG. 8, the P & R of the hierarchical block α is completed, so that the process of optimizing the placement and routing area for this hierarchical block α is performed. To do.
The process performed in this step 292 is the same as that in step 2 above.
The processing is similar to that performed in 86, and will be described later in detail with reference to FIG. 11 and FIG.

Next, at step 294, it is determined whether or not all logic circuit inputs and P & R of the entire integrated circuit including the hierarchical block α and the hierarchical block β have been completed. If it is determined in step 294 that all operations have been completed, the process proceeds to step 296. On the other hand, if it is determined that there is something that has not ended, the process branches to the front of the step 210 in FIG. 7.

At the step 296, since the logic circuit input or P & R of the entire integrated circuit including the hierarchical block α and the hierarchical block β is completed, each of the input integrated circuits is rewritten. Extract the wiring capacitance of the wiring. Specifically, as will be described later in detail with reference to FIG. 13, based on the length of each wiring after P & R,
The wiring capacitance of each wiring is obtained.

FIG. 11 and FIG. 12 are integrated circuit layout diagrams showing the state of each stage regarding the optimization of the placement and wiring area in this embodiment.

Hereinafter, FIG. 5, FIG. 11 and FIG.
2, the optimization process of the placement and routing area performed in this embodiment will be described in detail.

First, in this embodiment, the area of each hierarchical block as shown in FIG. 5 is set before the logic circuit input to the integrated circuit. After that, the logic circuit is input for each hierarchical block. In addition, P & R is sequentially performed for each hierarchical block for which the input of the logic circuit is completed. From the viewpoint of performing more optimal placement and routing, it is preferable that the logic circuit input or P & R to be performed for each hierarchical block be performed from the one having the highest connection strength.

Regarding the integrated circuit to be designed, at the time when the logic circuit input or P & R of at least one hierarchical block is completed, the step 286 in FIG. 9 or the FIG.
It is possible to optimize the placement and routing area shown in step 292 of 0.

For example, it is assumed that the logic circuit input or P & R of the hierarchical block D of FIG. 5 is completed. In FIG. 5, the area of the hierarchical block D is based on the number of logical gates (= 300 gates) predicted to be used for the hierarchical block, and the size thereof is based on the prediction. , To some extent. Therefore, in the hierarchical block D, P &
The area after R is generally smaller than the area of the hierarchical block D in FIG. For example, it becomes narrower as shown in the hierarchical block D in FIG. Further, the shape is also different from the initially set rectangular shape as shown in FIG.

Therefore, since the area of the hierarchical block D is reduced, it is possible to increase the area of another hierarchical block, specifically, the hierarchical block E or the hierarchical block F. Therefore, the hierarchical block D
The area of has become narrower and its shape has changed,
Optimization is performed by changing the shape and size of the area of other hierarchical blocks.

At this time, the order of the hierarchical blocks whose area and shape are changed is from the one having the strongest connection with the hierarchical block for which P & R related thereto is completed.

For example, with respect to the hierarchical block D of FIG. 11, the hierarchical block E is compared with the connection strength of the hierarchical block F (“4” indicated by “DF: 4” of FIG. 4). Of the hierarchical block E because the connection strength of the hierarchical block E is larger ("6" shown by "D-E: 6" in FIG.
After optimizing the placement and routing area of, the placement and routing area of the hierarchical block F is optimized.

When optimizing the layout and wiring area, it is preferable that each hierarchical block has a rectangular shape. This is because the rectangular shape generally has better wiring efficiency in the hierarchical block and the like, logic gate arrangement efficiency, and the like. The fact that the rectangular shape is preferable is the same as in the first determination of the placement / wiring area as shown in FIG.

Note that FIG. 12 shows the layout wiring area of each hierarchical block after optimization. Note that this FIG.
Although the layout wiring area of the hierarchical block E is not rectangular in shape, this is preferable because the integrated circuit area is effectively utilized.

FIG. 13 is a diagram showing a wiring length calculating method at the time of extracting the wiring capacitance in this embodiment.

In FIG. 3, one wiring from the coordinate point Pa to the coordinate point Pd on the integrated circuit is shown.
This wiring is bent at the coordinate points Pb and Pc.

The coordinate points Pa to Pd are respectively
(1,1), (3,1), (3,2), (5,2). Therefore, the wiring length L between the coordinate point Pa and the coordinate point Pb is "2". The wiring length L between the coordinate point Pb and the coordinate point Pc is "1". The wiring length between the coordinate point Pc and the coordinate point Pd is "2". In this embodiment, for such a bent wire, the wire length is the extension distance of the bent wire. For example, the wiring length L between the coordinate point Pa and the coordinate point Pd is (2 + 1 + 2 = 5).

Further, when the wiring length L based on the extended distance of the wiring is obtained in this manner, the wiring capacitance of each wiring in this embodiment is calculated according to the following equation.

Wiring capacitance = Kc × wiring length L (1)

Particularly, when the constant Kc is "1.2", the equation shown in FIG. 13 is as follows.

Wiring capacitance = 1.2 × 5 = 6 (2)

On the other hand, the conventionally calculated method of calculating the wiring capacitance is based on the following equation for the number X of branches of the wiring.

Wiring capacitance = Ka (X-1) + Kb (3)

For example, in equation (3), the constants Ka and Kb are "0.9" and "3.3", respectively. Therefore, for example, in the case of the branch number X (= 1) shown in FIG. 13, the wiring capacitance by the conventional calculation method obtained by the equation (3) is as follows.

Wiring capacity = 0.9 × (1-1) + 3.3 = 3.3 (4)

The wiring capacitance obtained by the equation (2) is almost twice the wiring capacitance obtained by the equation (4), and the error is large. Therefore, when a virtual wiring simulation using such a conventional wiring capacitance is performed, the simulation accuracy decreases. For example, even if no error occurs in the virtual wiring simulation, there is a risk that an error will occur in the actual wiring simulation.

In the present embodiment, the wiring capacitance used in the virtual wiring simulation is based on the tentative placement wiring, not the actual placement wiring. However, as described above, the wiring capacitance is not determined solely by the number of branches, but is performed based on the length of the arranged and arranged wiring. Therefore, the error in the wiring capacitance of the wiring after the temporary placement wiring as in the present invention with respect to the wiring capacitance after the actual placement wiring is more accurate than that which is determined only according to the conventional branch number. Is.

[0090]

As described above, according to the present invention, the accuracy of the wiring capacitance of each wiring in the logic circuit to be used for the virtual wiring simulation is improved, and thus,
It is possible to obtain an excellent effect that the accuracy of the virtual wiring simulation can be improved and the difference between the virtual wiring simulation and the actual wiring simulation can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a C for designing an integrated circuit of an embodiment to which the present invention is applied.
Flowchart showing the overall processing performed in the AD device

FIG. 3 is a hierarchical structure tree diagram showing a hierarchical block structure of an example of an integrated circuit to which the embodiment is applied and the number of gates of each hierarchical block.

FIG. 4 is a diagram showing connection strength between hierarchical blocks in the logic circuit of an example targeted by the embodiment.

FIG. 5 is an integrated circuit layout diagram showing an arrangement and wiring area of each hierarchical block in the logic circuit of the example of the embodiment.

FIG. 6 is a block diagram showing a process of determining a layout and wiring area performed in the embodiment.

FIG. 7 is a first flowchart showing a circuit diagram input process performed in the embodiment.

FIG. 8 is a second diagram showing the process of inputting the circuit diagram of the embodiment.
Flow chart

FIG. 9 is a third diagram showing the process of inputting the circuit diagram of the embodiment.
Flow chart

FIG. 10 is a fourth flowchart showing a process of inputting the circuit diagram of the embodiment.

FIG. 11 is a first integrated circuit layout diagram showing the optimization processing of the placement and routing area performed in the embodiment.

FIG. 12 is a second integrated circuit layout diagram showing a layout and wiring area optimization process performed in the embodiment.

FIG. 13 is a diagram showing the calculation of the wiring length used in the wiring capacitance calculation performed in the embodiment.

[Explanation of symbols]

 14 ... Logic circuit input processing means 15 ... Temporary placement and wiring means 16 ... Logic circuit information storage means 17 ... Wiring capacity calculation means 18 ... Virtual wiring simulation means A to H ... Hierarchical blocks Pa to Pd ... Coordinate points

Claims (1)

[Claims] 1. A logic circuit designed to be built into an integrated circuit can be input, and the operation of the logic circuit is verified before the completion of the design of actual placement and wiring of the logic circuit in the integrated circuit. In a CAD device for integrated circuit design capable of performing virtual wiring simulation for the above, circuit information indicating the input logic circuit is input in each of the hierarchical blocks in a form that can be discriminated from each other. The logic circuit information storage means for storing together with the input status information including at least the information to be input, and the input of the hierarchical block is accepted after the hierarchical block to be input is declared and input in advance, and the input is made in a form that can be distinguished as the hierarchical block. When the input of the logic circuit of the hierarchical block is completed, the circuit information is written in the logic circuit information storage means. A logic circuit input processing means for declaratively inputting the completion and writing the input status information of the hierarchical block based on the declarative input of the completion into the logic circuit information storage means, and a declarative input for completion of the input have already been made. A temporary placement and routing unit that performs temporary placement and routing of the hierarchical block and outputs the result as temporary placement and routing information; and wiring that obtains the wiring capacitance of the wiring in the logic circuit using the temporary placement and routing information. A capacitance calculation unit; and a virtual wiring simulation unit for performing the virtual wiring simulation using the wiring capacitance obtained by the wiring capacitance calculation unit. At least a part of the logic circuit input processing unit and the temporary placement wiring. At least a part of the means is realized by a single processing system, and the processing performed by the temporary placement and wiring means is realized.
A CAD device for designing an integrated circuit, characterized in that the CAD process is performed as a background process for the process performed by the logic circuit input processing means.