JPH07175726A - Memory device detecting mounting state and presence/ absence of fault - Google Patents

Abstract

PURPOSE:To provide a memory device which can easily detect the mounting state of a memory and also can make clear the factor of an error if detected. CONSTITUTION:This memory device is provided with a mounting state detecting part 2 which detects the mounting state and the presence/absence of faults of the memory and an error detecting part 3 which sends the detection information received from the part 2 to a microprocessor. Then the part 2 includes a sensor part 7 which detects the memory mounting state, a monitoring part 8 which always monitors the current flowing through a memory part 5 and notifies a fault is occurs, and a storage part 9 which stores the information on both parts 7 and 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for detecting the mounting state and the presence / absence of a failure.

[0002]

2. Description of the Related Art Conventionally, in this type of memory device, as shown in, for example, Japanese Patent Laid-Open No. 02-170767, memory expansion is performed so that there is no discontinuity in mounted memory addresses to simplify memory expansion and modification. I am trying. This device divides the basic memory block into two, and expands the installed memory on both upper and lower sides with respect to the direction of increasing the address and the direction of decreasing the address across the boundary, and when the expansion is completed, By making the overall addresses of the mounted memory consecutive, it is easy to add or change the memory.

However, in terms of the continuity of the mounted memory addresses, the condition is satisfied under the condition that the additional memory is not broken down. In order to know the presence or absence of the additional memory, the memory access means by the microprocessor is used. Data is written to a specific address in the memory, then data is read from the same address, read data and write data are compared, and when the data match, it is determined that the memory is mounted.

[0004]

This conventional memory device determines that the memory is not mounted when the memory itself has failed even though the additional memory is mounted. Therefore, it is difficult to detect the presence or absence of a memory failure when the memory is added.

[0005]

According to the present invention, there is provided a memory device for detecting the mounting state and the presence / absence of a failure. And an error detection unit for outputting to.

Further, in the memory device for detecting the mounting state and the presence / absence of failure of the present invention, the mounting state detecting section constantly monitors the sensor section for detecting the memory mounting state and the amount of current flowing in the memory to detect an abnormality. A monitoring unit for notifying and a storage unit for storing information on the sensor unit and the monitoring unit are provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a configuration diagram of a mounting state detection unit of this embodiment. Referring to FIG. 1 and FIG. 2, the memory device for detecting the mounting state and the presence / absence of a failure of this embodiment includes a mounting state detection unit 2 for detecting the memory mounting state and the presence / absence of a failure, and information from the mounting state detection unit 2. Is output to the microprocessor. In addition, the mounting state detection unit 2 includes a sensor unit 7 that detects a memory mounting state.
And a monitoring unit 8 that constantly monitors the amount of current flowing in the memory unit 5 to notify an abnormality, and a storage unit 9 that stores information on the sensor unit 7 and the monitoring unit 8.

The memory mounting signal 11 and the memory status signal 17 output from the memory unit 5 are always input to the mounting status detecting unit 2. The memory mounting signal 11 non-contactly detects whether or not the expansion memory is mounted in the socket for the expansion memory by using the photo sensor, and the sensor unit 7 as a potential difference indicating whether or not the expansion sensor blocks the photo sensor. Tell. The sensor unit 7 outputs the memory mounting signal 11 as the mounting detection signal 12. The memory status signal 17 is transmitted to the monitoring unit 8 as a current value flowing between the power supply and the ground of the expansion memory socket. This current value is expected to increase by a certain amount when the memory is normal, but shows an extremely large value when the memory is faulty or a value that hardly changes from that when not mounted. The monitoring unit 8 receives this current value and compares the upper limit value and the lower limit value of the normal range, and outputs a binary signal state detection signal 18 as normal if within the range and abnormal if not.

The mounting state detecting section 2 comprises a sensor section 7, a monitoring section 8 and a storage section 9. The sensor unit 7 converts an analog signal obtained from the memory mounting signal 11 into a binary signal. The converted binary signal indicates the presence or absence of the memory, and is output to the storage unit 9 and the error detection unit 3 as the mounting detection signal 12. The monitoring unit 8 converts the current value obtained from the memory status signal 17 into a binary signal using a comparator. The converted binary signal indicates whether the memory is normal or defective, and is output to the storage unit 9 and the error detection unit 3 as the state detection signal 18. The storage unit 9 stores the mounting detection signal 12 obtained from the sensor unit 7 and the monitoring unit 8.
And state detection signal 18 and memory select signal 15
A latch circuit that latches in synchronization with the memory access end signal 10, a logic circuit that determines the presence or absence of a memory and a failure state, and an adder circuit that calculates the mounted memory capacity.
Detects additional memory capacity. In this additional memory capacity detection method, data is latched in the latch circuit each time a memory access is performed, and the logic circuit receives the data and judges the memory mounting for each mounted memory size, and if the memory is mounted, the addition is performed. The memory size is transmitted to the circuit, and in response to this, the adder circuit calculates the mounting capacity. The calculated memory mounting capacity can be read via the data bus signal 16 from the address designated by the address signal 13 in the same manner as when accessing the peripheral device from the microprocessor 4.

The error detecting section 3 includes a mounting detection signal 12 and a state detection signal 1 obtained from the sensor section 7 and the monitoring section 8.
Know the memory failure based on 8. The mounting detection signal 12 and the state detection signal 18 make only the memory mounting signal 11 and the memory state signal 17 selected by the memory select signal 15 valid. This is because the memory mounting signal 11 and the memory status signal 17 are always output, so that the memory mounting signal 11 and the memory status signal 17 are valid only when the memory is accessed. Upon receiving the mounting detection signal 12 and the state detection signal 18, the storage unit 9 fetches and holds the value inside together with the memory select signal 15 in synchronization with the memory access end signal 10. Data is fetched in synchronization with the memory access end signal 10 because the delay time of the mounting detection signal 12 and the state detection signal 18 output by the sensor unit 7 and the monitoring unit 8 is taken into consideration so that the next memory access is performed. This is because the value is retained until it is reached. Upon receiving the mounting detection signal 12 and the state detection signal 18, the error detection unit 3 returns the result of the error determination to the microprocessor 4 as the status signal 14. Conventionally, the microprocessor 4 has been required to write, read, and compare data to and from the memory in order to detect the mounted state of the memory, but by using the present invention, it is only necessary to write or read data. The memory mounting status can be detected. When an error occurs by processing the status signal 14 as an interrupt signal, the error processing can be performed immediately. Further, like the memory, the storage unit 9 can specify the data bus signal 16 by designating a specific address.
The mounting detection signal 12 and the state detection signal 18 can be obtained via.

FIG. 3 shows the time series relationship of signals in this embodiment. Referring to FIG. 3 together with FIG. 1, when the memory is first accessed, the microprocessor 4 outputs the address signal 13 to specify the memory address.
In response to this, the memory select signal 15 outputs a signal permitting access only to the designated memory section 5. The mounting detection signal 12 and the state detection signal 18 are the memory access signal 1
The signal of the memory unit 5 which is validated by 5 is transmitted to the error detection unit 3. In response to this, the error detector 3 outputs the status signal 14 to the microprocessor 4. The data to be accessed next is output from the microprocessor 4 as the data bus signal 16. The memory access end signal 10 is output from the microprocessor 4 when the memory access is completed. The memory mounting signal 11 and the memory status signal 17 always change according to the memory mounting status regardless of other signals.

[0012]

As described above, according to the present invention,
By installing a mounting state detection unit that detects the mounted state of the memory and the presence or absence of a fault, and an error detection unit that outputs the information from this mounting state detection unit to the microprocessor, even if the memory is expanded, the fault occurs. Whether or not the memory is mounted can be accurately performed. Further, the presence or absence of a memory failure can always be detected without performing a means for comparing the memory write data of the microprocessor, and the secondary failure caused by the memory failure can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a mounting state detection unit of this embodiment.

FIG. 3 is a diagram showing a time-series relationship of signals in this embodiment.

[Explanation of symbols]

 1 memory mounting detection circuit 2 mounting state detection unit 3 error detection unit 4 microprocessor 5 memory unit 6 memory control unit 7 sensor unit 8 monitoring unit 9 storage unit 10 memory access end signal 11 memory mounting signal 12 mounting detection signal 13 address bus signal 14 status signal 15 memory select signal 16 data bus signal 17 memory status signal 18 status detection signal

Claims (2)

[Claims] 1. A mounting state and presence / absence of failure, comprising a mounting state detecting section for detecting a memory mounting state and presence / absence of failure, and an error detecting section for outputting information from the mounting state detecting section to a microprocessor. Memory device for detecting. 2. The mounting state detection unit includes a sensor unit that detects the mounting state of the memory, a monitoring unit that constantly monitors the amount of current flowing in the memory and reports an abnormality, and information on the sensor unit and the monitoring unit. The memory device for detecting the mounting state and the presence / absence of a failure according to claim 1, further comprising: