JPH07174963A - Range-finding device for camera - Google Patents

Range-finding device for camera

Info

Publication number
JPH07174963A
JPH07174963A JP32231893A JP32231893A JPH07174963A JP H07174963 A JPH07174963 A JP H07174963A JP 32231893 A JP32231893 A JP 32231893A JP 32231893 A JP32231893 A JP 32231893A JP H07174963 A JPH07174963 A JP H07174963A
Authority
JP
Japan
Prior art keywords
gain
circuit
current
light
subject
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32231893A
Other languages
Japanese (ja)
Other versions
JP3163405B2 (en
Inventor
Hiroyuki Saito
浩幸 斉藤
Akira Ito
顕 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP32231893A priority Critical patent/JP3163405B2/en
Publication of JPH07174963A publication Critical patent/JPH07174963A/en
Application granted granted Critical
Publication of JP3163405B2 publication Critical patent/JP3163405B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Measurement Of Optical Distance (AREA)
  • Focusing (AREA)
  • Automatic Focus Adjustment (AREA)

Abstract

PURPOSE:To rapidly perform the operation from starting light projection to the focusing of a photographing lens by deciding the gain of an amplifier circuit by performing preliminary light emission in the case of amplifying an optical signal from a subject, easily obtaining a subject distance from the decided gain, and focusing the photographing lens without starting normal light emission. CONSTITUTION:When a range-finding routine is started, the power sources of all the circuits are turned on, first. Next, a CPU 80 clears the contents of a storage device (RAM) 81 capable of reading/writing, and decides the optimum gains of the amplifier circuits 40 and 50. The gain is decided by the preliminary light emission. In the case of deciding that the subject is at a position within a certain distance while performing operation for deciding the gain, it is judged as being the closest without performing range-finding because a closest flag in the RAM 81 is set. Since values S1 and S2 are decided while performing the operation for deciding the gain, a lens barrel 86 is driven based on the moving amount of the photographing lens stored at the address of a ROM 82 univocally decided from the values.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、カメラなどの測距装
置、さらに詳しくはアクティブ式のカメラ用測距装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distance measuring device such as a camera, and more particularly to an active type distance measuring device for a camera.

【0002】[0002]

【従来の技術】従来からアクティブ式のさまざまな測距
装置が提案されているが、これらの測距装置において被
写体からの光信号を増幅する際に、まず数回投光して増
幅回路のゲインを決定し(以下、これを予備発光とい
う)、その後で投光回路をあらかじめ決められた回数あ
るいは時間だけ動作させ(以下これを本発光という)、
その出力結果から被写体までの距離を算出し、撮影レン
ズを合焦させていた。
2. Description of the Related Art Conventionally, various active distance measuring devices have been proposed, but when amplifying an optical signal from a subject in these distance measuring devices, first, the light is projected several times to gain the gain of an amplifier circuit. (Hereinafter, this is referred to as preliminary light emission), and thereafter, the light projecting circuit is operated for a predetermined number of times or time (hereinafter, this is referred to as main light emission),
The distance to the subject was calculated from the output result, and the taking lens was focused.

【0003】[0003]

【発明が解決しようとする課題】ところが前記のような
測距装置では、まず予備発光によって受光回路を構成す
る増幅回路の最適なゲインを決定し、さらに本発光によ
って被写体距離を算出するため、投光開始から撮影レン
ズの合焦までに非常に時間がかかり、ひいてはシャッタ
チャンスを逃す原因になっていた。
However, in the distance measuring device as described above, the optimum gain of the amplifier circuit constituting the light receiving circuit is first determined by the preliminary light emission, and the subject distance is calculated by the main light emission. It takes a very long time from the start of light to the focusing of the taking lens, which in turn causes a missed photo opportunity.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するた
め、本発明のカメラ用測距装置では、被写体へ光を照射
する投光手段と、前記投光手段の照射光が前記被写体で
反射する光を受光し2つの電流に変換する受光手段と、
前記受光手段の一方の出力電流を電圧に変換する第1の
電流電圧変換回路と、前記受光手段の他方の出力電流を
電圧に変換する第2の電流電圧変換回路と、前記第1ま
たは第2の電流電圧変換回路の出力を選択する選択手段
と、前記選択手段の選択した出力信号を増幅する増幅回
路と、前記増幅回路の出力信号を積分する積分回路と、
前記積分回路の出力信号を所定の信号と比較する比較手
段と、前記比較手段の比較結果に基づいて前記増幅回路
のゲインを調整するゲイン調整選択手段と、前記ゲイン
調整手段の調整結果に基づいて被写体までの距離信号を
得る演算手段とを備えている。
In order to solve the above problems, in the distance measuring apparatus for a camera according to the present invention, a light projecting means for irradiating a subject with light, and the light projected from the light projecting means is reflected by the subject. A light receiving means for receiving light and converting it into two currents;
A first current-voltage conversion circuit that converts one output current of the light-receiving means into a voltage; a second current-voltage conversion circuit that converts the other output current of the light-receiving means into a voltage; the first or second Selecting means for selecting the output of the current-voltage conversion circuit, an amplifier circuit for amplifying the output signal selected by the selecting means, and an integrating circuit for integrating the output signal of the amplifier circuit,
Based on a comparison unit that compares the output signal of the integration circuit with a predetermined signal, a gain adjustment selection unit that adjusts the gain of the amplification circuit based on the comparison result of the comparison unit, and an adjustment result of the gain adjustment unit. And a calculation means for obtaining a distance signal to the subject.

【0005】[0005]

【作用】被写体からの光信号を増幅する際に、予備発光
を行ない増幅回路のゲインを決定すると共に、そのゲイ
ンから被写体距離を簡易に求め、本発光に入ることなく
撮影レンズを合焦させる。
When the optical signal from the subject is amplified, preliminary light emission is performed to determine the gain of the amplifier circuit, and the subject distance is easily obtained from the gain to focus the photographing lens without entering the main light emission.

【0006】[0006]

【実施例】本発明の一実施例の構成を図1に基づいて説
明する。投光回路10は近赤外投光素子(以下IRED
という)14を駆動するための駆動回路であり、トラン
ジスタ11、ベース抵抗12、コレクタ抵抗13および
IRED14からなる。演算回路(以下CPUという)
80から投光信号が出力されると、IRED14は発光
する。発光した光は投光レンズ1を通り、不図示の被写
体によってその一部を反射され、反射した光の一部は受
光レンズ2を通って半導体位置検出素子(以下PSDと
いう)3に入射する。本発明ではIRED14はパルス
駆動される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. The light projecting circuit 10 is a near infrared light projecting element (hereinafter, IRED).
A driving circuit for driving a transistor 14, a base resistor 12, a collector resistor 13 and an IRED 14. Arithmetic circuit (hereinafter referred to as CPU)
When the light projection signal is output from 80, the IRED 14 emits light. The emitted light passes through the light projecting lens 1, a part thereof is reflected by a subject (not shown), and a part of the reflected light passes through the light receiving lens 2 and is incident on a semiconductor position detecting element (hereinafter referred to as PSD) 3. In the present invention, the IRED 14 is pulse-driven.

【0007】電流電圧変換回路20(遠距離側)と30
(近距離側)とはPSD3と一体となって受光回路を構
成する。PSD3に光信号が入射すると、PSD3はそ
の強度と入射位置に応じた電流を電流電圧変換回路20
と30に出力する。電流電圧変換回路20はアンプ21
と帰還抵抗22で構成された、入力電流に比例した電圧
を出力する回路であり、電流電圧変換回路30はアンプ
31と帰還抵抗32とを備え、電流電圧変換回路20と
まったく同じ構成で、信号電流に応じた電圧が出力さ
れ、スイッチ4に導かれる。
Current-voltage conversion circuits 20 (far side) and 30
(Near side) constitutes a light receiving circuit together with PSD3. When an optical signal is incident on the PSD 3, the PSD 3 generates a current according to its intensity and incident position in the current-voltage conversion circuit 20.
And output to 30. The current-voltage conversion circuit 20 has an amplifier 21.
Is a circuit configured to output a voltage proportional to an input current, the current-voltage conversion circuit 30 includes an amplifier 31 and a feedback resistor 32, and has the same configuration as the current-voltage conversion circuit 20. A voltage corresponding to the current is output and guided to the switch 4.

【0008】スイッチ4は電流電圧変換回路20および
30のいずれかの出力を後段の回路に伝える役割を有
し、その状態はCPU80によって制御される。遠距離
側の測距を行うときは電流電圧変換回路20、近距離側
の測距を行うときは電流電圧変換回路30側にオンす
る。
The switch 4 has a role of transmitting the output of one of the current-voltage conversion circuits 20 and 30 to a circuit in the subsequent stage, and its state is controlled by the CPU 80. When the distance measurement on the long distance side is performed, the current-voltage conversion circuit 20 is turned on, and when the distance measurement on the short distance side is performed, the current-voltage conversion circuit 30 side is turned on.

【0009】増幅回路40と50はゲイン切換の可能な
増幅回路である。これらの回路はまったく同様な構成な
ので、増幅回路40を例にとって説明する。増幅回路4
0の前にはカップリングコンデンサ5が接続され、入力
信号の直流分はここでカットされる。増幅回路40はア
ンプ41と3個の帰還抵抗で構成された、入力信号をあ
る一定のゲインで増幅する回路である。回路中にスイッ
チ46と47という2つのスイッチを備え、これらのス
イッチはCPU80によってオン/オフを制御できる。
スイッチ46は帰還抵抗43を、スイッチ47は帰還抵
抗43と帰還抵抗44とをそれぞれオン/オフするの
で、これらのスイッチの状態によりアンプ41のゲイン
が段階的に変化し、この変化したゲインに応じて増幅し
増幅回路50に出力される。増幅回路50もまったく同
様な動作をし、CPU80はスイッチ56と57を操作
して適切なゲインを設定し、それにしたがって増幅回路
40の出力した信号の増幅が行われる。増幅回路50の
出力信号はスイッチ7を経て後段の積分回路60に出力
される。
The amplifier circuits 40 and 50 are gain switchable amplifier circuits. Since these circuits have exactly the same configuration, the amplifier circuit 40 will be described as an example. Amplifier circuit 4
A coupling capacitor 5 is connected before 0, and the DC component of the input signal is cut off here. The amplifier circuit 40 is a circuit configured of an amplifier 41 and three feedback resistors, and amplifies an input signal with a certain gain. There are two switches 46 and 47 in the circuit, and these switches can be turned on / off by the CPU 80.
Since the switch 46 turns on / off the feedback resistor 43 and the switch 47 turns on / off the feedback resistor 43 and the feedback resistor 44, respectively, the gain of the amplifier 41 changes stepwise depending on the states of these switches, and the gain depending on the changed gain. It is amplified and output to the amplifier circuit 50. The amplifier circuit 50 also operates in exactly the same manner, and the CPU 80 operates the switches 56 and 57 to set an appropriate gain, and the signal output from the amplifier circuit 40 is amplified accordingly. The output signal of the amplifier circuit 50 is output to the integrating circuit 60 in the subsequent stage via the switch 7.

【0010】積分回路60はアンプ61、入力抵抗6
2、積分コンデンサ63、スイッチ64、電圧ホロワ6
5で構成された、入力電圧を時間積分するための回路で
ある。積分動作に先だって積分コンデンサ63に残って
いる電荷を放電するためスイッチ64がオンする。十分
に放電されるとスイッチ64はオフする。積分動作がス
イッチ7のオンによって開始されると、積分コンデンサ
63には入力信号の時間積分値が電荷として貯えられ
る。このときの積分コンデンサ63端子間電圧の値はコ
ンパレータ71に出力される。積分動作が終了するとス
イッチ7はオフする。
The integrating circuit 60 includes an amplifier 61 and an input resistor 6
2, integrating capacitor 63, switch 64, voltage follower 6
5 is a circuit configured to integrate the input voltage with time. Prior to the integration operation, the switch 64 is turned on to discharge the electric charge remaining in the integration capacitor 63. When fully discharged, the switch 64 turns off. When the integration operation is started by turning on the switch 7, the time integration value of the input signal is stored in the integration capacitor 63 as electric charge. The value of the voltage between the terminals of the integrating capacitor 63 at this time is output to the comparator 71. When the integration operation is completed, the switch 7 is turned off.

【0011】レベル判定回路70はコンパレータ71と
基準電源72とで構成された入力電圧のレベルを判定す
るための回路である。コンパレータ71は入力電圧の値
を基準電源72の電圧V1と比較し、入力電圧の方が高
ければ’H’レベル、入力電圧の方が低ければ’L’レ
ベルをCPU80に出力する。
The level determination circuit 70 is a circuit configured by a comparator 71 and a reference power source 72 for determining the level of the input voltage. The comparator 71 compares the value of the input voltage with the voltage V1 of the reference power source 72, and outputs the “H” level to the CPU 80 if the input voltage is higher, and outputs the “L” level to the CPU 80 if the input voltage is lower.

【0012】次に本発明の実施例の回路の動作について
説明する。この測距ルーチンに入ると、まず図1内のす
べての回路の電源をオンする。次にCPU80は読み書
き可能な記憶装置(以下RAMと言う)81の内容をク
リアし、増幅回路40と増幅回路50の最適なゲインを
決定する。このゲイン決定の動作の中で被写体がある距
離未満の位置にあると判定された場合はRAM81中の
至近フラグがセットされるので、その場合は測距を行わ
ずに至近と判定する。以上のゲイン決定の動作の中で、
値S1とS2とが定まるので、これらの値から一義的に
決定されるROM82のアドレスに格納されている撮影
レンズ駆動量に基づいて鏡筒86を駆動する。最後に測
距回路の電源をオフして、このルーチンを抜ける。
Next, the operation of the circuit according to the embodiment of the present invention will be described. When this distance measuring routine is entered, first, the power supplies of all the circuits in FIG. 1 are turned on. Next, the CPU 80 clears the contents of a readable / writable storage device (hereinafter referred to as RAM) 81 and determines the optimum gains of the amplification circuit 40 and the amplification circuit 50. If it is determined in this gain determination operation that the subject is at a position less than a certain distance, the close-up flag in the RAM 81 is set, and in that case, it is determined that the close-up is performed without performing distance measurement. Among the above gain determination operations,
Since the values S1 and S2 are determined, the lens barrel 86 is driven based on the photographing lens drive amount stored in the address of the ROM 82 that is uniquely determined from these values. Finally, the power of the distance measuring circuit is turned off, and this routine is exited.

【0013】次に、電流電圧変換回路20に対する増幅
回路40と増幅回路50のゲイン決定の動作を図2、図
3を使って説明する。最初にCPU80によってスイッ
チ4を電流電圧変換回路20側にオンする。スイッチ6
4をオンし、積分コンデンサ63にたまっている電荷を
放電させる(図2a)。十分に電荷を放電した後、スイ
ッチ64をオフし、そしてカウントリセット信号CRに
よってカウンタ83の値N1を0にクリアする(図2
b)。そしてCPU80は投光回路10を動作させ、投
光を開始する。投光開始に伴う各アンプの立ち上り時間
の確保と電源変動の影響とを軽減するため、投光後時間
T1を経過してから(図2c)、積分回路を時間T2の
間だけ動作させる。それが終わると投光および積分を停
止して(図2d)、時間T3の間だけ待機し(図2
e)、カウントアップ信号CUによってカウンタに1を
加える。
Next, the gain determining operation of the amplifier circuit 40 and the amplifier circuit 50 for the current-voltage conversion circuit 20 will be described with reference to FIGS. 2 and 3. First, the CPU 80 turns on the switch 4 to the current-voltage conversion circuit 20 side. Switch 6
4 is turned on to discharge the electric charge accumulated in the integrating capacitor 63 (FIG. 2a). After discharging the electric charge sufficiently, the switch 64 is turned off, and the value N1 of the counter 83 is cleared to 0 by the count reset signal CR (FIG. 2).
b). Then, the CPU 80 operates the light projecting circuit 10 to start light projecting. In order to secure the rise time of each amplifier due to the start of light emission and reduce the influence of power supply fluctuation, after the time T1 after light emission has passed (FIG. 2c), the integrating circuit is operated only for the time T2. After that, projection and integration are stopped (Fig. 2d), and the device waits for the time T3 (Fig. 2d).
e), 1 is added to the counter by the count-up signal CU.

【0014】図3のように、この動作をあらかじめ決め
られた回数Ng(たとえば10回)だけ繰り返した後、
積分コンデンサ63の端子間電圧すなわち積分電圧Vi
をコンパレータ71で基準電源72の電圧V1と比較し
てその結果をデジタル信号に変換してCPU80に出力
する。CPU80はコンパレータ71の出力がHレベル
ならば(図2f)、スイッチ46をオンする。以下同様
に、積分動作と比較演算とを繰り返し、コンパレータ7
1の出力がHレベルならスイッチ56、スイッチ47、
スイッチ57の順でオンする。もしもすべてのスイッチ
をオンしてもコンパレータ71の出力がHレベルなら至
近フラグをセットする。以上のようにして電流電圧変換
回路20にとって最適な増幅回路40と増幅回路50の
ゲインが決定される。
After repeating this operation for a predetermined number of times Ng (for example, 10 times) as shown in FIG.
The voltage between the terminals of the integrating capacitor 63, that is, the integrated voltage Vi
Is compared with the voltage V1 of the reference power source 72 by the comparator 71 and the result is converted into a digital signal and output to the CPU 80. When the output of the comparator 71 is H level (FIG. 2f), the CPU 80 turns on the switch 46. In the same manner, the integration operation and the comparison operation are repeated in the same manner, and the comparator 7
If the output of 1 is H level, switch 56, switch 47,
The switches 57 are turned on in this order. Even if all the switches are turned on, if the output of the comparator 71 is at H level, the near flag is set. As described above, the optimum gains of the amplification circuit 40 and the amplification circuit 50 for the current-voltage conversion circuit 20 are determined.

【0015】以上が本実施例における回路の動作であ
る。以上の動作をフローチャートで表わすと図5〜図7
のようになる。まず、メインルーチンを図5に基づいて
説明する。この測距ルーチンに入ると、CPU80は測
距回路全体の電源をオンし(#001)、RAM81の
内容をクリアする(#002)。次に電流電圧変換回路
20での最適ゲイン決定動作を行い、ゲインによって一
義的に定まる値S1を決定してRAM81に保存し(#
003)、さらに電流電圧変換回路30での最適ゲイン
決定動作を行い、ゲインによって一義的に定まる値S2
を決定してRAM81に保存する(#004)。次に至
近フラグの状態を確認し(#005)、もしセットされ
ていればDVを撮影が可能な最至近距離(たとえば0.
5m)に設定し(#006)、#008にジャンプす
る。ここでDVはRAM81中に予約された一定長の領
域である。至近フラグがセットされていなければ、RA
M81中の値S1の値と値S2の値とから参照すべきR
OM82のアドレスを生成し(#007)、そのアドレ
スに格納されている鏡筒86の駆動量を読み出してDV
にセットし(#008)、DVに基づいてモータ85を
制御して鏡筒86を合焦位置まで駆動する(#00
9)。最後に測距回路の電源をオフし(#010)、こ
のルーチンを抜けて露出作動に移る。
The above is the operation of the circuit in this embodiment. The above operation is shown in a flow chart in FIGS.
become that way. First, the main routine will be described with reference to FIG. When this distance measuring routine is entered, the CPU 80 turns on the power supply of the entire distance measuring circuit (# 001) and clears the contents of the RAM 81 (# 002). Next, the optimum gain determination operation in the current-voltage conversion circuit 20 is performed to determine the value S1 that is uniquely determined by the gain and save it in the RAM 81 (#
003), and further, the optimum gain determination operation in the current-voltage conversion circuit 30 is performed, and the value S2 uniquely determined by the gain is obtained.
Is stored in the RAM 81 (# 004). Next, the state of the closest flag is confirmed (# 005), and if it is set, the closest distance (for example, 0.
5m) (# 006) and jump to # 008. Here, DV is an area of a fixed length reserved in the RAM 81. If the near flag is not set, RA
R to be referred to from the value S1 and the value S2 in M81
The address of the OM 82 is generated (# 007), the drive amount of the lens barrel 86 stored at that address is read out, and the DV is read.
(# 008), the motor 85 is controlled based on DV to drive the lens barrel 86 to the in-focus position (# 00).
9). Finally, the power supply of the distance measuring circuit is turned off (# 010), and the routine is exited to start the exposure operation.

【0016】次に、各サブルーチン内での動作を説明す
る。まず値S1の決定のサブルーチンを図6に基づいて
説明する。値S1はRAM81中の適切なアドレスに保
持される1バイトのデータである。後段の増幅回路のゲ
イン決定のサブルーチンに入ると、CPU80はスイッ
チ4を電流電圧変換回路20側にオンし(#101)、
値S1を0にクリアし(#102)、スイッチ64をオ
ンし積分コンデンサ63にたまっている電荷を放電させ
て(#103)、カウンタ83の値N1を0にクリアす
る(#104)。
Next, the operation within each subroutine will be described. First, the subroutine for determining the value S1 will be described with reference to FIG. The value S1 is 1-byte data held at an appropriate address in the RAM 81. When entering the subroutine for determining the gain of the amplifier circuit in the subsequent stage, the CPU 80 turns on the switch 4 to the current-voltage conversion circuit 20 side (# 101),
The value S1 is cleared to 0 (# 102), the switch 64 is turned on to discharge the charge accumulated in the integrating capacitor 63 (# 103), and the value N1 of the counter 83 is cleared to 0 (# 104).

【0017】続いてCPU80によって投光回路10を
動作させ(#105)、時間T1だけ待機する(#10
6)と、スイッチ7をオンし積分動作をしながら(#1
07)、時間T2だけ待機する。この間積分コンデンサ
63には電荷が貯えられる(#108)。それから投光
回路10の動作を止めて投光動作を終了し、スイッチ7
をオフし積分動作を終えて(#109)、時間T3だけ
待機し(#110)、カウンタ83に1を加える(#1
11)。カウンタ83の値N1があらかじめ決められた
回数Ng未満ならば#105にジャンプする(#11
2)。値N1が回数Ng以上ならば積分電圧Viはコン
パレータ71に出力され、コンパレータ71はその電圧
を基準電源72の電圧V1と比較し、その結果電圧Vo
をCPU80に出力する(#113)。CPU80は電
圧Voのレベルを判断し(#114)、Hレベルであれ
ばメインルーチンに戻る。
Subsequently, the CPU 80 operates the light projecting circuit 10 (# 105) and waits for the time T1 (# 10).
6), the switch 7 is turned on to perform the integral operation (# 1
07), wait for time T2. During this time, electric charge is stored in the integrating capacitor 63 (# 108). Then, the operation of the light projecting circuit 10 is stopped to end the light projecting operation, and the switch 7
Is turned off to complete the integration operation (# 109), wait for time T3 (# 110), and add 1 to the counter 83 (# 1).
11). If the value N1 of the counter 83 is less than the predetermined number of times Ng, the process jumps to # 105 (# 11
2). If the value N1 is equal to or more than the number of times Ng, the integrated voltage Vi is output to the comparator 71, which compares the voltage with the voltage V1 of the reference power supply 72, and as a result, the voltage Vo.
Is output to the CPU 80 (# 113). The CPU 80 determines the level of the voltage Vo (# 114), and if it is at the H level, returns to the main routine.

【0018】電圧VoがLレベルだった場合、CPU8
0は値S1に1を加え(#115)、値S1が1に等し
いかどうかを確認し(#116)、等しければスイッチ
46をオンしてアンプ41のゲインをより小さくしてか
ら(#117)、#103にジャンプする。次に2に等
しいかどうかを確認し(#118)、等しければスイッ
チ56をオンしてアンプ51のゲインをより小さくして
から(#119)、#103にジャンプする。次に3に
等しいかどうかを確認し(#120)、等しければスイ
ッチ47をオンしてアンプ41のゲインをより小さくし
てから(#121)、#103にジャンプする。次に4
に等しいかどうかを確認し(#122)、等しければス
イッチ57をオンしてアンプ51のゲインをより小さく
してから(#123)、#103にジャンプする。値S
1の値が0から3のいずれでもなければ、RAM81中
の至近フラグをセットし(#124)、このサブルーチ
ンを抜け、メインルーチンに戻る。
When the voltage Vo is at L level, the CPU 8
For 0, add 1 to the value S1 (# 115), check whether the value S1 is equal to 1 (# 116), and if they are equal, turn on the switch 46 to reduce the gain of the amplifier 41 (# 117). ), Jump to # 103. Next, it is confirmed whether or not it is equal to 2 (# 118), and if they are equal, the switch 56 is turned on to further reduce the gain of the amplifier 51 (# 119), and the process jumps to # 103. Next, it is confirmed whether or not it is equal to 3 (# 120), and if they are equal, the switch 47 is turned on to further reduce the gain of the amplifier 41 (# 121), and the process jumps to # 103. Then 4
(# 122), and if they are equal, the switch 57 is turned on to further reduce the gain of the amplifier 51 (# 123), and the process jumps to # 103. Value S
If the value of 1 is neither 0 nor 3, the close flag in the RAM 81 is set (# 124), the process exits this subroutine and returns to the main routine.

【0019】次に値S2の決定のサブルーチンを図7に
示す。動作は値S1の決定の場合とほぼ同様であり、C
PU80はスイッチ4を電流電圧変換回路20側にオン
し、RAM81中の適切なアドレスに保持される1バイ
トのデータである値S2に1を加算しながら適切なゲイ
ンを決定する。このルーチンから抜ける際にはゲインに
よって一義的に定まる値S2が決定されているか、また
はRAM81中の至近フラグがセットされているかのい
ずれかである。
Next, FIG. 7 shows a subroutine for determining the value S2. The operation is almost the same as the case of determining the value S1, and C
The PU 80 turns on the switch 4 to the side of the current-voltage conversion circuit 20, and determines an appropriate gain while adding 1 to the value S2 which is 1 byte of data held at an appropriate address in the RAM 81. When exiting this routine, either the value S2 that is uniquely determined by the gain is determined, or the near-field flag in the RAM 81 is set.

【0020】本実施例では受光素子として2つの電極を
有するPSDを使用しているが、中間電極などを持つ3
つ以上の電極からなる受光素子、とりわけ分割フォトダ
イオード(SPD)などの素子を用いてもよいことは言
うまでもない。
In this embodiment, a PSD having two electrodes is used as a light receiving element, but a PSD having an intermediate electrode or the like is used.
It goes without saying that a light receiving element composed of one or more electrodes, especially an element such as a split photodiode (SPD) may be used.

【0021】また、本実施例では2つの電流電圧変換回
路が1つの増幅回路をスイッチによって共有している
が、それぞれの電流電圧変換回路に回路的に等価な別々
の増幅回路を接続し、これらの増幅回路のゲインを別々
に切り替え、そのようにして得られた2つのゲインから
距離信号を生成するようにしてもよい。
Further, in the present embodiment, the two current-voltage conversion circuits share one amplification circuit by the switch, but each current-voltage conversion circuit is connected with a separate amplification circuit which is equivalent to the circuit. The gain of the amplifier circuit may be switched separately, and the distance signal may be generated from the two gains thus obtained.

【0022】また、本実施例では積分回路の出力信号の
レベルをコンパレータによって判定しているが、アナロ
グ/デジタル変換器など別の比較手段を用いてもよい。
Further, in the present embodiment, the level of the output signal of the integrating circuit is judged by the comparator, but another comparing means such as an analog / digital converter may be used.

【0023】また、測距モードの切り換えを可能にする
スイッチを別に設け、そのスイッチを操作することで本
実施例に説明したような測距作動と通常の被写体距離を
求める測距作動とを選択的に使用できるようにしてもよ
い。
Further, a switch for changing over the distance measuring mode is separately provided, and by operating the switch, the distance measuring operation as described in this embodiment and the distance measuring operation for obtaining a normal object distance are selected. You may make it possible to use it.

【0024】[0024]

【発明の効果】本発明の構成によれば、被写体からの光
信号を増幅する際に、予備発光を行ない増幅回路のゲイ
ンを決定すると共に、そのゲインから被写体距離を簡易
に求め、本発光に入ることなく撮影レンズを合焦させる
ため、投光開始から撮影レンズの合焦までを極めて迅速
に行うことができ、シャッタチャンスに対して有利であ
る。また投光素子の駆動回数が少なくなり、消費電力も
少なくてすむ。
According to the structure of the present invention, when amplifying an optical signal from a subject, preliminary light emission is performed to determine the gain of the amplifier circuit, and the subject distance is easily obtained from the gain to realize main light emission. Since the photographic lens is focused without entering, the process from the start of light projection to the focusing of the photographic lens can be performed extremely quickly, which is advantageous for a photo opportunity. Further, the number of times the light emitting element is driven is reduced, and the power consumption can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of the present invention.

【図2】本発明の実施例の積分動作を説明する動作図で
ある。
FIG. 2 is an operation diagram illustrating an integration operation according to the embodiment of this invention.

【図3】本発明の実施例の増幅回路40と増幅回路50
のゲイン決定の方法を説明する動作図である。
FIG. 3 is an amplifier circuit 40 and an amplifier circuit 50 according to an embodiment of the present invention.
6 is an operation diagram illustrating a method of determining the gain of FIG.

【図4】本発明の実施例の値S1およびS2から距離を
求めるROM82上のテーブルである。
FIG. 4 is a table on a ROM 82 for obtaining a distance from values S1 and S2 according to the embodiment of the present invention.

【図5】本発明の実施例の動作を示すフローチャートで
ある。
FIG. 5 is a flowchart showing the operation of the embodiment of the present invention.

【図6】図5のフローチャートの値S1の決定の部分の
サブルーチンを示すフローチャートである。
FIG. 6 is a flowchart showing a subroutine of a part for determining a value S1 in the flowchart of FIG.

【図7】図5のフローチャートの値S2の決定の部分の
サブルーチンを示すフローチャートである。
FIG. 7 is a flowchart showing a subroutine of a part for determining a value S2 in the flowchart of FIG.

【符号の説明】[Explanation of symbols]

10 投光回路 3 PSD(受光素子) 20 電流電圧変換回路(遠距離側) 30 電流電圧変換回路(近距離側) 4 スイッチ 40 増幅回路 50 増幅回路 60 積分回路 70 レベル判定回路 80 CPU(演算手段) 10 Light emitting circuit 3 PSD (light receiving element) 20 Current-voltage conversion circuit (far distance side) 30 Current-voltage conversion circuit (short distance side) 4 Switch 40 Amplification circuit 50 Amplification circuit 60 Integration circuit 70 Level determination circuit 80 CPU (calculation means) )

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被写体へ光を照射する投光手段と、前記
投光手段の照射光が前記被写体で反射する光を受光し2
つの電流に変換する受光手段と、前記受光手段の一方の
出力電流を電圧に変換する第1の電流電圧変換回路と、
前記受光手段の他方の出力電流を電圧に変換する第2の
電流電圧変換回路と、前記第1または第2の電流電圧変
換回路の出力を選択する選択手段と、前記選択手段の選
択した出力信号を増幅する増幅回路と、前記増幅回路の
出力信号を積分する積分回路と、前記積分回路の出力信
号を所定の信号と比較する比較手段と、前記比較手段の
比較結果に基づいて前記増幅回路のゲインを調整するゲ
イン調整選択手段と、前記ゲイン調整手段の調整結果に
基づいて被写体までの距離信号を得る演算手段とを備え
たことを特徴とするカメラ用測距装置。
1. A light projecting means for irradiating a subject with light, and a light projecting means for receiving light reflected by the subject.
A light receiving means for converting into one current, and a first current-voltage conversion circuit for converting one output current of the light receiving means into a voltage,
A second current-voltage conversion circuit for converting the other output current of the light-receiving means into a voltage, selection means for selecting an output of the first or second current-voltage conversion circuit, and an output signal selected by the selection means. An amplifying circuit for amplifying the output signal of the amplifying circuit, a integrating circuit for integrating the output signal of the amplifying circuit, comparing means for comparing the output signal of the integrating circuit with a predetermined signal, and A distance measuring device for a camera, comprising: a gain adjustment selecting means for adjusting a gain; and a computing means for obtaining a distance signal to a subject based on an adjustment result of the gain adjusting means.
JP32231893A 1993-12-21 1993-12-21 Camera ranging device Expired - Fee Related JP3163405B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32231893A JP3163405B2 (en) 1993-12-21 1993-12-21 Camera ranging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32231893A JP3163405B2 (en) 1993-12-21 1993-12-21 Camera ranging device

Publications (2)

Publication Number Publication Date
JPH07174963A true JPH07174963A (en) 1995-07-14
JP3163405B2 JP3163405B2 (en) 2001-05-08

Family

ID=18142299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32231893A Expired - Fee Related JP3163405B2 (en) 1993-12-21 1993-12-21 Camera ranging device

Country Status (1)

Country Link
JP (1) JP3163405B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009287993A (en) * 2008-05-28 2009-12-10 Toto Ltd Human body detecting device and faucet device using it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009287993A (en) * 2008-05-28 2009-12-10 Toto Ltd Human body detecting device and faucet device using it

Also Published As

Publication number Publication date
JP3163405B2 (en) 2001-05-08

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