JPH07174813A - Element testing method - Google Patents

Abstract

PURPOSE:To recognize the contact condition of terminals of an element to be tested, and surely carry out a characteristic test by applying prescribed voltage to terminals for a signal channel and testing whether the detected voltage is the prescribed voltage or not. CONSTITUTION:Each terminal of an insulated gate bipolar transistor(IGBT) 10, an element to be tested, is so put as to be brought into contact with a terminal of a testing apparatus. Electric continuity of an emitter fourth terminal (a terminal for a signal channel) 22 and a gate return terminal 26 is checked. In a processing apparatus 52, a voltage generating circuit 32 supplied prescribed voltage to the terminal 26 and at the same time, a differential amplifier 44 controls as to amplify only the voltage of an input terminal connected to the terminal 22 of a resistor 34. When the value computed from the output signal of an ADC (A/D converter) 46 corresponds to the prescribed voltage supplied to the terminal 26, the terminals 26, 22 are electrically continued. When the value does not corresponds to the voltage, they are not electrically continued and the abnormality is displayed. Successively, following the processing procedure stored in the apparatus 52, prior testing is carried out to check the contact condition of each terminal of the IGBT 10 with each corresponding terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-test method for testing the characteristics of a device under test such as a semiconductor.

[0002]

2. Description of the Related Art An apparatus for testing the characteristics of an element such as a semiconductor includes a curve tracer and a parameter analyzer. In these test devices, the terminals of the device under test are brought into contact with the connection terminals of the test device, and the current flowing through the device under test when a predetermined voltage or current is supplied and the voltage at each terminal of the device under test are measured. The characteristics of the device under test are obtained according to these measurement results. Such a test device is disclosed, for example, in Japanese Examined Patent Publication No. 64-9595 and Japanese Examined Patent Publication No. 1-3770.
No. 1 and Japanese Patent Publication No. 3-75072.

[0003]

In order to surely test the characteristics of the device under test, it is necessary that each terminal of the device under test is surely in contact with the terminal of the test apparatus. But,
In the conventional test equipment, the test was performed on the assumption that the contact state is good, so if you get a bad test result, it is easy to determine whether the device under test is really defective or the contact state is the cause. I could not confirm.

Therefore, an object of the present invention is to provide an element test method for testing whether the terminals of the device under test are surely in contact with the terminals of the test apparatus before the characteristic test of the device under test.

[0005]

The element test method of the present invention is carried out in a test apparatus having a signal path terminal and a voltage detection terminal separately from the terminal of the element under test. When testing the characteristics of the device under test, a predetermined voltage is applied to the signal path terminal to test whether the voltage at the voltage detection terminal is the predetermined voltage. Then, when the voltage of the voltage detection terminal is not the predetermined voltage, it is determined that the abnormal state.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram of an element testing apparatus for carrying out the testing method of the present invention. In this embodiment, an insulated gate bipolar transistor (I
The present invention is not limited to the IGBT. IGBT 10 which is the device under test
Has a gate terminal 12, an emitter terminal 14 and a collector terminal 16. On the other hand, the contact terminal of the test device is a gate force terminal (signal path terminal) for the gate terminal 12.
18 and gate sense terminal (voltage detection terminal) 20
An emitter force terminal (signal path terminal) 22 for the source terminal 14, an emitter sense terminal (voltage detection terminal) 24 and a gate return terminal 26, and a collector force terminal (signal path) for the collector terminal 16. Terminal) 2
8 and a collector / sense terminal (voltage detection terminal) 30. These terminals are such that the terminals 18 and 20 conduct through the terminal 12 and the terminals 22, 24 and 26 conduct through the terminal 14 only when the device under test 10 correctly contacts the terminals of the test apparatus. 28 and 30 conduct through the terminal 16.

A gate bias voltage generating circuit 32 is inserted between the gate force terminal 18 and the gate return terminal 26. Further, between the emitter force terminal 22 and the collector force terminal 28, a collector current detecting resistor 34, a collector voltage source 36 and a collector load 3 are provided.
8 are connected in series. The differential amplifier 40 detects the voltage between the emitter / sense terminal 24 and the collector / sense terminal 30. The collector voltage that is this detection voltage is
A digital signal is converted by a digital converter (ADC) 42. The differential amplifier 44 detects the voltage drop of the resistor 34, that is, the voltage corresponding to the collector current of the IGBT 10, and the ADC 46 converts the detected voltage into a digital signal. The differential amplifier 48 also includes a gate / sense terminal 20.
The voltage between the emitter and the sense terminal 24, that is, the voltage between the emitter and the gate is detected, and the ADC 50 converts the detected voltage into a digital signal.

A processing unit 52 such as a personal computer receives the digital signals from the ADCs 42, 46 and 50 and controls the gate bias voltage generating circuit 32 and the collector voltage source 36. The input / output device 54 is
A keyboard, a display, etc. are used to input various commands to the processing device 52 and display the processing results. Also,
The differential amplifiers 40, 44 and 48 normally find the difference between the voltages at the two input terminals, but can also amplify only the voltage from one of the input terminals under the control of the processor 52.

FIG. 1 is an overall flow chart of the device testing method of the present invention. The microprocessor controls each circuit according to the processing procedure (program) stored in the processing device 52, and the respective ADCs control the circuits. Process digital signals. First, after the operator turns on the power of the test apparatus, the terminals of the IGBT 10 as the device under test are arranged so as to be in contact with the terminals of the test apparatus. (In the case of an automatic test apparatus, the device under test is automatically arranged.) In step 56, a preliminary test is performed to check whether each terminal of the IGBT 10 is surely contacted with the corresponding terminal of the test apparatus. This step 56 will be described in detail later. When it is confirmed in the pre-test of step 56 that the contact of the terminals is reliable, the process proceeds to step 58, and the characteristics of the IGBT 10 are tested. In this step 58, the differential amplifiers 40, 44 and 4 are responsive to the test procedure stored in the processor 52.
8 is operated as a differential amplifier to control the voltage amplitude and waveform generated by the gate / bias voltage generation circuit 32 and the value of the collector voltage source 36. In addition, ADC
The characteristics of the IGBT 10 are obtained according to the output signals of 42, 46 and 50, and the result is displayed on the display of the input / output device 54.

FIG. 2 is a detailed flow chart of step 56. In step 60, settings necessary for performing a preliminary test such as initializing each circuit are performed. In step (Test 1) 62, the emitter force terminal 22
Also, it is checked whether the gate / return terminal 26 is conductive. For this reason, the processing device 52 uses the voltage generating circuit 32.
Controls the terminal 26 to supply a predetermined voltage, and the differential amplifier 44 amplifies only the voltage of the input terminal from the left side of the resistor 34, that is, the input terminal connected to the emitter force terminal 22. To control. ADC4
If the value obtained from the output signal of No. 6 corresponds to the predetermined voltage supplied to the terminal 26, it means that the terminals 26 and 22 are conducting, the test 62 is passed (P), and the routine proceeds to step 66. However, if the value obtained from the output signal of the ADC 46 does not correspond to the predetermined voltage supplied to the terminal 26, it means that the terminal 26 is not conducting to 22. This is I
Ensure that the emitter terminal 14 of the GBT 10 has terminals 22 and 2
6 may not be in contact, or the IGBT 10 itself may be out of order. In this case, the test 62 has failed (F), and the process proceeds to step 64 to perform error processing such as displaying an abnormality on the display.

In step (test 2) 66, it is checked whether the emitter sense terminal 24 and the gate return terminal 26 are conducting. To this end, the processor 52
The voltage generation circuit 32 controls the terminal 26 to supply a predetermined voltage, and the differential amplifier 48 controls to amplify only the voltage of the input terminal connected to the emitter / sense terminal 24. If the value obtained from the output signal of the ADC 50 corresponds to the predetermined voltage supplied to the terminal 26, it means that the terminals 26 and 24 are conducting, and this test 6
Pass (P) 6 and proceed to step 70. In this case, since the step 62 has already been passed, the emitter terminal 14 of the IGBT 10 is surely in contact with all the terminals 22, 24 and 26. However, if the value obtained from the output signal of the ADC 50 does not correspond to the predetermined voltage supplied to the terminal 26, it means that the terminal 26 is not electrically connected to the terminal 24. This is because the emitter terminal 14 of the IGBT 10 is surely not in contact with the terminals 24 and 26.
It is possible that the device itself is out of order. in this case,
The test 66 is a failure (F), and the process proceeds to step 68 to perform error processing such as displaying an abnormality on the display.

In step (test 3) 70, it is checked whether the gate force terminal 18 and the gate sense terminal 20 are conducting. To this end, the processing device 52 controls the voltage generation circuit 32 to supply a predetermined voltage to the terminal 18, and the differential amplifier 48 controls only the voltage of the input terminal connected to the gate sense terminal 20. Control to amplify. The value obtained from the output signal of the ADC 50 is
If it corresponds to the predetermined voltage supplied to the terminal 18, the terminal 1
Since 8 and 20 are conductive, the test 70 is passed (P) and the process proceeds to step 74. However, ADC5
If the value obtained from the output signal of 0 does not correspond to the predetermined voltage supplied to the terminal 18, the terminal 18 is not conducting to 20. This is because the gate terminal 12 of the IGBT 10 is surely not in contact with the terminals 18 and 20.
It is possible that 10 itself is out of order. In this case, the test 70 has failed (F), and the process proceeds to step 72 to perform error processing such as displaying an abnormality on the display.

In step (test 4) 74, it is checked whether the collector force terminal 28 and the collector sense terminal 30 are conducting. Therefore, under the control of the processing device 52, the voltage generating circuit 32 reversely biases the IGBT 10 so that no collector current flows. Therefore, the load 38
The effect of will disappear. Further, the processing device 52 controls the collector voltage source 36 to supply a predetermined voltage to the terminal 28, and the differential amplifier 40 amplifies only the voltage of the input terminal connected to the collector / sense terminal 30. To control. If the value obtained from the output signal of the ADC 42 corresponds to the predetermined voltage supplied to the terminal 28, it means that the terminals 28 and 30 are conducting, the test 74 is passed (P), and the pre-test step 56 is performed. To finish. However, if the value obtained from the output signal of the ADC 42 does not correspond to the predetermined voltage supplied to the terminal 28, it means that the terminal 28 is not conducting to 30. This may be because the gate terminal 12 of the IGBT 10 is not surely in contact with the terminals 28 and 30, or the IGBT 10 itself is out of order. In this case, the test 74 is unsuccessful (F), and the process proceeds to step 76 to perform error processing such as displaying an abnormality on the display.

Although the preferred embodiment of the present invention has been described above, various modifications and changes can be made without departing from the spirit of the present invention. For example, the device under test may be a semiconductor device other than the IGBT. A test similar to the above-described preliminary test may be performed according to the number of terminals. Further, instead of changing the operation mode of the differential amplifier, a switch capable of selectively grounding its input terminal may be provided.

[0015]

As described above, according to the present invention, the contact state of the terminals is tested before the characteristics of the device under test are tested by the testing apparatus, so that the characteristics test can be reliably performed.

[Brief description of drawings]

FIG. 1 is an overall flow chart of the present invention.

2 is a detailed flow chart of step 58 of FIG.

FIG. 3 is a block diagram of a test apparatus to which the present invention is applied.

[Explanation of symbols]

 10 device under test 18, 22, 28 signal path terminal 20, 24, 30 voltage detection terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Usuda 5-9-31 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Tektronix Co., Ltd.

Claims (1)

[Claims] 1. A method for testing the characteristics of the device under test by a test apparatus having a signal path terminal and a voltage detection terminal for the terminals of the device under test, the method comprising: When testing, apply a predetermined voltage to the signal path terminal, test whether the voltage of the voltage detection terminal is the predetermined voltage, and if the voltage of the voltage detection terminal is not the predetermined voltage, an abnormal state A device test method characterized by determining that