JPH07169857A - Semiconductor device and semiconductor memory - Google Patents

Abstract

PURPOSE:To make wiring breadth larger and to lower the resistance by forming first power wiring for supplying drive power above a group of cells, causing second power wiring stretching in a direction perpendicular to this to pass just above the group of cells, and causing third power wiring perpendicular to this second power wiring to pass just above the group of cells. CONSTITUTION:High-potential side power lines Vcc11 and Vcc12 formed in the fourth one of polysilicon layers in parallel with a high-potential side power source Vcc are connected to memory cells. In a memory cell array 2, high- potential side power lines Vcc31 and Vcc32 and backed lines U1-U4 are formed in parallel with the high-potential side power line Vcc. The high-potential side power lines Vcc31 and Vcc32 are arranged at positions corresponding to the high-potential side power lines Vcc11 and Vcc12. Furthermore, in memory cell array 2 high-potential side power lines Vcc21-Vcc23 are formed in a direction perpendicular to the high-potential side power line Vcc. Besides, the high- potential side power lines Vcc21-Vcc23 are connected to the high-potential side power line Vcc through a contact hole 62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly to a semiconductor device and a semiconductor memory device capable of stabilizing a driving power supply supplied to a cell.

In recent years, semiconductor devices and semiconductor memory devices have been required to have large capacity, high speed, and low power consumption. Further, it is required to lower the drive voltage of the device. Therefore, it is important to suppress the voltage drop due to the wiring resistance inside the device.

[0003]

2. Description of the Related Art FIG. 7 shows a TFT (Thin Film Transistor).
FIG. 5 is a layout diagram of a memory cell array in which thin film transistor) load type memory cells are arranged. The memory cell array includes a plurality of bit line pairs BL1 and bars BL1 to BL1.
0, bar BL10 and a plurality of selected word lines WL11 to W
L14 and a plurality of high-potential-side power supply lines Vcc11 and Vcc12 are provided, and each memory cell C is connected to the bit line pair, the selected word line, and the high-potential-side power supply line. As the wiring layers of this memory cell array, first to fourth layers of polysilicon, and first and second layers of aluminum thereabove are provided.

The plurality of selected word lines WL11 to WL14 are formed in the first layer of polysilicon and have a high potential power supply line Vcc1.
1, Vcc12 are formed in the fourth layer of polysilicon. A plurality of bit line pairs BL1, bars BL1 to BL10, bar B
L10 is formed in the aluminum first layer, and high-potential-side power supply lines Vcc21 to Vcc23 are formed in parallel with the bit line pair in the aluminum first layer.

Further, the main word line WL is provided in the memory cell array.
1 and a plurality of back lining lines U1 to U4 are provided, and the main word line WL1 and the plurality of back lining lines U1 to U4 are made of aluminum second.
Formed in layers. The main word line WL1 is connected to a section selector (not shown) connected to each of the selected word lines WL11 to WL14, and the selected word lines WL11 to WL1 are selected based on the selection signal input to the section selector.
Select one of the four.

The back U1 to U4 are selected word lines WL1
1 to WL14 are provided corresponding to the selected word line WL1
1 to WL14 are short-circuited. Uchiuchi U1 to U
4 reduces the apparent resistance value of the selected word lines WL11 to WL14 and reduces the signal delay due to the selected word lines WL11 to WL14.

A high potential power supply line Vcc is formed in the second aluminum layer around the memory cell array. The high potential side power supply line Vcc is connected to the high potential side power supply lines Vcc21 to Vcc23. The high-potential-side power supply lines Vcc11 and Vcc12 are connected to each other through a contact hole 83 at the intersection with the high-potential-side power supply lines Vcc21 to Vcc23. A power supply pad (not shown) is connected to the high potential side power supply line Vcc, and drive power is supplied to the high potential side power supply line Vcc via the power supply pad.

The supplied driving power source is the high potential side power source line V
It is supplied to the memory cell C from cc through the high potential side power source lines Vcc21 to Vcc23 and the high potential side power source lines Vcc11 and Vcc12.
Then, the memory cell C stores information of "1" or "0" based on the supplied driving power source.

FIG. 5 shows a TFT load type memory cell. A flip-flop circuit is formed by connecting the gate terminals of driver transistors 20 and 21 which are N-channel MOS transistors formed on a semiconductor substrate to the drain terminals of the other driver transistor.

P-channel TFTs 25 and 26 are connected to the drain terminals of the driver transistors 20 and 21 as loads, respectively. The channel layers 28 and 30 of the TFTs 25 and 26 are the driver transistors 20 and 21.
Respectively connected to the drain terminals of. TFT 25
The gate electrode layer 27 is connected to the drain terminal of the driver transistor 21, and the gate electrode layer 29 of the TFT 26 is connected to the drain terminal of the driver transistor 20.

The TFT 25 and the driver transistor 20 are connected between the high potential side power source Vcc and the low potential side power source Vss, and the TFT 26 and the driver transistor 21 are connected.
Are connected between the high potential side power source Vcc and the low potential side power source Vss. Further, N is provided between the drain terminal of the driver transistor 20 and the bit line BL1, and between the drain terminal of the driver transistor 21 and the bit line bar BL1.
Gate transistors 22 and 23, which are channel MOS transistors, are connected. Each gate transistor 2
The gate terminals of 2 and 23 are connected to the selected word line WL11.

FIG. 6 shows a sectional view of a conventional TFT load type memory cell. An N-type drain region 71 and a source region (not shown) are formed in the P-type well 70 formed on the N-type semiconductor substrate. On the channel between the drain region 71 and the source region, a gate layer 73 made of polycide is formed on the first polysilicon layer via an insulating layer 72.
Are formed. The drain region 71, the source region and the gate layer 73 allow the driver transistors 20, 2
1 is formed.

An N-type source region 74 and a drain region 75 are formed in the P-type well 70. On the channel between the source region 74 and the drain region 75, a selected word line WL11 as a gate layer made of polycide is formed in the first polysilicon layer via an insulating layer 72. The gate transistors 22 and 23 are formed by the source region 74, the drain region 75 and the selected word line WL11.
Are formed.

On the gate layer 73, a low potential power supply line Vss made of polycide is formed as a second layer of polysilicon. The gate electrode layers 76 and 77 of the third polysilicon layer are formed above the low potential side power supply line Vss.
The gate electrode layer 77 includes the gate layer 73 and the source region 74.
Connected to. A P-type channel layer 78 is formed as a fourth polysilicon layer above both gate electrode layers 76 and 77. The TFTs 25 and 26 are formed by the two gate layer electrodes 76 and 77 and the channel layer 78.

A source region 79 and a drain region 80 are formed in the channel layer 78. The source region 78 is also the high potential side power supply line Vcc formed on the fourth layer of polysilicon.
It is connected to the. The drain region 80 is connected to the gate layer 73 and the source region 74 via the gate electrode layer 77. A bit line BL1 as a first aluminum layer is formed on the channel layer 78 via an insulating layer 72. The bit line BL1 is connected to the drain region 75 via a contactor 81 formed in the second layer of polysilicon.

An insulating layer 82 is formed above the bit line BL1. Then, on the insulating layer 82, a main word line WL1 as a second layer of aluminum and a back line U1 are formed in a direction orthogonal to the bit line BL1 (front and back directions in the drawing). The back line U1 is connected to the selected word line WL11 formed in the first polysilicon layer.

[0017]

By the way, the resistance value of the fourth layer of polysilicon in which the high potential side power supply lines Vcc11 and Vcc12 are formed is the same as that of the aluminum wiring layer in which the high potential side power supply lines Vcc and Vcc21 to Vcc23 are formed. High compared to resistance. Therefore, the resistance value from the power supply pad to the contact hole 83 depends on the resistance value of the high potential side power supply line Vcc and the high potential side power supply line Vcc21.
It becomes almost equal to the sum of the resistance values of Vcc23. The driving power supplied to the memory cell C is the high potential power supply line Vcc.
And a voltage drop occurs depending on the resistance value of Vcc21 to Vcc23.

As a result, in order to sufficiently drive the memory cell C, the driving voltage thereof is set to the high potential side power source lines Vcc and Vcc.
It is necessary to supply the power supply pad with a voltage that drops by 21 to Vcc23. As a result, there is a problem in that the higher the resistance value of the high-potential-side power supply lines Vcc and Vcc21 to Vcc23, the higher the drive power supply voltage that must be supplied to the semiconductor memory.

In order to suppress the voltage drop, the high potential power supply line Vc
The line widths of c and Vcc21 to Vcc23 may be thickened. But,
When the line width of the high-potential-side power supply line Vcc is made thick, there is a problem that the chip must be made large in accordance with the thickened line width. In addition, the high potential side power supply line Vcc21 to Vcc23
If the line width of is increased, the high-potential-side power supply lines Vcc21 to Vcc23
And bit line pair BL1, bar BL1 to BL10, bar BL
The distance from 10 must be kept at a predetermined distance.
As a result, there is a problem in that the space for arranging the memory cells C must be widened, and the region for arranging the memory cells C becomes large and the semiconductor memory device itself becomes large.

The present invention has been made to solve the above problems, and its purpose is to increase the effective wiring width of the power supply wiring and to reduce the resistance thereof. To provide.

[0021]

In order to achieve the above object, the present invention provides a first power supply wiring Vcc formed of a conductor for supplying driving power to each cell of a cell group formed on a semiconductor substrate. Is formed above the cell group, and second power supply wirings Vcc21 to Vcc23 made of a conductor and extending in a direction orthogonal to the first power supply wiring Vcc are formed so as to pass directly above the cell group. 1st and 2nd power supply wiring Vcc,
In a semiconductor device in which Vcc21 to Vcc23 are connected to each other, third power supply lines Vcc31 and Vcc which extend orthogonally to the second power supply lines Vcc21 to Vcc23 and are made of a conductor.
32 is formed so as to pass directly above the cell group, and the second power supply wirings Vcc21 to Vcc23 and the third power supply wirings Vcc31, Vcc are formed.
Connected to 32.

[0022]

Therefore, according to the present invention, the first power supply wiring Vcc made of the conductor for supplying the driving power to each cell of the cell group formed on the semiconductor substrate is formed above the cell group. At the same time, second power supply wirings Vcc21 to Vcc23 formed of conductors and extending in a direction orthogonal to the first power supply wiring Vcc are formed so as to pass directly above the cell group, and the first and second power supply wirings Vcc and Vcc21 are formed. .About.Vcc23 in a semiconductor device connected to each other, a third power supply wiring V which extends orthogonally to the second power supply wirings Vcc21 to Vcc23 and is made of a conductor.
cc31 and Vcc32 are formed so as to pass directly above the cell group,
Second power supply wiring Vcc21 to Vcc23 and third power supply wiring Vcc3
1, Vcc32 was connected. As a result, the line width of the power supply wiring can be made substantially thicker, and the value of the wiring resistance can be lowered.

[0023]

EXAMPLES The present invention will now be described with reference to a TFT load type memory cell C.
An embodiment embodied in a static RAM (SRAM) in which is arranged will be described with reference to FIGS. In addition, TFT
The circuit diagram of the load-type memory cell is the same as the conventional one, so that the description thereof will be omitted with reference to FIG.

FIG. 1 shows an SRAM 1, in which a row selection circuit 3 is connected to the memory cell array 2. The row selection circuit 3 inputs the predetermined bits A0 to A7 of the address signal via the address buffer 4. The row selection circuit 3 decodes the input address signals A0 to A7 and selects a predetermined word line of the memory cell array 2.

FIG. 2 is a partial circuit diagram for explaining the word lines of the row selection circuit 3. Only the signal lines necessary for the explanation are shown, and other signal lines and the like are omitted. The row selection circuit 3 is provided with a row decoder 3a and section selectors 3b to 3e. The memory cell array 2 includes the main word line WL1 output from the row decoder 3a and the selected word lines WL11 to WL14 output from the section selectors 3b to 3e.
It is connected to the. The row decoder 3a is adapted to select a predetermined main word line WL1 of the memory cell array 2 based on the inputted address signals A0 to A7.

The main word line WL1 and block selection lines SL1 to SL4 are connected to the inputs of the section selectors 3b to 3e, respectively. The selected word line W is output to the section selectors 3b to 3e.
L11 to WL14 are connected to the selected word line WL1
A memory cell C is connected to 1 to WL14. The memory cell C is a TFT type load memory cell shown in FIG. Back word lines U1 to U4 are provided for the selected word lines WL11 to WL14.
Are connected respectively.

For the selected word lines WL11 to WL14, the movement of the voltage of the selected word line is determined by the delay time based on the resistance value and parasitic capacitance of the selected word line. Therefore, apparently selected word lines WL11 are formed by forming back-out lines U1 to U4 having a resistance value lower than that of the selected word lines WL11 to WL14 and short-circuiting the back-out lines U1 to U4 and the selected word lines WL11 to WL14. The resistance value of WL14 is lowered to improve the speed of selecting the memory cell C.

Then, the section selectors 3b to 3e select the selected word lines WL11 to WL14 based on the states of the main word line WL1 and the block selection lines SL1 to SL4. Then, the selected selected word lines WL11 to WL
The information of the memory cell C connected to 14 is read.

Further, as shown in FIG. 1, a column selection circuit 6 is connected to the memory cell array 2 via a column input / output (I / O) circuit 5. The column selection circuit 6 transmits predetermined bits A8 to A8 of the address signal via the address buffer 7.
Enter A15. The column selection circuit 6 decodes the input address signals A8 to A15 to decode the memory cell array 2
The predetermined bit line pair is selected.

Write control circuit 10 composed of an AND circuit
Inputs the write enable signal bar WE and the chip select signal bar CS. In the write control circuit 10, when the write enable signal bar WE is at H level, the chip select signal bar C
When S is at L level, an H level write control signal is output.

The chip selection circuit 11 composed of an AND circuit inputs the write enable signal bar WE and the chip select signal bar CS. The chip selection circuit 11 outputs a control signal based on the write enable signal bar WE and the chip selection signal bar CS to the column I / O circuit 5.

An input data control circuit 8 is connected to the column I / O circuit 5. When the H level write control signal is input from the write control circuit 10, the input data control circuit 8 inputs a plurality of bits of data I1 to I4 via the data buffer 9. The input data control circuit 8 outputs the input data I1 to I4 to the column I / O circuit 5.

The column I / O circuit 5 is a chip selection circuit 11
When data is input from the input data control circuit 8 in the state where the control signal of H level is input to the memory cell array 2 through the bit line pair selected by the column selection circuit 6. Write.
Further, the column I / O circuit 5 reads out data from the memory cell array 2 via the bit line pair selected by the column selection circuit 6 when the L level control signal is input from the chip selection circuit 11. The column I / O circuit 5 outputs the read data O1 to O4.

The memory cell array 2 is shown in FIG. A high potential side power supply line Vcc is formed in the second layer of aluminum around the memory cell array 2. The high-potential-side power supply line Vcc is connected to a power supply pad (not shown), and drive power is supplied to the power supply pad from outside the SRAM 1.

In the memory cell array 2, a plurality of columns of memory cells C are arranged in parallel with the high potential side power source line Vcc at a predetermined interval. As the wiring layers of the memory cell array 2, first to fourth layers of polysilicon, and first and second layers of aluminum thereabove are provided. The memory cell C is connected to the high potential side power source lines Vcc11 and Vcc12 formed in the fourth layer of polysilicon in parallel with the high potential side power source line Vcc. Further, the memory cell C has a high potential side power supply line Vcc, V
Selected word lines WL11 to WL14 formed of polycide are connected to the first layer of polysilicon along cc11 and Vcc12.

The memory cell array 2 has a second aluminum
Main word line WL1 formed in a layer, high-potential-side power supply line Vcc
31, Vcc32 and the back lines U1 to U4 are the high-potential-side power line V
It is formed parallel to cc. The back lines U1 to U4 are arranged corresponding to the selected word lines WL11 to WL14 and short-circuited with the selected word lines WL11 to WL14, respectively. The high potential side power supply lines Vcc31 and Vcc32 are arranged at positions corresponding to the high potential side power supply lines Vcc11 and Vcc12.

Further, in the aluminum first layer of the memory cell array 2, a plurality of bit line pairs BL1 and bars BL1 to BL1 are provided.
10, bar BL10 and high potential side power source line Vcc21 to Vcc23
Are formed in a direction orthogonal to the high potential side power supply line Vcc. Bit line pair BL1, bars BL1 to BL1
0 and bar BL10 are connected to the memory cell C, respectively.

The high potential side power supply lines Vcc21 to Vcc23 are connected to the high potential side power supply line Vcc through a contact hole 62. Further, the high potential side power source lines Vcc21 to Vcc23 and the high potential side power source lines Vcc11, Vcc12, Vcc31, Vcc32 are connected by contact holes 60, 61 at their intersections.

Therefore, the high potential side power supply lines Vcc11, Vcc12,
Vcc31 and Vcc32, high-potential-side power supply lines Vcc21 to Vcc23, and contact holes 60 and 61 are formed in a grid pattern. FIG. 4 shows a sectional view of the memory cell C. An N type drain region 41 and a source region (not shown) are formed in the P type well 40 formed on the N type semiconductor substrate. On the channel between the drain region 41 and the source region, a gate layer 43 made of polycide is formed as the first polysilicon layer via an insulating layer 42. The driver regions 20 and 21 are formed by the drain region 41, the source region and the gate layer 43.

An N type source region 44 and a drain region 45 are formed in the P type well 40. On the channel between the source region 44 and the drain region 45, the selected word line WL11 as a gate layer made of polycide is formed in the first polysilicon layer via the insulating layer 42. The gate transistors 22 and 23 are formed by the source region 44, the drain region 45, and the selected word line WL11.
Are formed.

On the gate layer 43, a low potential side power source line Vss made of polycide is formed as a second layer of polysilicon. Above the low-potential-side power supply line Vss, gate electrode layers 46 and 47 of the third polysilicon layer are formed.
The gate electrode layer 47 includes the gate layer 43 and the source region 44.
Connected to. A P-type channel layer 48 is formed as a fourth polysilicon layer above both gate electrode layers 46 and 47. The TFTs 25 and 26 are formed by the two gate layer electrodes 46 and 47 and the channel layer 48.

A source region 49 and a drain region 50 are formed in the channel layer 48. The source region 48 is also the high potential side power supply line Vcc formed on the fourth layer of polysilicon.
11, connected to Vcc12. The drain region 50 is connected to the gate layer 43 and the source region 44 via the gate electrode layer 47. The insulating layer 4 is formed on the channel layer 48.
Bit line BL1 as the aluminum first layer
Are formed. Further, on the channel layer 48, the high potential side power source lines Vcc21 to Vcc23 and the bit line bar BL (not shown) are shown.
1 is formed in parallel with the bit line BL1. The bit line BL1 is a contactor 5 formed in the second layer of polysilicon.
1 to the drain region 45. The high-potential-side power supply lines Vcc21 to Vcc23 are connected to high-potential-side power supply lines Vcc11 and Vcc12 formed in the fourth layer of polysilicon through contact holes (not shown).

An insulating layer 52 is formed above the bit lines BL1, bar BL1 and the high potential side power source lines Vcc21 to Vcc23. Then, on the insulating layer 52, a main word line WL1, a back wire U1 and a high potential side power supply line Vcc31 as a second layer of aluminum are formed in a direction orthogonal to the bit line BL1. The back line U1 is connected to the selected word line WL11 formed in the first polysilicon layer. The high potential side power supply line Vcc31 is connected to the high potential side power supply lines Vcc21 to Vcc23 formed on the aluminum first layer.

In the SRAM 1 having the above-described structure, in the normal read operation of the SRAM 1, the row decoder 3a of the row selection circuit 3 first selects the main word line WL1 based on the address signals A0 to A7. Then, the block selectors SL1 to S are selected by the section selectors 3b to 3e.
Any one of the selected word lines WL11 to WL11 based on L4
Select WL14. Further, the column selection circuit 6 selects a predetermined bit line pair based on the address signals A8 to A15, and the information of the memory cell C connected to the selected word line WL11 to WL14 and the selected bit line pair is read. Be done.

Further, in the normal write operation of the SRAM 1, the row decoder 3a of the row selection circuit 3 causes the address signal A0.
~ Main word line WL1 is selected based on A7. Then, the section selectors 3b to 3e select any one of the selected word lines WL11 to WL14 based on the block selection lines SL1 to SL4. On the other hand, the column selection circuit 6 selects a predetermined bit line pair based on the address signals A8 to A15. And the column I / O circuit 5
Thus, the write operation is performed by setting one of the selected bit line pairs to the H level and the other to the L level.

At this time, driving power is externally supplied to the power pad of the SRAM 1. The driving power source is from the power source pad to the high potential side power source lines Vcc, Vcc21 to Vcc.
It is supplied to the memory cell C via 23, Vcc31, Vcc32 and Vcc11, Vcc12.

As described above, in this embodiment, the high potential side power source lines Vcc31 and Vcc32 are formed in the aluminum second layer in the direction perpendicular to the high potential side power source lines Vcc21 to Vcc23 formed in the aluminum first layer, Both power supply lines Vcc21 to Vcc23, Vcc3
1, Vcc32 was connected through a contact hole 61. The resistance value between the contact holes 61 is equal to both power supply lines Vcc21 to Vcc23,
The resistance value is obtained by connecting Vcc31 and Vcc32 in parallel, and the value is the power supply line Vcc21 to Vcc23, V between the contact holes 61.
It is lower than the resistance value of cc31 and Vcc32 alone. As a result, the substantial line width of the high-potential-side power supply line supplied to the memory cell C can be thickened and the resistance value can be lowered, so that the voltage drop of the driving power supply can be suppressed.

Further, since the high potential side power source lines Vcc31 and Vcc32 are formed above the memory cell array, the high potential side power source line Vcc.
It is possible to reduce the value of the wiring resistance without increasing the thickness, and it is not necessary to increase the size of the semiconductor memory device itself.

The present invention is not limited to the above embodiments, but may be carried out in the following modes. (1) In this embodiment, the application was made to the SRAM using the TFT load type memory cell C. However, the SRAM using the complete CMOS type 6 transistor cell or the high resistance polysilicon load type E / R cell is used.
It may be applied to RAM. In addition, dynamic RAM (D
It may be applied to a RAM) or various ROMs (Read Only Memory).

(2) Although the present embodiment is applied to the SRAM, it may be applied to other semiconductor devices such as a gate array. In addition, MPU (Micro Processing) with built-in SRAM
Unit) and other semiconductor devices.

(3) In this embodiment, the high potential side power source line Vc
Although c, Vcc21 to Vcc23, Vcc31, and Vcc32 are formed in the aluminum first layer and the second layer, the layers to be formed may be appropriately changed and formed. Alternatively, a third aluminum layer may be provided and the high potential side power source line may be formed in that layer.

[0052]

As described in detail above, according to the present invention,
There is an excellent effect that the wiring width of the power supply wiring can be substantially widened and the resistance can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a static RAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating divided word lines according to an embodiment.

FIG. 3 is a layout diagram illustrating a signal line around a memory cell according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a TFT load type memory cell showing an embodiment.

FIG. 5 is a circuit diagram showing a TFT load type memory cell of one embodiment.

FIG. 6 is a cross-sectional view of a conventional TFT load type memory cell.

FIG. 7 is a layout diagram illustrating a signal line around a conventional memory cell.

[Explanation of symbols]

Vcc First high potential side power supply line Vcc21 to Vcc23 Second high potential side power supply line Vcc31, Vcc32 Third high potential side power supply line 2 Memory cell array 20, 21 Driver transistor 25, 26 Thin film transistor (TFT) 27, 29 Gate Electrode layer 28, 30 Channel layer C Memory cell BL1, bar BL1 to BL10, bar BL10 Bit line WL11 to WL14 Word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/04 21/822 29/786 H01L 27/04 D 9056-4M 29/78 311 C

Claims (7)

[Claims] 1. A first conductor comprising a conductor for supplying drive power to each cell of a cell group formed on a semiconductor substrate.
Power supply wiring (Vcc) is formed above the cell group, and second power supply wirings (Vcc21 to Vcc23) extending in a direction orthogonal to the first power supply wiring (Vcc) and made of a conductor are directly above the cell group. In a semiconductor device in which the first and second power supply wirings (Vcc, Vcc21 to Vcc23) are connected to each other, so that they are orthogonal to the second power supply wirings (Vcc21 to Vcc23). Third power supply wiring (Vcc31, Vcc) that extends and is made of a conductor
32) is formed so as to pass directly above the cell group, and the second
Power supply wiring (Vcc21 to Vcc23) and third power supply wiring (Vcc
31, Vcc32) connected to a semiconductor device. 2. The third power supply wiring (Vcc31, Vcc32)
The semiconductor device according to claim 1, wherein is formed in a wiring layer different from the second power supply wiring (Vcc21 to Vcc23). 3. A first power supply wiring (Vcc) made of a conductor for supplying drive power to each memory cell (C) of the memory cell array (2) formed on a semiconductor substrate is connected to the memory cell array (2). ) And extending in a direction orthogonal to the first power supply wiring (Vcc) and including second power supply wirings (Vcc21 to Vcc23) made of a conductor so as to pass directly above the memory cell array (2). In a semiconductor memory device in which the first and second power supply wirings (Vcc, Vcc21 to Vcc23) are connected to each other, the semiconductor storage device extends perpendicularly to the second power supply wirings (Vcc21 to Vcc23) and has a conductor. Third power supply wiring (Vcc31, Vcc
32) is formed so as to pass directly above the memory cell array (2), and is connected to the second power supply wiring (Vcc21 to Vcc23) and the third power supply wiring (Vcc21 to Vcc23).
2. A semiconductor memory device characterized by being connected to the power supply wiring (Vcc31, Vcc32) of. 4. A plurality of bit lines formed of a conductor immediately above the memory cell array (2) and extending in a direction orthogonal to the first power supply wiring (Vcc) and connected to each memory cell (C). (BL1, bars BL1 to BL10,
Bar BL10) is formed, and the bit line (BL1, bar BL is formed directly above the memory cell array (2).
1 to BL10, BL10) and a plurality of word lines (WL11 to WL14) made of a conductor in a different wiring layer and extending in parallel with the first power supply wiring (Vcc) and for selecting each memory cell. The third power supply line (Vcc31, Vcc32) is formed so as to extend parallel to the first power supply line (Vcc) in a wiring layer different from that of the bit lines (BL1, bars BL1 to BL10, bar BL10). The semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed. 5. The second power supply wiring (Vcc21 to Vcc23)
And the bit lines (BL1, bars BL1 to BL10, bar BL10) are formed in the same wiring layer, and the third power supply wires (Vcc31, Vcc32) and the word lines (WL11 to WL11 to
5. The semiconductor memory device according to claim 3, which is formed in the same wiring layer as WL14). 6. The third power supply wiring (Vcc31, Vcc32)
And the word lines (WL11 to WL14) are formed in different wiring layers.
The semiconductor memory device according to 1. 7. The memory cell (C) includes a gate electrode layer (27, 29) stacked above the semiconductor substrate via an insulating layer and a channel layer (28, 30) made of polysilicon. A pair of thin film transistors (25, 26) and a flip-flop in which the gate terminals of the pair of driver transistors (20, 21) formed on the semiconductor substrate are connected to the drain terminals of the other driver transistor (21, 20). And a channel circuit (28, 30) of the pair of thin film transistors (25, 26) is connected to each driver transistor (20,
21) and the gate electrode layer (27, 29) of each thin film transistor (25, 26) while being connected to the drain terminal.
7. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a thin film transistor load type cell in which the drain terminals of the other driver transistors (21, 20) are connected to each other.