JPH07169845A - Semiconductor device and mnufacture of it - Google Patents

Abstract

PURPOSE:To simplify the process and to maintain the electrostatic breakdown strength high by forming the drain of The N-channel MOS transistor in an input/output part simultaneously with the N-type capacitor diffusion layer of the lower electrode of a MOS capacitor, concerning to a semiconductor device having an N-channel MOS transistor of LDD structure. CONSTITUTION:The N-channel MOS transistor of an internal circuit has an LDD structure provided with a gate insulating film 3, a gate electrode 4, side spacers 12, N-type low-concentration source and drain diffusion layers 9 formed self-alignedly to the gate electrode, N-type high-concentration source and drain diffusion layers 8 formed self-alignedly to the side spacers, and respective electrode terminals. Next the N-channel MOS transistor in the input/output part has a gate insulating film 3, a gate electrode 4, side spacers 12, and N-type source and drain diffusion layers 21 formed with an N-type capacitor diffusion layer 20 which is partially under the gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including an N-channel MOS transistor having an LDD structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a MOS integrated circuit in which MOS transistors are integrated, design rules are being reduced year by year in order to achieve high integration and high speed. Especially about the gate length, 1μm
The following so-called submicron level products have already been commercialized. In this way, the gate length is submicron
In a MOS transistor reduced to the level, in order to suppress fluctuations in electrical characteristics due to hot carriers,
The LDD structure is routinely adopted.

By the way, it is known that, in an integrated circuit including an LDD structure MOS transistor, if an LDD structure N channel MOS transistor is used as it is in the input / output portion, the electrostatic breakdown strength of the integrated circuit is lowered. This is because the LDD structure N-channel MOS transistor is
This is because the electrostatic breakdown strength is lower than that of the conventional single-drain structure MOS transistor.

Therefore, in the conventional integrated circuit including the LDD structure MOS transistor, as shown in FIG. 16, a normal LDD structure MOS transistor is used for the internal circuit.
A MOS transistor having a single drain structure is used for the input / output section. As a document of such an integrated circuit, for example, JP-A-2-292857 and JP-A-3-259.
There is a 562 publication and the like. Next, a conventional manufacturing method of such an integrated circuit in which a normal LDD structure MOS transistor is used for the internal circuit and a single drain structure MOS transistor is used for the input / output section will be described according to the literature.

First, a conventional manufacturing method exemplified in Japanese Patent Laid-Open No. 2-292857 will be described with reference to FIGS. The field insulating film 2 is formed on the main surface of the P-type semiconductor substrate 1 by using a known selective oxidation technique. Next, the semiconductor substrate in a portion which will become an active region in the future is exposed, and the surface is thermally oxidized to form the gate insulating film 3. Next, polycrystalline silicon is deposited on the entire surface of the semiconductor substrate by a chemical vapor deposition method, phosphorus is diffused in this, and then a gate electrode 4 is formed by a normal patterning technique (FIG. 12). Subsequently, the surface of the gate electrode is thermally oxidized in a steam atmosphere to form a thick side oxide film 5 by the accelerated oxidation effect on the side wall of the gate electrode. Next, the photoresist 6 covers only the internal circuit portion, and with this as a mask, the thick side oxide film of the MOS transistor at the input / output portion is removed in an HF solution (FIG. 1).
3). Then, after removing the photoresist, a thin side oxide film 7 is formed on the surface of the gate electrode in a high temperature oxidizing atmosphere. Next, add medium energy arsenic to 1 × 10 ¹⁵ cm
Ions are implanted with a dose amount of about ^-2 to form the N-type high-concentration source / drain diffusion layer 8 of the N-channel MOS transistor (FIG. 14). Then, after removing the thick side oxide film of the internal circuit portion, phosphorus is ion-implanted into the entire surface at a dose of about 1 × 10 ¹³ cm ^-2, and N-type low-concentration source / drain diffusion is performed only in the internal circuit transistor. Form layer 9 (FIG. 15). Subsequently, after depositing an interlayer insulating film 10 such as PSG, reflow is performed in a nitrogen atmosphere at a relatively high temperature. Finally, a contact hole required for the interlayer insulating film is opened and the terminal electrode 11 is formed to obtain a desired semiconductor device (FIG. 16). In the above example, only the N-channel MOS transistor is formed for both the internal circuit and the input / output section.
By adding a photolithography process and a boron ion implantation process, P
A channel MOS transistor can also be formed.

Next, a conventional manufacturing method exemplified in Japanese Patent Laid-Open No. 3-259562 will be described with reference to FIGS. Note that in FIGS. 17 to 19, FIGS.
The same elements as those in No. 6 are designated by the same reference numerals. After forming a field insulating film, a gate insulating film, and a gate electrode on a P-type semiconductor substrate, N-type impurities are ion-implanted to form an N-type low-concentration source / drain diffusion layer 9 (FIG. 17). Subsequently, a side wall spacer 12 is formed by depositing a silicon oxide film on the entire surface of the semiconductor substrate by chemical vapor deposition and then performing anisotropic etching. next,
After only the internal circuit portion is covered with the photoresist, the silicon oxide film is isotropically etched to remove the side spacers of the transistors in the input / output portion (FIG. 18). continue,
After the photoresist is removed, a high dose of N-type impurities is ion-implanted to form an N-type high-concentration source / drain diffusion layer 8. As a result, the N-type low concentration source / drain diffusion layer remains only in the transistor of the internal circuit, and LDD
The structure is formed, and the transistor of the input / output section is formed with a single drain structure by the N-type high-concentration source / drain diffusion layer to obtain a desired semiconductor element (FIG. 19). In this example as well, only the N-channel MOS transistor is formed for both the internal circuit and the input / output section, but the same applies to the P-channel MOS transistor.

However, in the above two manufacturing methods, the internal circuit and the input / output portion are the same until the gate insulating film, the gate electrode and the side spacer are formed, and then only the MOS transistor in the input / output portion is provided with the side spacer. The main point is to remove and form the high-concentration source / drain diffusion layers in a self-aligned manner with the gate electrode. For this purpose, a photolithography process of masking the internal circuit and removing only the side spacers of the MOS transistors in the input / output section is indispensable, and the number of processes is greater than that in the case of simply manufacturing an LDD structure MOS transistor. Increase in manufacturing cost and manufacturing cost.

On the other hand, an integrated circuit including a MOS transistor of LDD structure, particularly a BiMOS integrated circuit in which a bipolar transistor and a MOS transistor of LDD structure are mixedly mounted on the same semiconductor chip (hereinafter referred to as LDD-BiMOS).
LD of a MOS transistor in an integrated circuit)
A manufacturing method has been proposed in which the low-concentration source / drain diffusion layer of D and the base diffusion layer of a bipolar transistor are formed in the same step, and the number of steps is reduced (for example, Japanese Patent Laid-Open No. Hei 2).
-39564). A method of manufacturing the LDD-BiMOS integrated circuit disclosed in Japanese Patent Laid-Open No. 2-39564 will be described with reference to FIGS. Below, P
An N-channel MOS transistor of LDD structure and a vertical PNP transistor are formed on the semiconductor substrate of
The substrate may be an epitaxial substrate in which an N-type or P-type buried layer is formed on a P-type semiconductor substrate and then an N-type or P-type epitaxial layer is grown. The transistor to be formed is also an LDD-structure P-channel MOS. Transistors and vertical NPN transistors are likewise possible.

First, the P-type well 1 is formed on the main surface of the P-type semiconductor substrate.
3 is formed. This P-type well is the well of the N-channel MOS transistor and also the collector of the vertical PNP transistor.

Next, the field insulating film 2, the P-type channel stopper 14, the gate insulating film 3 and the gate electrode 4 are formed by using a known technique (FIG. 20). Then, by photolithography, a pattern of the photoresist 15 having an N-channel MOS transistor region and a vertical PNP transistor region as an opening is formed. Next, N such as phosphorus
Type impurities are ion-implanted to form the N-type low-concentration source / drain diffusion layer 9 of the N-channel MOS transistor and the vertical P-type.
The N-type base diffusion layer 16 of the NP transistor is simultaneously formed (FIG. 21).

Then, after removing the photoresist, a silicon oxide film is deposited on the entire surface of the semiconductor substrate and anisotropically etched to form side spacers 12.
Next, the P-type emitter diffusion layer 17 is formed by a known technique such as photolithography and ion implantation. Next, a pattern of the photoresist 18 is formed by photolithography, in which the N-channel MOS transistor region and a part of the base region of the vertical PNP transistor are opened. Next, N-type impurities such as arsenic are ion-implanted to form an N-channel MO.
N-type high concentration source / drain diffusion layer 8 of S transistor
And the N-type external base diffusion layer 1 of the vertical PNP transistor
9 is formed at the same time (FIG. 22).

In this way, in the above manufacturing method, LDD
The N-type low-concentration source / drain diffusion layer of the N-channel MOS transistor having the structure and the N-type base diffusion layer of the vertical PNP transistor are formed in the same process, and the N-type high-concentration source / drain of the N-channel MOS transistor of the LDD structure is formed. The number of steps can be reduced by forming the diffusion layer and the N-type external base diffusion layer of the vertical PNP transistor in the same step. In addition, when the LDD structure P-channel MOS transistor and the vertical NPN transistor are mounted together on the same chip, the P-type low concentration source / drain diffusion layer of the P-channel MOS transistor and the P-type base diffusion layer of the vertical NPN transistor are combined. Are formed in the same step, and the P-type high-concentration source / drain diffusion layer of the P-channel MOS transistor and the P-type external base diffusion layer of the vertical NPN transistor are formed in the same step, so that the number of steps can be reduced.

However, the LDD-BiMOS described above is used.
In the method of manufacturing an integrated circuit, the N-channel MOS of the internal circuit is used.
The transistor and the N-channel MOS transistor in the input / output section have to have the same LDD structure, and the problem of the decrease in the electrostatic breakdown strength remains as it is.

[0014]

In an integrated circuit including a MOS transistor having an LDD structure, if an N-channel MOS transistor having an LDD structure is used for an input / output portion, it will be more difficult than an N-channel MOS transistor having a conventional single drain structure. However, there is a problem that the electrostatic breakdown strength is reduced.

Normally, breakdown of an N-channel MOS transistor proceeds as follows. First, the electric field strength increases at the end of the drain diffusion layer on the gate electrode side, avalanche breakdown occurs, and a substrate current flows. Next, the substrate current raises the potential of the substrate, the parasitic NPN transistor composed of the source, substrate and drain is turned on, and a large current flows from the drain to the source. This is the so-called snap back phenomenon.

However, an LDD structure N-channel MOS
In the transistor, since an N-type low-concentration source / drain diffusion layer is added to relax the electric field strength at the end of the drain diffusion layer on the gate electrode side, avalanche breakdown does not easily occur, and as a result snap back does not easily occur. Therefore, when a surge or the like is applied to the LDD-structure N-channel MOS transistor, the parasitic NPN transistor cannot be turned on to release the charge, and strong avalanche breakdown is concentrated at relative weak spots. It is considered that the part will be destroyed by heat.

In order to avoid the above thermal breakdown, it is necessary to disperse the avalanche breakdown concentrated in the weak spots so that snap back is likely to occur. For that purpose, like the conventional MOS transistor with a single-drain structure, the impurity concentration at the end of the drain diffusion layer on the gate electrode side is increased to lower the threshold value for generating avalanche breakdown, and the avalanche breakdown occurs in a wide region along the gate electrode. Is good to generate. This also results in a faster snap back response. However, it is clear that the above measures are contrary to the purpose of adopting the LDD structure for the MOS transistor, and it has been difficult to satisfy both with the same MOS transistor structure.

Therefore, the conventional LD proposed in JP-A-2-292857 and JP-A-3-259562.
In the integrated circuit including the MOS transistor of D structure, the low-concentration drain diffusion layer is eliminated only in the input / output portion to maintain the electrostatic breakdown strength. As a method of manufacturing such an integrated circuit,
JP-A-2-292857 and JP-A-3-25956
The method exemplified in Japanese Patent Publication No. 2 is the same for the internal circuit and the input / output section up to the formation of the gate insulating film, the gate electrode, and the side spacer. After that, only the side spacer of the MOS transistor in the input / output section is removed to increase the height. By implanting ions in the concentrated source / drain diffusion layers,
Only in the S transistor, the high-concentration source / drain diffusion layer is formed in self-alignment with the gate electrode.

However, in this manufacturing method, the LDD is simply
Compared with the case where only the MOS transistor having the structure is manufactured, it is necessary to add a photolithography process for removing only the side spacer of the MOS transistor in the input / output section, and the manufacturing period and the manufacturing cost are increased due to the increase in the number of processes. I couldn't escape.

On the other hand, in an LDD-BiMOS integrated circuit, a method has been proposed in which a low-concentration source / drain diffusion layer and a base diffusion layer of LDD are formed in the same step to reduce the number of manufacturing steps (for example, Japanese Unexamined Patent Publication No. HEI 2- 39564). However, in this manufacturing method, the internal circuit and the MOS transistor of the input / output section have the same LDD structure, and the problem of the decrease in electrostatic breakdown strength is left as it is. Practically, depending on the heat treatment, the base of the bipolar transistor is formed by ion implantation with a dose amount of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² , which is the ion implantation required for LDD formation. It is about the same as the dose. That is, the amount of impurities is insufficient for the drain diffusion layer of the input / output portion, and the electrostatic breakdown strength is reduced.

[0021]

The semiconductor device of the present invention comprises:
The drain of the N-channel MOS transistor in the input / output section is formed of the N-type diffusion layer which is the lower electrode of the MOS capacitor or the same diffusion layer as the N-type collector diffusion layer of the vertical NPN transistor, while the N-channel of the internal circuit is The drain of the channel MOS transistor has an LDD structure including a low concentration drain diffusion layer and a high concentration drain diffusion layer.

Further, in the method for manufacturing a semiconductor device according to the present invention, the lower electrode of the MOS capacitor or the N-type diffusion layer serving as the N-type collector of the vertical NPN transistor and the drain of the N-channel MOS transistor in the input / output section are formed. A step of forming an N-type diffusion layer at the same time, a step of forming a gate insulating film, a step of forming a gate electrode via this gate insulating film, and a low-concentration drain diffusion layer and a high-concentration drain diffusion layer in an N-channel MOS transistor of an internal circuit. Forming a concentration drain diffusion layer and forming an LDD structure in an internal circuit.

[0023]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an integrated circuit including an N-channel MOS transistor having an LDD structure according to a first embodiment of the present invention. In this figure, a MOS capacitor, an N-channel MOS transistor of an internal circuit, and an N-channel MOS transistor of an input / output unit are shown in order from the left. At this time, the internal circuit and the P-channel MOS transistor of the input / output unit are omitted. In FIG. 1, the same elements as those in FIGS. 12 to 16 are designated by the same reference numerals.

In the integrated circuit of FIG. 1, each element is formed on the main surface of a P-type semiconductor substrate 1, and a MOS capacitor has an N-type capacitor diffusion layer 20 serving as a lower electrode, a gate insulating film 3, and an upper part. The gate electrode 4 serving as an electrode is provided. Next, the N-channel MOS transistor of the internal circuit includes the gate insulating film 3, the gate electrode 4, the side spacer 12,
N-type low-concentration source / drain diffusion layer 9 formed in self-alignment with the gate electrode, N-type high-concentration source / drain diffusion layer 8 formed in self-alignment with the side spacers, and each electrode It has an LDD structure with terminals. Next, the N-channel MOS transistor of the input / output section is an N-type capacitor formed of the gate insulating film 3, the gate electrode 4, the side spacers 12, and the N-type capacitor diffusion layer 20 partially located under the gate electrode. And a source / drain diffusion layer 21.

In this embodiment, the N channel MO of the input / output unit is used.
The S-transistor does not have the LDD structure, and its source / drain is formed using the same high-concentration N-type capacitor diffusion layer as the lower electrode of the MOS capacitor so that a part thereof is located under the gate electrode. Therefore, the threshold value of the avalanche breakdown of the N-channel MOS transistor of the input / output section is low, and when a surge or the like is applied,
A stable avalanche breakdown occurs in a wide region at the edge of the drain diffusion layer along the gate electrode, and as a result, the snap-back state can be achieved at a high response speed and the added charge can be released to the ground electrode. In this way, the electrostatic breakdown strength of the integrated load can be improved.

Next, FIG. 2 is a sectional view of an LDD-BiMOS integrated circuit showing a second embodiment of the present invention. In this figure, the vertical NPN transistor, the N-channel MOS transistor of the internal circuit, and the N-channel MOS transistor of the input / output unit are shown in order from the left. At this time, P-channel MOS transistors in the internal circuit and the input / output unit and passive elements such as resistors are omitted. In FIG. 1, the same elements as those in FIGS. 12 to 16 are designated by the same reference numerals.

The LDD-BiMOS integrated circuit of FIG.
After forming an N type buried layer 22 for lowering the collector resistance of the vertical NPN transistor on the main surface of the type semiconductor substrate 1, an N type epitaxial layer 23 is deposited and each element is formed on the surface. There is. The vertical NPN transistor is P
Formed in the island of the N-type epitaxial layer which is junction-separated by the type well 13, and has an N-type collector diffusion layer 24, an N-type emitter diffusion layer 25, a P-type base diffusion layer 26, and a P-type external base diffusion layer. 27 and each terminal electrode.
Next, the N-channel MOS transistor of the internal circuit is formed in the P-type well 13 and formed in the gate insulating film 3, the gate electrode 4, the side spacer 12, and the gate electrode 4 in a self-aligned manner. Has a LDD structure including a low-concentration type source / drain diffusion layer 9, an N-type high-concentration source / drain diffusion layer 8 formed in self-alignment with the side spacers, and each terminal electrode 11. Next, the N-channel MOS transistor of the input / output section is also formed in the P-type well 13, and includes the gate insulating film 3, the gate electrode 4, the side spacer 12, and the N-type collector partly located under the gate electrode. And an N-type source / drain diffusion layer 28 formed of the diffusion layer 24.

In the second embodiment of the present invention, the N-type capacitor diffusion layer is used as the source / drain of the N-channel MOS transistor in the input / output section in the first embodiment described above. The LDD-BiMO is the same as that of the first embodiment except that the collector diffusion layer is formed.
The electrostatic breakdown strength of the S integrated circuit can be improved.
In the present invention, the source / drain of the N-channel MOS transistor in the input / output section does not have a self-aligned structure with the gate electrode. Therefore, compared with the self-aligned case, it is necessary to allow a large margin for alignment exposure in the photolithography process. In practice, however, the size of the transistor of the input / output unit is increased by several μm. Does not significantly affect the area of the entire integrated circuit. Further, in the above-mentioned two embodiments, the source of the N-channel MOS transistor of the input / output portion is also formed by the N-type capacitor diffusion layer or the N-type collector diffusion layer similarly to the drain, but this is not always necessary. The source side may have a double structure of a low-concentration source / drain diffusion layer and a high-concentration source / drain diffusion layer, like the N-channel MOS transistor of the internal circuit.

Subsequently, a method of manufacturing a semiconductor device including an LDD structure N-channel MOS transistor according to the present invention will be described.
The structures shown in the above two embodiments will be described with reference to the drawings.

3 to 6 are process sectional views of a third embodiment of the present invention for explaining the method of manufacturing the integrated circuit shown in the first embodiment. In FIG. 3, similarly to FIG. 1, a MOS capacitor, an N-channel MOS transistor of an internal circuit, and an N-channel MOS transistor of an input / output portion are formed in order from the left. First, the field insulating film 2 is formed on the main surface of the P-type semiconductor substrate 1 by using a known selective oxidation technique. Next, the surface of the semiconductor substrate, which will become an active region in the future, is exposed to light and the surface is thermally oxidized to form a thin sacrificial oxide film 29. Next, by photolithography, a pattern of the photoresist 30 having openings in the source / drain portions of the input / output portion N-channel MOS transistor of the MOS capacitor portion is formed, and the intermediate energy is 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm. Phosphorus ions are implanted at a dose of about ^-2 to simultaneously form the N-type capacitor diffusion layer 20 and the N-type source / drain diffusion layer 21 (FIG. 3). Then, the photoresist 30
After peeling off, the sacrificial oxide film 29 is removed and the gate oxide film 3 is formed again. Next, a polycrystalline silicon film is grown on the entire surface by a chemical vapor deposition method, and a high concentration of phosphorus is introduced into this by phosphorus diffusion. Next, this polycrystalline silicon film is patterned to form the gate electrode 4 of the MOS transistor and the upper electrode 4 of the MOS capacitor. Next, by photolithography, a pattern of the photoresist 31 having an opening portion in the N-channel MOS transistor region of the internal circuit and the input / output portion is formed, and it is 5 × 10 ¹³ with medium energy.
Ion implantation of phosphorus with a dose of about cm ⁻² is performed to form an N-type low-concentration source / drain diffusion layer 9 (FIG. 4).
At this time, in the N-channel MOS transistor of the internal circuit, the N-type low-concentration source / drain diffusion layer 9 is formed in self-alignment with the gate electrode 4, but in the N-channel MOS transistor of the input / output section, It is buried in the N-type source / drain diffusion layer 21 and has only the meaning of slightly lowering the resistance of the diffusion layer.

Then, after removing the photoresist 31, a silicon oxide film of 200 is formed by chemical vapor deposition.
Deposit about 0 to 3000 angstroms. Next, annealing is performed in a nitrogen atmosphere to push in the introduced impurities and activate them. Next, anisotropic oxide film dry etching is performed to form the side spacers 12 (FIG. 5). Subsequently, a pattern of the photoresist 32 having an opening portion in the N-channel MOS transistor region of the internal circuit and the input / output portion is formed by photolithography, and the arsenic having a dose amount of about 3 × 10 ¹⁵ cm ⁻² with medium energy is formed. Ion implantation is performed to form the N-type high-concentration source / drain diffusion layer 8 (FIG. 6). At this time, in the N-channel MOS transistor of the internal circuit, the N-type high-concentration source / drain diffusion layer 8 is formed in self-alignment with the side spacers 12, but in the N-channel MOS transistor of the input / output section, It is buried in the N-type source / drain diffusion layer 21, and there is only the meaning of lowering the resistance of the diffusion layer.
After that, the photoresist 32 is peeled off, and a normal CMOS
Similar to the integrated circuit manufacturing method, by forming an interlayer insulating film, opening contact holes, and forming each terminal electrode,
The semiconductor device shown in FIG. 1 can be manufactured.

As described above, in the manufacturing method of this embodiment, the drain of the N-channel MOS transistor in the input / output section is set to M
By forming the N-type diffusion layer, which is the lower electrode of the OS capacitor, at the same time, it was necessary in the conventional manufacturing method.
It is possible to omit the photolithography process for removing only the side spacers of the N-channel MOS transistor in the input / output portion, and it is possible to keep the electrostatic breakdown strength as high as the conventional one.

7 to 11 are process sectional views of a fourth embodiment of the present invention for explaining the method of manufacturing the integrated circuit shown in the second embodiment. 7 to 11, in the same manner as in FIG. 2, the vertical NPN transistor and the internal circuit N are sequentially arranged from the left.
Channel MOS transistor, N channel M of input / output section
An OS transistor is formed. First, the N-type buried layer 22 is formed on the main surface of the P-type semiconductor substrate 1, and then the N-type epitaxial layer 23 is deposited. Next, after depositing a thin silicon oxide film 33 on the epitaxial surface, boron is ion-implanted around the N-channel MOS transistor forming region of the internal circuit and the input / output portion and around the bipolar transistor to form the P-type well 13. . Next, as in the case of forming the P-type well, a pattern of the photoresist 34 having openings in the collector portion of the vertical NPN transistor and the source / drain portion of the input / output N-channel MOS transistor is formed by photolithography, Ion implantation of phosphorus or arsenic with a dose of about 5 × 10 ¹⁵ cm ^{−2 is performed} to simultaneously form the N-type collector diffusion layer 24 and the N-type source / drain diffusion layer 28 (FIG. 7). Then, after removing the photoresist 34, the field insulating film 2 is formed by a known selective oxidation technique. Further, the heat treatment at this time causes the diffusion layers such as the P-type well 13 to be pushed in, and the P-type well 13
Contacts the P-type semiconductor substrate 1 so that the bipolar transistor is junction-isolated as an island of the N-type epitaxial layer 23 (FIG. 8). Subsequently, after the gate oxide film 3 and the gate electrode are formed, the N-type low-concentration source / drain diffusion layer 9 of the N-channel MOS transistor of the internal circuit is formed similarly to the third embodiment (FIG. 9). Then, the N-type emitter diffusion layer 2 is formed in the same manner as in a normal bipolar integrated circuit manufacturing method.
5, P-type base diffusion layer 26, P-type external base diffusion layer 27
Are formed (FIG. 10). Then, similarly to the third embodiment, the N-type high-concentration source / drain diffusion layer 8 of the N-channel MOS transistor of the internal circuit is formed (FIG. 11).
Subsequently, the photoresist 36 is peeled off, an interlayer insulating film is formed, contact holes are opened, and each terminal electrode is formed, whereby the semiconductor device shown in FIG. 2 can be manufactured.

In this embodiment, in the case of the LDD-BiMOS integrated circuit, in the third embodiment, the drain of the N channel MOS transistor of the input / output portion is formed by the N type capacitor diffusion layer of the MOS capacitor. The vertical NPN transistor is replaced with an N-type collector diffusion layer. Also in this embodiment, the photolithography process for removing only the side spacer of the N-channel MOS transistor in the input / output portion, which is required in the conventional manufacturing method, can be omitted, and the electrostatic breakdown strength is as high as the conventional one. Can be kept.

[0035]

As described above, according to the present invention, in the semiconductor device including the N-channel MOS transistor having the LDD structure, the drain of the N-channel MOS transistor in the input / output portion is diffused into the N-type capacitor which is the lower electrode of the MOS capacitor. Since it is formed at the same time as the layer or the N-type collector diffusion layer of the vertical NPN transistor, the photolithography step for removing only the side spacer of the N-channel MOS transistor of the input / output section, which is required in the conventional manufacturing method, is omitted. And the electrostatic breakdown strength can be kept as high as the conventional one.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a structural sectional view of a second embodiment of the present invention.

FIG. 3 is a process sectional view of a third embodiment of the present invention.

FIG. 4 is a process sectional view of a third embodiment of the present invention.

FIG. 5 is a process sectional view of a third embodiment of the present invention.

FIG. 6 is a process sectional view of a third embodiment of the present invention.

FIG. 7 is a process sectional view of a fourth embodiment of the present invention.

FIG. 8 is a process sectional view of a fourth embodiment of the present invention.

FIG. 9 is a process sectional view of a fourth embodiment of the present invention.

FIG. 10 is a process sectional view of a fourth embodiment of the present invention.

FIG. 11 is a process sectional view of a fourth embodiment of the present invention.

FIG. 12 is a process sectional view of a conventional technique.

FIG. 13 is a process sectional view of a conventional technique.

FIG. 14 is a process cross-sectional view of a conventional technique.

FIG. 15 is a process sectional view of a conventional technique.

FIG. 16 is a process sectional view of a conventional technique.

FIG. 17 is a process sectional view of a conventional technique.

FIG. 18 is a process cross-sectional view of a conventional technique.

FIG. 19 is a process sectional view of a conventional technique.

FIG. 20 is a process sectional view of a conventional technique.

FIG. 21 is a process sectional view of a conventional technique.

FIG. 22 is a process sectional view of a conventional technique.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Field insulating film 3 Gate insulating film 4 Gate electrode 5 Thick side oxide film 7 Thin side oxide film 8 N-type high concentration source / drain diffusion layer 9 N-type low concentration source / drain diffusion layer 10 Interlayer insulation film 11 Terminal Electrode 12 Side Spacer 13 P-type Well 14 P-type Channel Stopper 16 N-type Base Diffusion Layer 17 P-type Emitter Diffusion Layer 19 N-type External Base Diffusion Layer 20 N-type Capacitor Diffusion Layer 21 N-type Source / Drain Diffusion Layer 22 N Type buried layer 23 N type epitaxial layer 24 N type collector diffusion layer 25 N type emitter diffusion layer 26 P type base diffusion layer 27 P type external base diffusion layer 28 N type source / drain diffusion layer 29 Sacrificial oxide film 33 Silicon oxide film 6 , 15, 18, 30, 31, 32, 34, 35, 36
Photoresist

Claims (4)

[Claims] 1. The drain of the N-channel MOS transistor of the input / output section is formed of the same diffusion layer as the N-type diffusion layer which is the lower electrode of the MOS capacitor, while the drain of the N-channel MOS transistor of the internal circuit is A semiconductor device having an LDD structure including a low-concentration drain diffusion layer and a high-concentration drain diffusion layer. 2. The drain of the N-channel MOS transistor of the input / output section is formed of the same diffusion layer as the N-type collector diffusion layer of the vertical NPN transistor, while the drain of the N-channel MOS transistor of the internal circuit is low. A semiconductor device having an LDD structure including a high concentration drain diffusion layer and a high concentration drain diffusion layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a step of forming an N-type diffusion layer to be a lower electrode of the MOS capacitor and a drain of the N-channel MOS transistor of the input / output section, and a gate insulating film. And a step of forming an upper electrode of the MOS capacitor and a gate electrode to be the gate of the MOS transistor through the gate insulating film, a low concentration drain diffusion layer and a high concentration drain in the N channel MOS transistor of the internal circuit. A step of forming a diffusion layer and forming an LDD structure in an internal circuit. 4. A method of manufacturing a semiconductor device according to claim 2, wherein an N-type diffusion layer to be the N-type collector of the vertical NPN transistor and the drain of the N-channel MOS transistor of the input / output unit is formed, A step of forming a gate insulating film, a step of forming a gate electrode of a MOS transistor through the gate insulating film, a low concentration drain diffusion layer and a high concentration drain diffusion layer are formed in an N channel MOS transistor of an internal circuit, And a step of forming an LDD structure in an internal circuit.