JPH07162406A - Frame synchronization detection and protection circuit - Google Patents

Abstract

PURPOSE:To obtain the frame synchronization detection and protection circuit in which frame synchronization is detected and protected without an external input. CONSTITUTION:A frame SYNC comparison circuit 1 compares a bit stream signal with a frame synchronization pattern. Upon the receipt of a comparison result representing initial coincidence after reset, a first coincidence confirmation circuit 2 provides an output of a first coincidence flag. A gate selection circuit 3 receives a first coincidence flag and the result of frame SYNC comparison and provides an output of a signal to select sequentially plural gates which is set at time position predicted to receive a succeeding frame synchronizing signal after the first coincidence by taking frame lengths of plural kinds into account. A bit counter 4 counts the frame length and is reset by the first coincidence. A selector circuit 5 receives a gate selection signal and provides an output of a gate generating signal. A gate generating circuit 6 provides an output of a gate signal. A frame SYNC protection circuit 7 protects a frame synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization detection / protection circuit, and more particularly to a frame synchronization detection / protection circuit of a receiver used for digital broadcasting or communication, which multiplexes a plurality of types of data to form a frame for transmission. Regarding

[0002]

2. Description of the Related Art Conventionally, in digital broadcasting and digital communication, data to be transmitted has a frame structure in which it is multiplexed with a frame synchronizing signal and the like, and the data is transmitted in this frame unit. In order to accurately receive and demodulate the received data, it is necessary to detect this frame synchronization signal and determine the frame position. Therefore, when the frame length is fixed, the conventional frame synchronization detection circuit in the receiving device compares, for example, a known frame synchronization pattern with the input received data, and when they match, the predetermined frame length is reached from that point. After that, it is again determined whether or not it matches the frame synchronization pattern, and thereafter, the operation is repeated a predetermined number of times to detect the reception of the frame synchronization signal.

In recent years, a plurality of transmission modes having different frame lengths have been mixed and transmitted. For example, when a data-compressed video signal and audio signal are formed into one frame and transmitted, the frame length differs depending on the compression mode. In such a case, in the conventional frame synchronization detection / protection circuit, a parameter capable of determining the frame length corresponding to the frame length is set from the outside.

[0004]

However, in the conventional frame synchronization detection / protection circuit, the parameter for determining the frame length must be set from the outside every time the frame length of the received signal is different as described above. , For example, if a transmission mode different from the transmission mode of the channel being watched until then is received when the channel is switched while receiving digital broadcasting, the parameter for determining the frame length must be set from the outside. However, there is a problem that the operation is extremely complicated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a frame synchronization detection protection circuit capable of performing frame synchronization detection protection without external input.

[0006]

In order to achieve the above object, the present invention determines whether an input signal input with any one of a plurality of types of frame lengths matches a frame synchronization pattern. A frame sync comparison circuit for comparing whether or not, a first match confirmation circuit that outputs a first match flag after confirming that the comparison result indicating the match from the frame sync comparison circuit is first input after reset, gate setting means, and It is composed of a frame sync protection circuit.

Here, the gate setting means receives the first match flag and the output comparison result of the frame sync comparison circuit as inputs, causes the frame sync comparison circuit to perform the comparison operation only during the gate period, and A plurality of gates are set corresponding to the plurality of types of frame lengths, which are set at a time position where the frame synchronization signal is expected to be input next from the time of input, and the plurality of gates are matched. Are sequentially selected until the comparison result is input, and the gate is set. Further, the frame sync protection circuit displays the comparison result from the frame sync comparison circuit that performs the comparison operation during the period of the set gate after the gate setting means sets one of the plurality of gates. Based on this, frame synchronization protection is performed.

[0008]

In the present invention, the frame length of the input signal is not known at which frame length of the plurality of types of frame length is input, but the frame synchronization signal (frame sync) has the same fixed pattern at any frame length. Therefore, the frame sync comparison circuit compares the frame sync pattern with the input signal to detect the frame sync signal that matches the frame sync pattern.

When the comparison result indicating the coincidence is output from the frame sync comparison circuit for the first time after the reset, the initial coincidence confirmation circuit outputs the initial coincidence flag, whereby the gate setting means sets the plural kinds of frame lengths. Correspondingly, a plurality of gates set at the temporal position where the frame sync signal is expected to be input next,
Gates are sequentially selected and set until the comparison result indicating coincidence is input. As a result, in the present invention, it is possible to perform gate setting that matches the frame length of the input signal.

[0010]

EXAMPLES Next, examples of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. As shown in the figure, the frame sync detection and protection circuit of this embodiment includes a frame sync comparison circuit 1, an initial match confirmation circuit 2, a gate selection circuit 3, a bit counter 4, a selector circuit 5, a gate generation circuit 6 and a frame sync. It is composed of a protection circuit 7.

The frame sync comparison circuit 1 compares the received bit stream signal with a frame sync pattern (frame sync pattern), which is a known fixed pattern of the frame sync signal, and compares the result, and Output. The first match confirmation circuit 2 receives this comparison result, and upon receipt of the comparison result indicating the first match after the start of reception or after the loss of synchronization, thereafter outputs the first match flag. The gate selection circuit 3 is set at a temporal position at which it is predicted that a frame synchronization signal (frame sync) will be input next after the first match in consideration of a plurality of preset frame lengths. Multiple gates,
Upon receiving the first match flag and the frame sync comparison result, a signal for sequentially selecting is output.

The bit counter 4 counts the frame length (bit length) and is reset by the first match. The selector circuit 5 receives the gate selection signal which is the output of the gate selection circuit 3, and outputs a signal (gate generation signal) for generating a gate that determines whether the frame sync comparison result is valid or invalid. The gate generation circuit 6 outputs a gate signal which permits or disallows the comparison operation of the frame sync comparison circuit 1 based on the gate generation signal.

The frame sync protection circuit 7 receives the gate determination flag from the gate selection circuit 3 and the comparison result from the frame sync comparison circuit 1 as input, performs frame synchronization protection, and receives the protected frame synchronization signal. When the synchronization protection is removed, a reset signal is output to each necessary circuit unit (not shown) in the receiving device.

Next, the operation of this embodiment will be described with reference to the flow charts of FIGS. 2 to 4 and the time chart of FIG. Here, FIG. 2 is a flowchart from resetting to frame sync initial matching in this embodiment, FIG. 3 is a flowchart from initial matching to gate determination (second matching) in this embodiment, and FIG. 4 is this embodiment. 7 shows a flowchart from gate determination to frame synchronization protection.

FIG. 5 is a timing chart up to the third match in this embodiment. (A) is a frame synchronization signal in the received signal, (B) is an output gate signal of the gate generation circuit 6, and (C) is. The comparison result of the frame sync comparison circuit 1, (D) shows the output first match flag of the first match confirmation circuit 2, and (E) shows the output gate determination flag of the gate selection circuit 3. It should be noted that the term “reset” as used herein refers to power-on reset and out-of-sync reset.

First, the power-on reset is applied by turning on the power of the receiving device (FIG. 5). By this power-on reset, the gate signal of the gate generation circuit 6 becomes high level (H level) as shown in FIG. 5B, and the received bit stream signal input to the frame sync comparison circuit 1 is processed according to the procedure of FIG. Always be in a state where they can be compared. As a result, the frame sync comparison circuit 1 starts to compare the received bit stream signal with the frame synchronization pattern every clock (step 10 in FIG. 2).
1).

After the start of comparison, when the first frame sync signal that matches the frame sync pattern is input as indicated by a1 in FIG. 5A, the frame sync comparison circuit 1 operates as shown in FIG.
The comparison result indicating the coincidence with the time indicated by is output (see FIG. 2).
Step 102). The comparison result showing this agreement is shown in FIG.
As shown in (C), it is an H level pulse having a constant width. When the first match confirmation circuit 2 receives the comparison result (match pulse) indicating the first match after the power-on reset from the frame sync comparison circuit 1, it sets the first match flag to H at time as shown in FIG. Level. At this time, the bit counter 4 is reset.

When the initial match flag is set, the gate selection circuit 3 follows the procedure shown in FIG. 3 to set a plurality of gates set at the temporal positions where the frame sync signal is expected to be input next. Select sequentially. For example, the frame length settings are a, b, c, d, e (where a <b <
It is assumed that there are five types of c <d <e), and the frame length of the signal currently received is c.

In this case, the gate selection circuit 3 first outputs a gate selection signal for opening the gate at a time position where the frame synchronization signal is expected to be input next when the frame length is a. It is output (step 104 in FIG. 3). The selector circuit 5 receiving this gate selection signal outputs a gate generation signal for causing the bit counter 4 to generate a gate. The gate generation circuit 6 receives the gate generation signal and outputs a gate signal as indicated by a in FIG. 5B, and causes the frame sync comparison circuit 1 to perform the comparison operation only during the period of the gate signal a (see FIG. Step 105 of 3).

Since the comparison in the frame sync comparison circuit 1 during this period of the gate signal a does not match, the gate selection circuit 3 judges that there is no match because the comparison result indicating the match is not input from the frame sync comparison circuit 1 (see FIG. (Step 103 of 3), while waiting for the input of the next comparison result, at the same time, when the frame length is b, the gate is opened at the time position where the frame sync signal is expected to be input next. Output a gate selection signal for
Step 104). As a result, similarly to the above, the gate generation circuit 6 outputs a gate signal as indicated by b in FIG. 5B, and causes the frame sync comparison circuit 1 to perform a comparison operation during the period of this gate signal (see FIG. 3). Step 10
5).

At this time as well, since the comparison in the frame sync comparison circuit 1 does not match, the gate selection circuit 3 judges that there is no match because the comparison result indicating the match is not input from the frame sync comparison circuit 1 (step 103 in FIG. 3). ), While waiting for the input of the next comparison result, similarly, at the same time, when the frame length is c, the gate is opened at the time position where the next frame synchronization signal is expected to be input. A gate selection signal for outputting is output (step 104 in FIG. 3). As a result, similarly to the above, the gate generation circuit 6 outputs a gate signal as indicated by c in FIG. 5 (B).

Since the frame sync signal of the frame having the frame length c is input to the frame sync comparison circuit 1 within the pulse width period of the gate signal as indicated by a2 in FIG. 5A, this time the frame sync comparison is performed. The comparison result in the circuit 1 is coincidence, and the frame sync comparison circuit 1 outputs the comparison result (coincidence pulse) of the second coincidence at the timing of time as shown in FIG. When the gate selection circuit 3 receives this comparison result (step 103 in FIG. 3),
As shown in (E), an H level gate determination flag is output (step 106 in FIG. 3).

At the same time, the bit counter 4 is reset by the comparison result indicating the above coincidence, and the gate is not opened when the frame lengths are d and e which are longer than c. When the comparison results at the gates corresponding to all the set frame lengths are all inconsistent,
The gate selection circuit 3 is reset and the operation of searching for the first match is started.

When the gate determination flag is set, the gate selection circuit 3 opens the gate at the time position where the frame sync signal is expected to be input when the frame length is c, according to the procedure shown in FIG. In order to output only the gate selection signal for causing (step 108 in FIG. 4),
As shown in FIG. 5 (B), the gate generator circuit 6 outputs a gate signal at a time interval of the frame length c thereafter, so that the frame sync comparison circuit 1 also performs the comparison operation at the time interval of the frame length c ( Step 107 in FIG. 4).

After the gate determination flag is set, the frame sync protection circuit 7 is based on the comparison result from the frame sync comparison circuit 1 and after the third match at the time shown in FIG. (Protection count) When continuously input, the synchronous state is entered and the protected frame pulse (frame sync) is output (step 109 in FIG. 4). Further, in this synchronization state, the frame sync protection circuit 7 regards it as out of synchronization and outputs a reset signal when a comparison result indicating a mismatch is continuously input from the frame sync comparison circuit 1 for a set number of times (forward protection number). (Step 109 in FIG. 4).

As described above, according to this embodiment, it is not necessary to externally set the parameter relating to the frame length,
Further, even if the received signal does not include the information indicating the frame length, the frame synchronization protection can always be detected corresponding to the frame length of the input bit stream signal.

[0027]

As described above, according to the present invention,
For an input signal input with any one of a plurality of frame lengths, a prediction gate is provided at a temporal position corresponding to each of the above-mentioned plurality of frame lengths after the first frame synchronization signal is detected. By detecting whether or not the frame sync signal is input sequentially, it is possible to set the gate that matches the frame length of the input signal. Therefore, it is possible to input the frame sync signal without externally inputting parameters related to the frame length. Can be easily detected and protected.

Therefore, according to the present invention, when a bit stream signal having a plurality of frame lengths is received, it can be received by one receiving device, and when the frame length changes during reception. However, it is not necessary to externally change the parameter related to the frame length each time, and the operation for changing the parameter related to the frame length can be released.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a process from the reset in FIG. 1 to the first frame sync match.

FIG. 3 is a flowchart illustrating a process from after the first match in FIG. 1 to gate determination.

FIG. 4 is a flowchart illustrating a process from gate determination to frame synchronization protection in FIG.

5 is a timing chart for explaining the operation of FIG.

[Explanation of Codes] 1 Frame Sync Comparison Circuit 2 First Match Confirmation Circuit 3 Gate Selection Circuit 4 Bit Counter 5 Selector Circuit 6 Gate Generation Circuit 7 Frame Sync Protection Circuit

Claims (2)

[Claims] 1. A frame sync comparison circuit for comparing whether or not an input signal input with any one of a plurality of types of frame lengths matches a frame synchronization pattern, and the frame sync comparison circuit. The comparison result indicating a match from
An initial match confirmation circuit that outputs the initial match flag after confirming that the signal is input first after reset, and receives the initial match flag and the output comparison result of the frame sync comparison circuit as input, and the frame sync is performed only in the gate period. The gate for setting the comparison circuit to perform the comparison operation and for setting the time position at which the next frame synchronization signal is expected to be input from the time when the first match flag is input is set to the plurality of types of frame lengths. A plurality of gates corresponding to the above, and the gate setting means for sequentially selecting the plurality of gates until a comparison result indicating coincidence is input, and the gate setting means, After the gate is set to one of the gates, the frame is compared based on the comparison result from the frame sync comparison circuit that performs the comparison operation during the set gate period. Frame synchronization detection and protection circuit, characterized in that it comprises a frame sync protection circuit performing period protection. 2. The gate setting means receives the first match flag and the output comparison result of the frame sync comparison circuit as inputs, and when the first match flag is input corresponding to the plurality of types of frame lengths. The gate selection signal that sequentially selects the plurality of gates set at the time positions where the frame synchronization signal is expected to be input next is input until the comparison result indicating coincidence is input. , A gate selection circuit that outputs a gate determination flag to the frame sync protection circuit when the comparison result indicating the coincidence is input, and is reset by the comparison result indicating the coincidence from the frame sync comparison circuit, and counts the number of bits of the input signal Generating a gate by receiving a bit counter for inputting, a gate selection signal and an output signal of the bit counter as input signals 2. A selector circuit for outputting a gate generation signal for causing the frame generation circuit, and a gate generation circuit for outputting a gate signal for controlling its operation to the frame comparison circuit based on the gate generation signal. Frame sync detection and protection circuit.