JPH07161987A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To provide a buried channel type MIS type semiconductor device suitable for an analog circuit by a method wherein a drain current slightly changes by a drain voltage in a saturated region (namely, output resistance is high), and the dependence of a threshold value on the channel length and punch-through of a surface are suppressed. CONSTITUTION:An N-type impurity region 6 is formed between a p-type buried channel region 5 and a p-type drain region 4 of a MOS transistor. A PN junction by the N-type impurity region 6 provided at an end of the buried channel region 5 on the side of the drain region 4 absorbs the change in a potential by a drain voltage and a potential hardly changes in a channel inside.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a MIS (Metal-Insulator)
-Semiconductor) type semiconductor device, especially by suppressing the change of drain current due to the drain voltage to increase the output resistance and suppressing the fluctuation of the threshold value due to the gate length, the embedded circuit suitable for analog circuits of semiconductor integrated circuits. The present invention relates to an embedded channel type MOS semiconductor device.

[0002]

2. Description of the Related Art In a CMOS integrated circuit, a P channel MO is used.
The gate electrode of the S transistor (hereinafter, abbreviated as PMOS transistor) has an N channel MOS transistor (hereinafter, N
The process becomes easier when the same n-type polysilicon as the MOS transistor) is used. Therefore, PM
A MOS transistor having a P-type buried channel 5 for the purpose of making the absolute value of the threshold value of OS equal to that of NMOS.
(Fig. 2) is often used. This embedded channel type M
In the OS transistor, the carrier has a merit that the mobility is large because the carrier travels inside the buried channel 5 away from the interface between the gate insulating film and the semiconductor substrate surface, but between the source / drain region 4 and the buried channel region 5. Since there is no pn junction, the influence of the drain electric field extends to the buried channel region 5, and (1) the change of the drain current due to the drain voltage is large (the output resistance is small), (2) the source region and the drain region on the channel surface. There are problems that punch-through that connects the depletion layer from (3) is likely to occur and (3) the threshold value of the short channel is greatly reduced. The output resistance is the reciprocal of the slope of increase in drain current due to drain voltage in the saturation region of MOS transistor characteristics.
In an analog circuit, the maximum voltage amplification factor of the amplifier is determined by the product of the mutual conductance (gm) of the MOS transistor and the output resistance, and thus the size of the output resistance is as important as gm. Therefore, the fact that the output resistance of the buried channel type MOS transistor is small becomes a serious problem in the analog circuit.

As a conventional example (FIG. 3) for solving these problems, as shown in JP-A-61-160975, a source / source
A pocket region 10 having a high impurity concentration is formed under the drain region 4.
Is provided to suppress the extension of the depletion layer into the substrate to reduce the drain voltage dependency of the threshold value.
According to this structure, since the expansion of the depletion layer due to the drain electric field in the substrate region 1 in which the pocket is formed is reduced,
It has an effect of suppressing the change of the threshold voltage due to the drain voltage and punch-through inside the substrate.

[0004]

When the pockets are provided inside the substrate as described above, the effect is the surface channel type MOS.
As in the case where the pocket type semiconductor device is provided, the influence of the drain electric field on the inside of the substrate can be reduced, but the influence of the drain electric field on the semiconductor substrate surface peculiar to the buried channel structure cannot be reduced.

Therefore, an object of the present invention is to reduce the influence of the drain electric field on the substrate surface, which is peculiar to the buried channel structure, to improve the output resistance and suppress the surface punch-through. An object of the present invention is to provide a MOS semiconductor device adapted to an analog circuit by reducing the channel length dependency of the threshold value.

[0006]

The above-mentioned object is, as shown in the basic embodiment of the present invention (FIG. 1), a region (6) of opposite conductivity type to the channel region (5) of the buried channel structure. ) Is provided at both ends or one end of the channel to make the channel end a surface channel.

[0007]

In the present invention, since the pn junction is formed at the end of the buried channel region (5), the action of the drain electric field is lost by the potential change of this pn junction, and the influence on the channel region is reduced.

FIG. 4 shows the potential change of the MOS transistor in the channel direction. As shown in FIG. 4, in the prior art, the drain voltage lowers the potential inside the channel region, and as a result, the height of the barrier also lowers on the source side, resulting in a lower threshold and an increase in drain current. Further, in the short channel, lowering of the threshold value and punch through are likely to occur. On the other hand, in the present invention, as shown in FIG. 4, the buried channel region on the drain region (4) side is formed.
The potential change due to the drain voltage is absorbed by the pn junction formed by the opposite conductivity type region (6) provided at the end of (5), and the potential change is small inside the channel.
That is, since the buried channel region (5) surrounded by the pn junction is less affected by the electric field of the source and drain 4, the output resistance is large, the channel length dependency of the threshold value is small, and surface punch-through hardly occurs. Become. Other objects and features of the present invention will be apparent from the following examples.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. Although the embodiment has been described by using the silicon MOS transistor, the operating principle is the same for MOS type semiconductor devices using other semiconductor materials. Further, in the embodiments, the description has been mainly given of the p-type MOS transistor as an example, but the operating principle is the same for the n-type MOS transistor. Also in the forming method, an n-type MOS transistor can be similarly formed by changing the impurities used to have opposite conductivity types.

A basic embodiment of the present invention is shown in FIG.
1 is an n-type silicon substrate, 2 is an element isolation insulating film, 3 is n-type gate polysilicon, 4 is p-type source / drain region, 5 is p-type buried channel region, and 6 is n-type as an electric field stopper. Region, 7 is a gate insulating film, 8 is an interlayer insulating film,
Reference numeral 9 is a source / drain metal wiring. in this way,
A region 6 having a conductivity type (n-type) opposite to that of the channel region 5 is provided at the channel end of the channel region 5 of the buried channel type structure, and this portion 6 is used as a surface channel which causes surface inversion by the n-type gate polysilicon. . As a result, a pn junction is formed between the channel region 5 and the source / drain region 4, so that the influence of the drain voltage is absorbed by the pn junction in the region 6, and carriers from the source / drain region 4 (in the present embodiment) are used. Then, the seepage of holes) is also reduced. Therefore, it is possible to improve the output resistance, reduce the surface punch-through, and reduce the channel length dependency of the threshold value. The formation method is the same as that of a normal buried channel type MOS transistor up to the point of processing the gate electrode 3. After the gate electrode 3 is processed, the channel region 5 is canceled at the channel end by oblique ion implantation using the gate electrode 3 as a mask. To form a region 6 of opposite conductivity type. Vertical ion implantation may be performed instead of oblique ion implantation, and then impurities may be diffused laterally by a thermal process. After that, the source / drain region 4 is formed by ion implantation, and then the normal MO is formed.
It may be formed according to the process of the S transistor.

Next, a second embodiment is shown in FIG. In this embodiment, an n-type high impurity concentration buried layer 11 is provided below the channel region 5 in addition to the opposite conductivity type region 6 at the channel end. The buried layer 11 functions as a punch-through stopper, and has effects of reducing punch-through in a short channel and reducing the channel length dependency of the threshold value. n-type region 6
And the effect of the n-type buried layer 11 are combined, the output resistance is improved in the short channel, the punch-through is reduced,
The effect of reducing the channel length dependency of the threshold is further enhanced. The forming method is to form the high-concentration buried layer 11 by ion implantation after forming the element isolation region 2, and then form the channel region 5 by ion implantation. Gate oxide film 7
And then p + polysilicon is deposited to form the gate electrode 3
To process. The subsequent process is the same as that of the first embodiment, and after forming the region 6 by oblique ion implantation, it is formed according to the process of a normal MOS transistor.

A third embodiment is shown in FIG. In this embodiment, the n-type high impurity concentration pocket 10 is formed under the source / drain region 4. The pocket 10 also functions as a punch-through stopper, and has the effect of reducing punch-through in the short channel and reducing the channel length dependency of the threshold value. As in the case of the second embodiment, it is possible to improve the output resistance in the short channel, reduce punch-through, and reduce the dependence of the threshold on the channel length. The method for forming the gate electrode 3 is the same as that of a normal buried channel type MOS transistor up to the point of processing, and high energy (phosphorus 200 keV in this embodiment) oblique ions using the gate electrode 3 as a mask after the gate electrode 3 is processed. The pocket 10 is formed by implantation, and then the channel region 5 is canceled at the channel end by oblique ion implantation of low energy (phosphorus 50 keV in this embodiment) to form the region 6 of opposite conductivity type. After that, the source / drain region 4 is formed by ion implantation, and thereafter, the source / drain region 4 is formed in accordance with a normal MOS transistor process.

Next, FIG. 7 shows a fourth embodiment of the present invention having an SOI structure. The thickness of silicon on the oxide film 12 is 0.1 μm.
At m, the channel is completely depleted at a gate voltage of 0V. Due to the effect of the buried channel type and complete depletion, the electric field strength at the interface of the gate oxide film is low, so that the mobility is increased. At this time, by providing the region 6 of the opposite conductivity type to the channel region 5 at the channel end, it is possible to increase the output resistance, reduce the surface punch-through, and reduce the channel length dependency of the threshold value. The forming method may be the same as that of the first embodiment on the SOI substrate formed by wafer bonding or the like.

Next, a fifth region in which the region 6 is provided only at the drain end
An example of is shown in FIG. In this structure, the influence of the drain electric field is mitigated by the conductivity of the other region 6 opposite to that of the channel region 5, so that the output resistance can be improved and the drain voltage dependency of the threshold value can be reduced. By not providing the region 6 on the source side, the increase in threshold value and the decrease in mobility can be made smaller than in the first embodiment. The formation method is made possible by covering the source side with a photomask when forming the region 6 by oblique ion implantation in the first embodiment.

Next, FIG. 9 shows a sixth embodiment in which the present invention is applied to a power MOSFET. Normal power MOSFET
The surface channel type is used in order to improve the punch-through withstand voltage, but since the punch-through withstand voltage can be improved by using the present invention, the buried channel type can be adopted, the ON resistance is reduced by the improvement in mobility, and the high frequency characteristics are improved. Can be improved. A channel region of a normal lateral power MOSFET is a buried channel type with a p-well 16 and a channel region 15, and an n-type low impurity concentration offset region 1
A region 6 having a conductivity type (p-type) opposite to that of the channel region 15 is provided on the drain side in contact with 8. Since punch-through on the surface can be suppressed by this structure, the mobility is increased by the effect of the buried channel type, the on-resistance can be reduced, and the cutoff frequency can be improved. The formation method is p
The well region 16 is formed on the substrate for the epitaxial formation of − / p +.
Then, the element isolation region 2 is formed. After forming the channel region 15 by ion implantation, the gate oxide film 7 is formed by oxidation,
Next, after forming the p + polysilicon gate electrode 19, a region 6 is formed by oblique ion implantation only on the drain side using a photomask. Here, the material of the gate electrode may be a metal such as molybdenum or tungsten in order to improve high frequency characteristics. Next, an offset region 7 is formed by ion implantation on the entire surface, and a source / drain region 14 is formed. After that, it is completed through a normal wiring process.

Next, FIG. 10 shows a seventh embodiment in which the present invention is applied to a CMOS (complementary MOS transistor) structure. Reference numeral 17 is a p-type electric field stopper region, 6 is an n-type electric field stopper region, 24 is a P + pocket, and 23 is an N + pocket. In this embodiment, n + is added to the PMOS transistor.
The polysilicon gate 3 is used, and the p + polysilicon gate 4 is used as the NMOS transistor to make all the MOS transistors a buried channel type to improve the mobility and thereby increase the speed. Here the gate material 3, 4
If titanium nitride is used as the material, the work function is a value between n + polysilicon and p + polysilicon, so NMOS and PMO
It is easy to make both S into buried channels. Of course, it is possible to make the NMOS a surface channel type by using only n + polysilicon, and in that case, the region 17 is unnecessary. In addition, LDD (L
ightly Doped Drain) structure is adopted, and this LDD
As the region, an n-region 25 is provided for the NMOS and a p-region 23 is provided for the PMOS. According to this embodiment, since the output resistance is large and the mobility is high, analog and analog /
It is possible to provide a high-speed CMOS structure suitable for a digital mixed integrated circuit.

FIG. 11 shows the forming method of the seventh embodiment.
First, according to a normal CMOS process, the p well region 21
Then, the n-well region 20 is formed and the element isolation region 2 is formed. Next, phosphorus is ion-implanted to form the n-type channel region 15, and boron is ion-implanted to form the p-type channel region 5 (FIG. 11A). After forming the oxide film 7 by gate oxidation, polysilicon is deposited and ion implantation is performed to obtain n + polysilicon 19 and p + polysilicon 3, and a gate electrode is formed by an etching process.
Next, a pocket 17 is formed by ion implantation of boron (70 keV) into the NMOS by a photomask, and a region 17 is formed by oblique ion implantation (30 keV) to make the channel end a surface channel type. Further, an n-layer 25 having an LDD structure is formed by ion implantation of phosphorus.
Next, for the PMOS, similarly, a photomask is used and phosphorus ion implantation (200 keV) is performed to form the pocket region 1.
0 is formed, and the region 6 is formed by oblique ion implantation (80 keV). Further, an LDD structure p-layer 23 is formed by boron ion implantation (FIG. 11b). Next, a sidewall 22 is formed on the sidewall of the gate electrode, and an NMOS is formed.
Arsenic is ion-implanted into the source / drain 14 and boron is ion-implanted into the PMOS to form the source / drain 4 (FIG. 11c). After that, the interlayer insulating film 8 is deposited, and the aluminum wiring layer 10 is attached to complete the process (FIG. 11d).

FIG. 12 shows the effect of the present invention on the drain current-drain voltage characteristic. Comparing the threshold voltage of the entire transistor of the present invention with that of the conventional one, the threshold value of the channel region 5 becomes lower than that of the conventional one, so that a large amount of drain current flows in the non-saturated region for the same gate voltage.
On the other hand, in the saturation region, the conventional drain current increases as the drain voltage increases, whereas in the present invention, a substantially constant drain current flows regardless of the drain voltage and the output resistance increases. .

Further, in the present invention, as shown in FIG.
Even in the dependence of the threshold value on the channel length, the threshold value drop in the short channel is small because surface punch-through is suppressed.

[0020]

As described above, according to the present invention, the drain current change due to the drain voltage is small in the saturation region, that is, the output resistance is large, and the fluctuation of the threshold value due to the channel length and the surface punch-through are suppressed. A buried channel type MOS semiconductor device capable of suppressing a short channel can be realized. As a result, it is possible to use a miniaturized buried channel type MOS semiconductor device even in an analog circuit, and it is possible to increase the amplification factor of the amplifier and the high frequency characteristics.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a first embodiment having a basic structure of the present invention.

FIG. 2 shows a sectional structure of a conventional buried channel type MOS transistor.

FIG. 3 shows a cross-sectional structure of a conventional example in which pockets are provided near the source / drain at both ends of the channel.

FIG. 4 shows changes in potential along the channel direction of the MOS transistor of the present invention and the following Urai example.

FIG. 5 is a sectional structural view showing a second embodiment of the present invention.

FIG. 6 is a sectional structural view showing a third embodiment of the present invention.

FIG. 7 is a sectional structural view showing a fourth embodiment of the present invention.

FIG. 8 is a sectional structural view showing a fifth embodiment of the present invention.

FIG. 9 is a sectional structural view showing a sixth embodiment of the present invention.

FIG. 10 is a sectional structural view showing a seventh embodiment of the present invention.

FIG. 11 is a process drawing showing the method for forming the device structure according to the seventh embodiment of the present invention.

FIG. 12 shows the effect of the present invention on drain current-drain voltage characteristics.

FIG. 13 shows the effect of the present invention on the channel length dependence of the threshold value.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... N-type polysilicon gate electrode, 4 ... P + source, drain region,
5 ... p-channel region, 6 ... n- drain electric field stopper, 7 ... gate insulating film, 8 ... interlayer insulating film, 9 ... metal wiring, 10 ... n + pocket, 11 ... high-concentration buried layer, 12 ...
Insulating film substrate, 13 ... p- / p + epitaxial substrate, 1
4 ... n + source / drain region, 15 ... n-channel region, 16 ... p well, 17 ... p-drain electric field stopper, 18 ... n offset high breakdown voltage layer, 19 ... p + polysilicon gate electrode, 20 ... n well, 21 ... p-well,
22 ... Sidewall insulating film, 23 ... p-LDD layer, 2
4 ... p + pocket, 25 ... n-LDD layer.

Claims (6)

[Claims] 1. A buried channel type MIS type semiconductor device, comprising: the buried channel region and a drain side opposite conductivity type region opposite conductivity type to the drain region between the buried channel region and the drain region. M characterized by having done
IS type semiconductor device. 2. The source side opposite conductivity type region having a conductivity type opposite to that of the buried channel region and the source region is further provided between the buried channel region and the source region. The MIS type semiconductor device described. 3. A high impurity concentration buried layer of the opposite conductivity type is formed inside a semiconductor substrate deeper than the buried channel region so as to be connected to the source region and the drain region. The MIS type semiconductor device according to claim 2. 4. A semiconductor substrate deeper than the buried channel region is provided with two high impurity concentration pocket layers of the opposite conductivity type formed so as to be connected to the source region and the drain region, respectively. The MIS type semiconductor device according to claim 2, wherein 5. A semiconductor layer provided on an insulator, wherein the buried channel region, the source region, the drain region, the source-side opposite conductivity type region, and the drain-side opposite conductivity type region are formed. The MIS type semiconductor device according to any one of claims 2 to 4, characterized in that: 6. The MIS according to claim 1, wherein an offset layer of the same conductivity type as the drain region and having a low impurity concentration is provided between the drain region and the drain side opposite conductivity type region. Type semiconductor device.