JPH07161926A - Analog signal switching circuit - Google Patents

Abstract

PURPOSE:To provide a bipolar/CMOS type analog signal switching circuit which makes possible the processing of an analog signal whereto a high bias voltage is applied by using a highly versatile analog switch of CMOS structure having low gate-to-source breakdown strength. CONSTITUTION:A standard voltage source 7 is provided to supply two electric potentials VDD, VSS to both an analog switch functional block 120 and a level shift circuit 8. A driving signal which is output from a signal processing circuit 6 and whose voltage is converted into a potential VDD or VSS at the level shift circuit 8 is input to a gate of CMOS structure analog switches 1, 2 wherein two potentials VDD, VSS are applied to a back gate to drive them alternately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a bipolar and a CM.
The present invention relates to a mixed-type semiconductor integrated circuit formed by mixing OS structure elements, and particularly to an analog signal switching circuit for switching an input analog signal.

[0002]

2. Description of the Related Art For example, in the past, two sensors output two
An analog signal switching circuit formed by mixing bipolar and CMOS structure elements in one integrated circuit as shown in the block diagram of FIG. 10 is used as a sensor interface for alternately extracting various kinds of analog signals. There is. In the figure, 1 and 2 are P-channel MOS
This is an analog switch having a CMOS structure composed of a transistor and an N-channel MOS transistor. Gates of different channels of these two analog switches 1 and 2 are connected to each other, and their input terminals are respectively connected to an input terminal 100.
Alternatively, it is connected to the input terminal 200 and each output terminal is connected to the positive sign terminal of the voltage follower type operational amplifier 5. Reference numeral 3 is an inverter having a CMOS structure, and 6 is a signal processing circuit, which outputs a signal for turning on or off the analog switches 1 and 2, and receives an output of the operational amplifier 5.
Reference numeral 8 denotes a bipolar structure level shift circuit for converting a voltage level, which converts a signal output from the signal processing circuit 6 into a predetermined voltage level, and converts the voltage level into a N-channel MOS transistor of the analog switch 1. And to the P channel MOS transistor of the analog switch 2 via the inverter 3 and directly to the P channel MOS transistor of the analog switch 1 and the N channel MOS transistor of the analog switch 2.

Next, the operation will be described. First, the two types of analog signals from the two sensors input to the input terminal 100 and the input terminal 200 are input to the analog switch 1 or the analog switch 2, respectively.

At this time, a signal for driving the analog switches 1 and 2 is output from the signal processing circuit 6 to the level shift circuit 8. The level shift circuit 8 outputs the voltage of the drive signal to the analog switches 1 and 2. Is converted into a voltage of the driving voltage level of and the voltage is supplied to the analog switches 1 and 2.

Then, as shown in FIG. 10, the analog switch 1 and the analog switch 2 which are supplied with a drive voltage from the level shift circuit 8 have gates of different channels connected to each other. The gates are connected to the output end of the level shift circuit 8 through the inverter 3, and the output end of the level shift circuit 8 is directly connected to the other gate, so that the opposite operations are performed. Therefore, for example, when the high voltage level drive signal is output from the signal processing circuit 6, the analog switch 1 is turned off, the analog switch 2 is turned on, and the analog signal input to the analog switch 2 is turned on. The signal is picked up. When the drive signal is at the low voltage level, the analog switch 1 is turned on, the analog switch 2 is turned off, and the analog signal input to the analog switch 1 is taken out. In this way, the two types of analog signals alternately selected and taken out by the analog switches 1 and 2 are supplied to the operational amplifier 5
To the signal processing circuit 6 after being impedance-converted.

It should be noted that the analog signal switching circuit is connected to, for example, a bridge comparison circuit for comparing the resistance value of each of two sensors whose resistance values change when actuated with the resistance value of a reference resistance. When used as an interface, the signal processing circuit 6 has the configuration shown in FIG. 11, and the reference resistor 61 connected to the power supply terminal 400 is used.
And resistors 72, 63, and 64 are connected to the sensors 72 and 73, respectively, and the voltage applied to the power supply terminal 400 is divided into resistors, and the divided voltage obtained by the sensor 72 and the resistor 63 is converted into the analog signal. The divided voltage obtained by the sensor 73 and the resistor 64 is input to the input terminal 200 of the signal switching circuit 1000 and input to the other input terminal 100. Then, the analog signal switching circuit 1000
The above-mentioned operation alternately takes out the two types of divided voltages and inputs them to the signal processing circuit 6. The signal processing circuit 6 is a reference obtained by a reference resistor 61 and a resistor 62. The divided voltage and the above-mentioned two kinds of divided voltages are alternately compared by a circuit including operational amplifiers 69, 70 and 71 and resistors 65 to 68, and the error is amplified and output from the signal output terminal 500.

[0007]

The conventional analog signal switching circuit is constructed as described above, and generally the amplitude of the analog signal voltage output by the sensor is small, but the sensor and its Considering these points, when the installation location from the control circuit is distant and the sensor cannot be supplied with the power supply voltage of 5 V, or when the S / N ratio (noise resistance) is improved, the analog signal described above is taken into consideration. There is a case where the bias voltage applied to is increased, and in such a case, the analog switches 1 and 2 of CMOS structure have
An input voltage obtained by adding the high bias voltage and a voltage that is ½ of the voltage of the input analog signal is applied to the source and drain thereof. Therefore, in order to drive the analog switches 1 and 2, it is necessary to set the range of the voltage applied to the gates thereof from 0 V to a voltage exceeding the input voltage. In order to prevent the destruction or malfunction of the elements, the breakdown voltage between the gate and the source of the analog switches 1 and 2 must be increased, and the structure becomes complicated in the process of forming the CMOS structure and the number of manufacturing steps increases. There was a problem.

The present invention has been made to solve the above problems, and a high bias voltage is applied by using an analog switch having a CMOS structure, which has a low gate-source breakdown voltage and high versatility. Another object of the present invention is to provide an analog signal switching circuit capable of processing analog signals.

[0009]

SUMMARY OF THE INVENTION An analog signal switching circuit according to the present invention has a plurality of input terminals in a mixed mounting type semiconductor integrated circuit in which a bipolar element and a CMOS element are mixed and formed in one integrated circuit. In the analog signal switching circuit for selecting a predetermined analog signal from the analog signals applied with the bias voltage input individually to the analog signal switching circuit for impedance-converting the selected analog signal and inputting it to the signal processing means of the first analog signal, Of a predetermined potential of 2 and a second predetermined potential lower than the above bias voltage
Voltage supply means for supplying two voltage signals, and two voltage signals of the first predetermined potential and the second predetermined potential are supplied, and the input voltage of the drive signal output by the signal processing means is output in binary. Voltage conversion means for converting and outputting to a drive voltage, and two voltages of the first predetermined potential and the second predetermined potential as its power supply voltage, driven by the output drive voltage output by the voltage conversion means, Analog signal switching means having a MOS structure for selecting a predetermined analog signal from the plurality of analog signals and outputting the selected analog signal toward the signal processing means, the first predetermined potential and the second The predetermined potential is such that the potential difference between them is larger than the amplitude voltage of the analog signal and does not exceed the withstand voltage of the analog signal switching means having the MOS structure.

In the analog signal switching circuit according to the present invention, the voltage supply means converts the power supply voltage of the analog signal switching circuit into a reference voltage for generating the first predetermined potential and the second predetermined potential. It is the source. In the analog signal switching circuit according to the present invention, the voltage supply means is provided with a voltage detection means for detecting a bias voltage applied to the analog signal, and the level of the detected voltage is increased by a predetermined value. It comprises a level shift means for shifting downward to generate the first predetermined potential and the second predetermined potential.

Further, in the analog signal switching circuit according to the present invention, the amplitude voltage of the analog signal is set to the first predetermined potential at the next stage of each input terminal to which the analog signal including the bias voltage is input. An input voltage limiting means for limiting the voltage to the second predetermined potential is provided.

In the analog signal switching circuit according to the present invention, the analog signal switching means is a P channel M.
It includes two analog switches and an inverter having a CMOS structure composed of an OS transistor and an N-channel MOS transistor. The two analog switches connect gates of different channels to each other, and connect one of the interconnected gates. The output terminals of the inverters are connected to each other, and the other interconnected gates and the input terminals of the inverters are commonly connected to the output terminals of the voltage converting means. The above-mentioned first predetermined potential is applied to the back gate of each P-channel MOS transistor.
The second predetermined potential is applied to the back gate of the transistor, and in the two analog switches of the analog signal switching means, the voltage conversion means has the first predetermined potential, the first predetermined potential and the first drive potential with respect to the input drive voltage. A drive signal that is converted into a binary output drive voltage equal to a predetermined potential of 2 and then output is used to selectively output an analog signal input to each source or drain from that drain or source. is there.

In the analog signal switching circuit according to the present invention, the analog signal switching means is a P channel,
Alternatively, two analog switches using one type of N-channel MOS transistors and two types of MOS transistors of P-channel and N-channel are used, and the output terminal is connected to one of the gates of the two analog switches. The input terminal of the inverter and the gate of another analog switch not connected to the output terminal of the inverter are commonly connected to the output terminal of the voltage conversion means, and P The first predetermined potential is applied to the back gate of the channel MOS transistor, the second predetermined potential is applied to the back gate of the N channel MOS transistor, and the two analog switches of the analog signal switching means are , The voltage conversion means has the first predetermined potential with respect to the input drive voltage. Two analog signals input to the respective sources or drains are selectively output from the drains or sources by a drive signal converted into a binary output drive voltage equal to the second predetermined potential and output. It is what

[0014]

In the present invention, because of the above-mentioned configuration, the two voltages of the first and second predetermined potentials output by the voltage supply means are used as the power supply voltage of the analog signal switching means having the MOS structure. The drive signal output from the signal processing circuit is converted into the first or second predetermined potential level by the voltage conversion means according to the voltage level thereof,
By driving the analog signal switching means with the converted binary output drive voltage, the range of the effective voltage of the analog signal including the bias voltage input to the analog signal switching means is changed from the second predetermined potential. By narrowing to the first predetermined potential, the withstand voltage of the analog signal switching means having the MOS structure can be lowered, and the input signal in the voltage region exceeding this withstand voltage can also be lowered substantially. It can be selectively retrieved and processed.

Further, in the present invention, the voltage supply means is a voltage detection means for detecting the bias voltage applied to the analog signal, and the level of the detected voltage is increased or decreased by a predetermined value. Since it comprises the level shift means for shifting to generate the first predetermined potential and the second predetermined potential, the first and second predetermined potentials are generated according to the change of the bias voltage. Therefore, at the time of manufacturing the analog signal switching circuit, there is no need to preliminarily check the bias voltage included in the analog signal input to the analog signal switching circuit in the device using the analog signal switching circuit to determine the circuit configuration, and the versatility is high. Can be one.

Furthermore, in the present invention, the amplitude voltage of the analog signal is applied to the first predetermined potential and the second predetermined voltage at the next stage of each input terminal to which the analog signal including the bias voltage is input. Since the input voltage limiting means for limiting the voltage to the potential is provided, even if the amplitude voltage of the analog signal fluctuates, when the analog signal is input to the analog signal switching means, the amplitude voltage is always the first voltage. It is kept within the range of the potential difference between the first predetermined potential and the second predetermined potential, whereby the destruction or malfunction of the element of the analog signal switching means can be prevented.

[0017]

EXAMPLES Example 1. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram showing an analog signal switching circuit according to a first embodiment of the present invention. In the figure, reference numeral 120 denotes an analog functional block having a CMOS structure using a P-channel MOS transistor and an N-channel MOS transistor, which includes analog switches 1 and 2 and an inverter 3. The two analog switches 1 and 2 of the analog function block 120
Is an input terminal 100 or an input terminal 2 to which an analog signal to which a bias voltage is applied is input, respectively.
00, and the output terminal thereof is commonly connected to the positive sign terminal of the voltage follower type operational amplifier 5, the gates of different channels are connected to each other, and the output terminal of the inverter 3 is connected to one of the mutually connected gates. Are connected. 6 is a signal processing circuit, which is an analog switch 1,
It outputs a signal for turning on or off 2 and receives the output of the operational amplifier 5. Reference numeral 8 denotes a bipolar structure level shift circuit for converting the voltage level, which converts the signal output from the signal processing circuit 6 into a binary voltage level and converts the voltage level converted signal into the N channel of the analog switch 1 and It is applied to the P channel of the analog switch 2 via the inverter 3 and directly to the P channel of the analog switch 1 and the N channel of the analog switch 2. A reference voltage source 7 outputs two potentials, a first potential VDD and a second potential VSS, and a VDD terminal 60
The two potentials VDD and VSS are supplied to both the analog switch function block 120 and the level shift circuit 8 via the 0 or VSS terminal 700.

FIG. 3 shows a circuit diagram of the analog switch 2, and in the figure, the analog switch 2 is shown.
Is a P-channel MOS transistor 14 whose gate is supplied with a drive voltage via an inverter 3 and an N-channel M transistor whose gate is directly supplied with a drive voltage.
And the P-channel MO
The first potential V is applied to the back gate of the S transistor 14.
The N-channel MOS transistor 15 is applied with DD
Is applied with the second potential VSS.

The analog switch 1 has the same circuit configuration as the analog switch 2, but the method of inputting the drive voltage to each gate is opposite to that of the analog switch 2 and is a P-channel MOS transistor. The driving voltage is directly input to the gate of the N channel MOS transistor, and the driving voltage is input to the gate of the N-channel MOS transistor through the inverter 3.

Next, the operation will be described. First, the two types of analog signals, to which the bias voltage is applied, input to the input terminal 100 and the input terminal 200 are input to the analog switch 1 or the analog switch 2, respectively. At this time, the signal processing circuit 6 to the level shift circuit 8
A signal for driving the analog switches 1 and 2 is output to the reference voltage source 7 and an input signal including the analog signal is output from the reference voltage source 7 when the maximum effective amplitude voltage of the analog signal is within 5V. The first potential VDD higher than the bias voltage by 2.5V and the second potential VSS lower than the bias voltage by 2.5V are applied to the level shift circuit 8.

When the voltage of the drive signal from the signal processing circuit 6 is at the high voltage level, the level shift circuit 8 sets the voltage to the first potential VDD and L
When it is at the ow voltage level, it is converted to the second potential VSS, and the converted drive voltage VDD or VSS is supplied to the analog switches 1 and 2.

Here, as shown in FIG. 1, the first and second potentials VDD and VSS are set to the analog switches 1 and 2, respectively.
It is also supplied as the power supply voltage of the analog switch function block 120 composed of the inverter 3 and the inverter 3, so that the bias voltage input to the analog switch function block 120 composed of MOS elements is reduced by the second potential VSS. Becomes

Then, the signal processing circuit 6 outputs High.
When a drive signal of a voltage level is output and the drive voltage whose level has been converted to VDD by the level shift circuit 8 is input to the analog switch function block 120, the analog switch 1 is turned off and the analog switch 2 is turned on. When turned on, the analog signal input to the input terminal 200 is taken out, and when the drive voltage VSS obtained by converting the drive signal of the Low voltage level is input,
The analog switch 1 is turned on and the analog switch 2 is turned off, and the analog signal input to the input terminal 100 is taken out.

That is, as shown in FIG. 2, the reference voltage source 7 sets the operating voltage range of the analog switches 1 and 2 between the first potential VDD and the second potential VSS. Moreover, since the analog switch 1 and the analog switch 2 are alternately turned on / off by the first and second potentials VDD and VSS, the gate and source of the analog switches 1 and 2 are turned on and off. The voltage applied between the input terminals 100 and 200 is controlled within 5V.
The two types of analog signals respectively input to are alternately selected and taken out. Then, the two kinds of alternately fetched analog signals are input to the operational amplifier 5, impedance-converted, and then input to the signal processing circuit 6.

Further, when this analog signal switching circuit is used as a sensor interface connected to the bridge comparison circuit as shown in FIG. 11 in the same manner as in the conventional example, the signal processing circuit 6 operates as a reference division voltage. , Each sensor and the divided voltage by the resistor are compared with each other, and a signal obtained by amplifying each error is output from the output terminal 500.

As described above, according to the first embodiment, in the analog signal switching circuit formed by mixing the bipolar and CMOS elements, the first potential VDD higher than the bias voltage of the input signal by a predetermined voltage. And a reference voltage source 7 for outputting a second potential VSS lower by a predetermined voltage than the reference potential source 7, and both the first and second potentials VDD and VSS are set to 2
The voltage of the drive signal of the signal processing circuit 6 is supplied to the analog switch function block 120 having a CMOS structure including the analog switches 1 and 2 and the inverter 3 for alternately selecting the type of analog signal as its power supply voltage. The level shift circuit 8 for converting the level to the drive voltage level of the analog switches 1 and 2 is also supplied with both the first and second potentials VDD and VSS, and the level shift circuit 8 outputs the potential. Analog switch 1, 2 of 2
Since the drive voltage having the value is set to the first potential VDD or the second potential VSS, the range of the drive voltage of the analog switches 1 and 2 is the first potential VDD and the second potential. It is between VSS and the analog switch 1,
The voltage applied between the gate and the source of 2 is suppressed to a low level. As a result, the withstand voltage of the analog switches 1 and 2 having the CMOS structure can be lowered,
An analog signal switching circuit having an analog switch manufactured by a process of forming a 5V CMOS device can be obtained.

In the first embodiment, two analog switches for alternately selecting and extracting the input signal are shown, but the number of analog switches is not limited to two, and the signal to be selected is selected. It goes without saying that the inverters 3, the operational amplifiers 5, and the signal processing circuits 6 may be additionally provided in accordance with the number of the above.

Example 2. An analog signal switching circuit according to the second embodiment of the present invention will be described below. In the first embodiment, both the analog switch function block 120 and the level shift circuit 8 have the first potential VDD,
A reference voltage source 7 for supplying both potentials of the second potential VSS.
However, in the second embodiment, the circuit for supplying both the first potential VDD and the second potential VSS is a circuit whose block diagram is shown in FIG. .

In FIG. 4, 9 is a voltage detection circuit,
The DC voltage component included in the input signal input to the input terminal 100 is detected. Reference numeral 10 denotes an up / down level shift circuit, which steps up and down the DC voltage output from the voltage detection circuit 9 to produce a first potential VDD and a second potential VSS, and both potentials are the analog switch function block 1
20 and the level shift circuit 8.

Further, in the analog signal switching circuit according to the second embodiment, the configuration of each circuit not shown in FIG.
The configuration is the same as that shown in FIG. 1 of the first embodiment except for the reference voltage source 7 in the first embodiment which corresponds to the voltage detection circuit 9 and the vertical level shift circuit 10.

Next, the operation will be described. First, when an input signal composed of an analog signal and a bias signal is input to the input terminal 100, the voltage detection circuit 9 detects a DC component included in the input signal, that is, a bias voltage.

The upper / lower level shift circuit 10 receives the bias voltage detected and output by the voltage detection circuit 9 and boosts it to generate the first potential VDD, and at the same time reduces the bias voltage. The second potential VSS is generated, and both the first and second potentials VDD and VSS are supplied to both the analog switch function block 120 and the level shift circuit 8.

Here, an example of the circuit configuration of the voltage detection circuit 9 and the upper / lower level shift circuit 10 is shown in FIG. 5, and its operation will be described in detail. As shown in FIG. 5, the input terminal 100
The input signal input to the input terminal is impedance-converted by a voltage follower type operational amplifier 80 connected to the input terminal 100, and is converted into a bias signal only by a low-pass filter including a resistor 82 and a capacitor 87 whose one end is grounded. Further, this is again impedance-converted by another voltage follower type operational amplifier 81, and then a plurality of diodes 9 connected in series are connected.
It is input between the diode 92 of 1 to 94 and the diode 93.

Then, the input bias signal is
The voltage is boosted by the diodes 91 and 92, its collector terminal is connected to the power supply 400, and the constant current source 8
The signal is input to the base terminal of the NPN transistor 88, which is connected to the emitter follower by 4 and biased by the resistor 83. Then, the voltage of the boosted bias signal is slightly reduced by the base-emitter voltage of the NPN transistor 88 to become the first potential VDD (bias voltage + 2.5V), which is output from the VDD terminal 600. It

At the same time, the voltage of the bias signal is reduced by the diodes 93 and 94, its collector terminal is grounded, and the resistor 8 of the PNP transistor 89 connected to the emitter follower by the constant current source 85 is connected.
The voltage of the bias signal, which has been input to the base terminal biased by 6, is slightly boosted by the base-emitter voltage of the PNP transistor 89, and the second potential VSS (bias voltage − 2.5V)
Which is output from the VSS terminal 700.

As described above in the first embodiment, the analog switch function block 120 and the level shift circuit 8 to which the first and second potentials VDD and VSS are respectively supplied in this manner are provided. , From the signal processing circuit 6 to High
When a drive signal of a voltage level is output, the level shift circuit 8 converts the voltage level to VDD, and the drive voltage VDD causes the analog switch function block 12 to operate.
The analog switch 1 of 0 is turned off, the analog switch 2 is turned on, the analog signal input to the input terminal 200 is impedance-converted by the operational amplifier 5 and is input to the signal processing circuit 6, and the drive signal of Low voltage level is also supplied. Is output, the analog switch 1 is turned on and the analog switch 2 is turned off by the drive voltage VSS converted by the level shift circuit 8, and the analog signal input to the input terminal 100 is impeded by the operational amplifier 5. The converted signal processing circuit 6
Entered in.

As described above, according to the second embodiment, the analog signal switching circuit formed by mixing bipolar and CMOS elements is provided with the voltage detection circuit 9 and the upper and lower level shift circuit 10, and the DC voltage of the input signal is supplied. The component is detected by the voltage detection circuit 9, and the DC voltage is boosted and depressurized by the upper and lower level shift circuit 10 to generate the first potential VDD and the second potential VSS. It is not necessary to know the voltage of the included bias signal in advance, and even if bias signals of different voltages are applied, the above-mentioned first potential VDD and second potential VSS can always be output, The first and second potentials VDD and V
CM including the above analog switches 1 and 2 and an inverter 3 for alternately selecting two kinds of analog signals for SS
The level shift circuit 8 which supplies the power voltage to the analog switch function block 120 having the OS structure and also converts the voltage level of the drive signal of the signal processing circuit 6 into the drive voltage level of the analog switches 1 and 2, The first and second potentials VDD and VSS are supplied so that the drive voltage of the analog switches 1 and 2 output by the level shift circuit 8 becomes VDD or VSS. The drive voltage range of 2 is the above first
Between the potential VDD of the analog switch 1 and the second potential VSS, and the voltage applied between the gate and the source of the analog switches 1 and 2 is suppressed to a low level. As a result, the withstand voltage of the analog switches 1 and 2 having the CMOS structure can be made low, and the analog signal switching circuit having the analog switches manufactured by the process of forming the 5V CMOS device can be obtained.

Although the voltage detection circuit 9 and the upper and lower level shift circuit 10 are provided on the input terminal 100 side in the second embodiment, they may be provided on the input terminal 200 side. It goes without saying that it has the same effect.

Example 3. FIG. 6 is a block diagram showing a part of an analog signal switching circuit according to the third embodiment of the present invention. The circuit of the part not shown in FIG. 6 is the same as that of FIG. It has the same circuit configuration as that of FIG. 4 and FIG. 5 in the second example.
In FIG. 6, 220 is a clamp circuit that limits the input signal voltage to the analog switch function block 120. This is composed of two resistors 11 and 11 ′ each having one end connected to the input terminals 100 and 200, and the resistors. 11, 1
Two diodes 1 each having its anode connected to the other end of 1'and its cathode connected to the VDD terminal 600
2, 12 'and the cathodes of the resistors 11 and 11' are respectively connected to the other ends of the resistors 11 and 11 ', and the anodes thereof are connected to the VSS terminal 70.
It consists of two diodes 13, 13 'connected to 0.

The basic operation of the analog signal switching circuit according to the third embodiment of alternately selecting two kinds of analog signals input from the input terminals 100 and 200 and supplying the selected analog signals to the signal processing circuit 6 is as follows. Since it is the same as the operation described in the first or second embodiment, only the difference in the operation will be described below.

For example, the analog switch function block 1
The operating voltage range of 20, that is, the potential difference between the first potential VDD and the second potential VSS is set to 5 V, the voltage of the analog signal included in the input signal input to the input terminal 100 is high, and its amplitude is large. If the voltage exceeds 5V, VDD terminal 600
Since it exceeds the first potential VDD which is set to, the input terminal 10 is connected through the resistor 11 and the diode 12.
A current of a voltage exceeding the first potential VDD flows from 0 to the VDD terminal 600, and the upper limit of the voltage input to the analog switch 1 is limited to the voltage obtained by subtracting the forward voltage of the diode 12 from the VDD voltage. To be done.

At the same time, since the second potential VSS set at the VSS terminal 700 is dropped, the second potential is applied from the VSS terminal 700 to the input terminal 100 via the resistor 11 and the diode 13. A current corresponding to the lower voltage flows, and the lower limit of the voltage input to the analog switch 1 is limited to the voltage obtained by adding the VSS voltage and the forward voltage of the diode 13. Then, even when the amplitude voltage of the analog signal included in the input signal input to the input terminal 200 exceeds 5 V, the resistance 11 ′ and the diode 1
By the action of 2'and 13 ', the voltage input to the analog switch 2 is limited as described above.

As described above, according to the analog signal switching circuit of the third embodiment, the clamp circuit 220 is provided next to the input terminals 100 and 200 of the analog signal switching circuit of the first or second embodiment. In addition to being able to use an analog switch having a low withstand voltage CMOS structure by suppressing the voltage applied between the gate and source of the analog switches 1 and 2, the analog signal switching circuit is used as a sensor interface. If the sensor characteristics or sensitivity change,
When the output voltage of the sensor changes, the voltage of the input signal of the analog signal switching circuit changes, and an analog signal whose amplitude voltage exceeds the voltage between the first and second potentials VDD and VSS is input. Also, by limiting the voltage input to the analog switch having the CMOS structure, it is possible to prevent the destruction or malfunction of the MOS transistor which is a constituent element of the analog switch.

Example 4. The fourth embodiment of the present invention will be described below. FIG. 7 is a circuit diagram showing an analog signal switching circuit according to the fourth embodiment. In the figure, the same reference numerals as those in the first to third embodiments represent the same or corresponding portions,
220 'is a clamp circuit and includes diodes 33, 34
And resistors 35, 36, 37 and 42, NPN transistors 38 and 40, and PNP transistors 39 and 41 to limit the voltage of the input signal to a predetermined voltage.

Next, the operation will be described. First, the input signal composed of the analog signal input to the input terminal 200 and the bias signal is input to the resistor 35 of the clamp circuit 220 ′.
P channel M that constitutes the analog switch 2 via
It is input to each drain terminal of the OS transistor 14 and the N-channel MOS transistor 15.

At this time, in the reference voltage source 7, the resistor 20 connected in series between the power supply terminal 400 and the ground terminal 300,
Of the voltage obtained by dividing the power supply voltage Vcc by 21 and 22, the divided voltage at the connection point between the resistor 20 and the resistor 21 is applied to the base terminal of the NPN transistor 24 connected to the emitter follower via the resistor 26, The division voltage at the connection point between the resistor 21 and the resistor 22 is applied to the base terminal of the PNP transistor 25 connected in the emitter follower via the resistor 23.
The divided voltage applied to the PNP transistor 25 is current-amplified to a first potential VDD higher than the bias voltage by a predetermined voltage at its emitter terminal, and the divided voltage applied to the PNP transistor 25 is current-amplified. A second potential V lower than the bias voltage by a predetermined voltage at the emitter terminal
It is SS.

Then, the first potential VDD is supplied to the drain terminal and the back gate of the P channel MOS transistor 31 of the inverter 3 and the back gates of the P channel MOS transistors 14 and 14 'of the analog switches 1 and 2. The second potential VSS is supplied to the source terminal and the back gate of the N channel MOS transistor 32 of the inverter 3 and the back gates of the N channel MOS transistors 15 and 15 'of the analog switches 1 and 2.

On the other hand, in the clamp circuit 220 ', when the connection point between the resistor 35 and the analog switch 2 is point A, the NPN transistor 38 having the collector terminal connected to the power supply terminal 400 is connected to the point A. Is connected to the emitter terminal of a PNP transistor 39 whose collector terminal is connected to the ground terminal 300, and one end of the base terminal of the NPN transistor 38 is connected to the power supply terminal 400. Connected the resistor 37 and the anode of the diode 33 whose cathode is supplied with the second potential VSS,
Since the base terminal of the PNP transistor 39 is connected to the resistor 36 whose one end is connected to the ground terminal 300 and the cathode of the diode 34 whose first potential VDD is input to its anode, When the amplitude voltage of the analog signal included in the input signal input to the input terminal 200 is large and the upper side of the analog signal exceeds the first potential VDD, from the point A, the PNP transistor 39 and the resistor 36. When a current flows to the ground terminal 300 via the ground terminal 300 and the lower side of the analog signal falls below the second potential VSS, the power supply terminal 400 connects the resistor 37 and the NPN transistor 38 to the A terminal. A current will flow to the point, so that the amplitude voltage of the analog signal is always the first potential VDD.
Then, the voltage is maintained at the potential difference from the second potential VSS and is input to the analog switch 2.

Similarly, an analog signal input from the input terminal 100 to the analog switch 1 via the resistor 42 has its base terminal connected to the resistor 37 and the NPN transistor 40 having its base terminal connected. Due to the action of the connected PNP transistor 41, the potential difference between the first potential VDD and the second potential VSS is maintained. A drive signal for the analog switches 1 and 2 is output from the signal processing circuit 6 to the level shift circuit 8, and the drive signal is applied to the base terminal of the grounded NPN transistor 28 of the level shift circuit 8. Is entered.

Here, the collector terminal of the NPN transistor 28 is connected to the first terminal via the resistors 27 and 29.
Potential VDD is supplied to the resistor 27 and the resistor 2
The second potential VSS is applied to the gate terminal between
Then, the collector terminal thereof is connected to the emitter terminal of the NPN transistor 30 to which the power supply voltage Vcc is supplied, and further the two MOSs forming the inverter 3 are connected.
Gates of the transistors 31 and 32, the N-channel MOS transistor 15 of the analog switch 2 and the P-channel MOS transistor 1 of the analog switch 1
4 ′ is connected to each gate, and the P-channel MOS transistor 14 of the analog switch 2 and the N-channel MO of the analog switch 1 are connected to the output terminal of the inverter 3.
Each gate of the S transistor 15 'is connected.

Therefore, when the drive signal is at the high voltage level, the collector-emitter of the NPN transistor 28 becomes conductive, so that the potential of the collector terminal becomes the level of the ground terminal 300 and the NPN transistor 30 has the potential. The voltage at the emitter terminal is the voltage obtained by subtracting the base-emitter voltage VBE of the NPN transistor 30 from the second potential VSS. And this VSS
-VBE voltage is the P channel MO of the analog switch 1
The VDD voltage, which is input to the gates of the S-transistor 14 'and the N-channel MOS transistor 15 of the analog switch 2 and at the same time is inverted by the inverter 3 to output the VSS-VBE voltage, is output as
By inputting to the gates of the channel MOS transistor 15 'and the P-channel MOS transistor 14 of the analog switch 2, the analog switch 1 is turned on, the analog switch 2 is turned off, and the analog signal input to the input terminal 100 is input. Are sent to the signal processing circuit 6.

When the drive signal is at the Low voltage level, the collector-emitter of the NPN transistor 28 becomes non-conductive, and the first potential VDD is
The VSS voltage that is output by inverting this with the inverter 3 is input to the respective gates of the analog switches 1 and 2 in the relationship opposite to that when the above-mentioned drive signal is at the high voltage level. The switch 1 is turned off, the analog switch 2 is turned on, and the analog signal input to the input terminal 200 is sent to the signal processing circuit 6.

Then, the above-described operation is repeated in accordance with the drive signal output from the signal processing circuit 6, and the analog signal input to the input terminals 100 and 200 has its amplitude voltage restricted and the analog signal is input. Switches 1 and 2
When it passes through, the voltage applied between the gate and the source is suppressed, and the voltage is alternately taken out and supplied to the signal processing circuit 6.

As described above, in the analog signal switching circuit according to the fourth embodiment, the clamp circuit 220 'for limiting the amplitude voltage of the analog signal included in the input signal between the first potential VDD and the second potential VSS is used. , The first and second potentials VD on the back gates of the analog switches 1 and 2.
The reference voltage source 7 for supplying D and VSS, and the voltage of the drive signal input to the gates of the analog switches 1 and 2 from the first potential VDD and the second potential VSS between the base and emitter of the NPN transistor 30. Since the level shift circuit 8 for converting the voltage VBE into two potentials is provided, the voltage of the input signal fluctuates and its amplitude voltage exceeds the voltage between the first and second potentials VDD and VSS. Even if an analog signal is input, when the analog signal is input to the analog switches 1 and 2 having the CMOS structure, the clamp circuit 220 ′ limits the amplitude voltage. The voltage is kept at a voltage within the potential difference between the first potential VDD and the second potential VSS, preventing overvoltage from being applied to the analog switches 1 and 2. It is a component of a breakdown of the MOS transistor, or can prevent a malfunction,
Further, the reference voltage source 7 and the level shift circuit 8
And the bias voltage included in the input signal is
Therefore, the voltage applied between the gate and the source of the analog switches 1 and 2 can be suppressed to a low level, whereby an analog switch having a low withstand voltage CMOS structure can be used.

Example 5. An analog signal switching circuit according to the fifth embodiment of the present invention is a P-channel MOS transistor 14 and an N-channel MO transistor according to the first to fourth embodiments.
As shown in FIG. 8, the structure of the analog switches 1 and 2 including the S transistor 15 is a structure using only the P-channel MOS transistor 14, and the power supply voltage supplied to the analog switches 1 ′ and 2 ′ is the first. Of the potential VDD.

Also in the fifth embodiment, the above first to fourth embodiments are performed.
Similarly, the voltage applied between the gate and the source of the analog switches 1'and 2'can be kept low, and the analog signals input to the input terminals 100 and 200 can be alternately taken out and sent to the signal processing circuit 6. An analog signal switching circuit using the analog switches 1'and 2'having a low breakdown voltage MOS structure can be provided.

Example 6. In the analog signal switching circuit according to the sixth embodiment of the present invention, the structure of the analog switches 1 and 2 is a P channel M as shown in FIG.
This is a structure in which only the OS transistor 15 is used, and the power supply voltage supplied to the analog switches 1 ″ and 2 ″ is only the second potential VSS. This also enables the gates of the analog switches 1 ″ and 2 ″. The voltage applied between the sources can be suppressed low, and an analog signal switching circuit using analog switches 1 ″ and 2 ″ having a low breakdown voltage MOS structure can be realized.

In the fifth embodiment and the sixth embodiment, the inverter 3 shown in FIGS. 8 and 9 is the same CMOS device as the first to fourth embodiments, and the inverter 3 has the first Both the potential VDD and the second potential VSS are supplied as the power supply voltage.

[0059]

As described above, according to the present invention, a plurality of input terminals are individually provided to a plurality of input terminals in an embedded semiconductor integrated circuit in which a bipolar element and a CMOS element are formed in a mixed manner in one integrated circuit. An analog signal switching circuit that selects a predetermined analog signal from the input analog signal to which the bias voltage is applied, converts the impedance of the analog signal, and inputs the analog signal to the signal processing means included in the analog signal switching circuit is provided at a first predetermined potential higher than the bias voltage. , And a voltage supply means for supplying two voltage signals of a second predetermined potential lower than the bias voltage, and two voltage signals of the first predetermined potential and the second predetermined potential, and the signal processing Voltage conversion means for converting the input voltage of the drive signal output by the means into a binary output drive voltage and outputting the binary output drive voltage, and the first predetermined potential and the second predetermined potential. One of a voltage as its power supply voltage, is driven by the output drive voltage in which the voltage converting means is output,
Analog signal switching means having a MOS structure for selecting a predetermined analog signal from the plurality of analog signals and outputting the selected analog signal toward the signal processing means, the first predetermined potential and the second The predetermined potential of
Since the potential difference between them is larger than the amplitude voltage of the analog signal and does not exceed the withstand voltage of the analog signal switching means having the MOS structure, the drive signal output from the signal processing circuit is changed according to the voltage level thereof. By converting the voltage into the first or second predetermined potential level by the voltage converting means, and driving the analog signal switching means whose power supply voltage is the two voltages by the converted binary output drive voltage. The range of the effective voltage of the analog signal including the bias voltage input to the analog signal switching means is narrowed from the second predetermined potential to the first predetermined potential, and the withstand voltage of the analog signal switching means is increased. Even if an input signal in a voltage range exceeding it is input, it is possible to lower the effective voltage and selectively extract it for processing. An analog signal switching circuit having an OS structure, which can reduce the withstand voltage of the analog signal switching means, has high versatility, and uses an analog signal switching means manufactured by a simple and general forming process to reduce the manufacturing cost. There is an effect that can be obtained.

Further, according to the present invention, the voltage supply means is a voltage detection means for detecting the bias voltage applied to the analog signal, and the level of the detected voltage is increased or decreased by a predetermined value. Since it comprises the level shift means for shifting to the first predetermined potential and the second predetermined potential, the first and second predetermined potentials are generated in accordance with the change of the bias voltage. Since it is not necessary to preliminarily check the bias voltage included in the input analog signal in the device in which the analog signal switching circuit is manufactured to determine the circuit configuration at the time of manufacturing the analog signal switching circuit, a highly versatile analog signal switching circuit can be provided. There is an effect that can be obtained.

Further, according to the present invention, the amplitude voltage of the analog signal is applied to the first predetermined potential and the second predetermined voltage to the next stage of each input terminal to which the analog signal including the bias voltage is input. Since the input voltage limiting means for limiting the voltage to the predetermined potential is provided, even if the amplitude voltage of the analog signal at the input terminal fluctuates, its amplitude is always input to the analog signal switching means. The voltage can be kept within the range of the potential difference between the first predetermined potential and the second predetermined potential, and there is an effect that destruction of the element of the analog signal switching means or malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an analog signal switching circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of each voltage level in the analog signal switching circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an analog switch in the analog signal switching circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a part of an analog signal switching circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a power supply detection circuit and an upper / lower level shift circuit in an analog signal switching circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing an analog signal switching circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an analog signal switching circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing analog switches in an analog signal switching circuit according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing analog switches in an analog signal switching circuit according to a sixth embodiment of the present invention.

FIG. 10 is a block diagram showing a conventional analog signal switching circuit.

FIG. 11 shows a conventional analog signal switching circuit for a sensor
The block diagram which shows the case where it is used as an interface.

[Explanation of symbols]

1, 2 Analog switch 3 Inverter 5 Operational amplifier 6 Signal processing circuit 7 Reference voltage source 8 Level shift circuit 9 Voltage detection circuit 10 Upper and lower level shift circuit 11, 11 'Resistor 12, 12', 13, 13 'Diode 14, 14', 31 Pch CMOS transistor 15, 15 ', 32 Nch CMOS transistor 33, 34 Diode 20-23, 26, 27, 29 Resistor 35-37, 42 Resistor 24, 28, 30, 38, 40 NPN transistor 25, 39, 41 PNP transistor 65 -68 resistance 69-71 operational amplifier 72,73 sensor 80,81 operational amplifier 82,83,86 resistance 84,85 constant current source 87 capacitor 88 NPN transistor 89 PNP transistor 91-94 diode 100,200 input terminal 120 Na logging switch function block 220, 220 'clamp circuit 300 ground terminal 400 power terminal 500 signal output terminal 600 VDD terminal 700 VSS terminal 1000 an analog signal switching circuit

Claims (6)

[Claims] 1. A bipolar device and a CMOS device
In a mixed-type semiconductor integrated circuit formed in a mixed manner in one integrated circuit, a predetermined analog signal is selected from the analog signals to which the bias voltages individually input to a plurality of input terminals are applied, and impedance conversion is performed on the selected analog signal. An analog signal switching circuit for inputting to the signal processing means by means of a voltage supply means for supplying two voltage signals of a first predetermined potential higher than the bias voltage and a second predetermined potential lower than the bias voltage; Two voltage signals of a predetermined potential of 1 and the second predetermined potential are supplied, and voltage conversion means for converting the input voltage of the drive signal output by the signal processing means into a binary output drive voltage and outputting the binary output drive voltage, Driven by the output drive voltage output from the voltage conversion means, with the two voltages of the first predetermined potential and the second predetermined potential as its power supply voltages, An analog signal switching unit having a MOS structure for selecting a predetermined analog signal from a plurality of analog signals and outputting the selected analog signal to the signal processing unit, the first predetermined potential and the second 2. The analog signal switching circuit according to claim 1, wherein the predetermined potential is greater than the amplitude voltage of the analog signal and does not exceed the withstand voltage of the analog signal switching means having the MOS structure. 2. The analog signal switching circuit according to claim 1, wherein the voltage supply means converts a power supply voltage of the analog signal switching circuit to generate the first predetermined potential and the second predetermined potential. An analog signal switching circuit characterized by being a voltage source. 3. The analog signal switching circuit according to claim 1, wherein the voltage supply means detects a bias voltage applied to the analog signal, and a level of the detected voltage is a predetermined value. The analog signal switching circuit is characterized by comprising level shift means for shifting the signal upward or downward to generate the first predetermined potential and the second predetermined potential. 4. The analog signal switching circuit according to claim 1, wherein the amplitude voltage of the analog signal is added to the next stage of each input terminal to which the analog signal including the bias voltage is input. An analog signal switching circuit comprising input voltage limiting means for limiting a voltage between a first predetermined potential and the second predetermined potential. 5. The analog signal switching circuit according to any one of claims 1 to 4, wherein the analog signal switching means has two analog switches having a CMOS structure composed of a P channel MOS transistor and an N channel MOS transistor. And an inverter, wherein the two analog switches connect the gates of different channels to each other, connect one of the interconnected gates to the output of the inverter, and connect the other interconnected gate of The input terminal of the inverter is commonly connected to the output terminal of the voltage converting means, and the first predetermined potential is applied to the back gates of the P channel MOS transistors of the two analog switches and the inverter. The back gate of each N-channel MOS transistor has the above-mentioned second position. Potential is applied, and the two analog switches of the analog signal switching means, said voltage converting means to the input drive voltage equal to the first predetermined potential, said second predetermined potential 2
By the drive signal output by converting to the output drive voltage of the value,
An analog signal switching circuit, wherein an analog signal input to each source or drain is selectively output from the drain or source. 6. The analog signal switching circuit according to any one of claims 1 to 4, wherein the analog signal switching means is two analog switches using a P-channel or N-channel MOS transistor. And an inverter having an output terminal connected to the gate of any one of the two analog switches using two types of P-channel and N-channel MOS transistors, and the input terminal of the inverter and the output of the inverter. Another one that does not connect the ends
The gates of two analog switches are commonly connected to the output terminal of the voltage conversion means, and the back gate of the P-channel MOS transistor has the first predetermined potential and the back gate of the N-channel MOS transistor. Is applied with the second predetermined potential, and in the two analog switches of the analog signal switching means, the voltage conversion means has the first predetermined potential and the second predetermined potential with respect to the input drive voltage thereof. Equal to 2
By the drive signal output by converting to the output drive voltage of the value,
An analog signal switching circuit characterized in that it selectively outputs two analog signals input to respective sources or drains from the drains or sources.