JPH07159494A - Monitor burn-in device - Google Patents

Abstract

PURPOSE:To efficiently test by discriminating product classification code at I/O board unit provided for a burn-in board loaded with an IC memory to be tested and conducting a mask control for judging good or bad with a comparator. CONSTITUTION:IDO of a product classification terminal 5 is defined as logic '0' and the terminal ID1 in open state is practically set to logic '1'. The information of the terminal 5 provided to this burn-in board (BT board) 1 is input to an I/D board 2 constituted correspondingly one-to-one to the BT board 1. In a judging control part 3, a two input AND circuit for outputting mask control signal to a comparator 6 converts the signal from a terminal provided on the BT board 1 into negative input and activates the comparator 6. With another input of strobe signal, the stroke signal does not conduct in the AND circuit when the signal from the terminal 5 is logic '0', and the judgment of good or bad in the comparator 6 is masked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory testing device, and more particularly to a monitor burn-in device for performing a burn-in test while monitoring an output signal of a partially non-defective memory.

[0002]

2. Description of the Related Art Recently, in a burn-in test of a semiconductor memory (referred to as "IC memory"), a monitor burn-in system has become popular in place of the conventional dynamic burn-in system. This system detects an output signal of an IC memory under test (hereinafter referred to as "DUT"; Device Under Test) in order to improve the reliability of burn-in and secure an optimization time, and determines whether the output signal is good or bad.

In addition, a test burn-in system is also widely used in which a part of the test conventionally performed by the general-purpose memory tester is carried out at the burn-in test. Here, both of them are referred to as monitor burn-in system. A device that enables the burn-in test is referred to as a monitor burn-in device and will be described below.

FIG. 4 shows a block diagram of a conventional monitor burn-in device. Generally, a monitor burn-in device has a DUT
It is possible to install multiple burn-in boards 1 (hereinafter referred to as "BT boards") equipped with
A plurality of I / O boards 2 corresponding to the boards are also installed. Then, the pattern generator 7 generates a test pattern such as an address signal and a write data signal, the timing generator 8 generates a clock signal, and these are generated through a driver (not shown) in the I / O board 2. Signal is applied to the DUT (not shown) on the BT board 1.

Generally, in the burn-in test by the monitor burn-in device, the test operation of the DUT is divided into a burn-in mode and a test mode. In the burn-in mode, a test pattern and a clock signal are continuously applied to all DUTs under a certain temperature environment at the same time for a predetermined time, and the output signal is not detected.

Next, in order to confirm the functional operation of each DUT after burn-in, a test mode is executed in which the output signal of the DUT is detected and a pass / fail judgment is made. In the BT board 1 used in the monitor burn-in device, the device power supply, address signal, and I / O signal are commonly wired to all DUTs, and the clock signal is divided into several DUTs on the BT board. However, it is normal that the wiring is commonly made in this block. This clock signal is called a scan signal, and which functional terminal of the DUT is wired depends on the memory type.

FIG. 3 shows a wiring example of the BT board 1 having eight IC memories under test (DUT) of 4 word × 2 bit configuration. Here, for convenience of description, only the address (A0, A1), chip select (CE), and I / O (I / O0, I / O1) of the DUT 4 are described as necessary signals, and other signals for other terminals are described. The description is omitted. Further, the CE terminal of the DUT 4 can set the I / O terminal of the DUT 4 to a high impedance state in the read mode by its signal logic.

Address signal ADD0 of the monitor burn-in device,
ADD1 is commonly connected to all DUTs (A1 to A4, B1 to B4). Also, CLK1 of the scan signal is A1 to A4
C of 4 DUTs (these four DUTs are referred to as “row A”)
The CLK2 is connected to the E terminal, and the CLK2 is connected to the CE terminals of the 4DUTs B1 to B4 (this row is referred to as "B row").

The input and output signals of the DUT are I / O0-
It is connected to the I / O7 terminal. That is, I / O0,
I / O1 is DUTA1, and I / O0 and I / O1 of B1
Are connected in common, and I / O2 and I / O3 are also connected to DU
Commonly connected to I / O0 and I / O1 of TA2 and B2,
I / O4 and I / O5 are I / O0 and I of DUTA3 and B3
Commonly connected to / O1 and I / O6 and I / O7 are DUT
It is commonly connected to I / O0 and I / O1 of A4 and B4.

In the burn-in mode, the scan signals CLK1 and CLK2 are applied with the clock signal at the same timing, and the DUTs on all BT boards operate simultaneously.

Next, in the test mode, first, 4D in the A-row is used.
A clock signal is applied to the scan signal CLK1 so that the UT is in an output state, and the scan signal CLK2 of the B column is set to, for example, a logical "1" level, whereby the four DUTs of the B column are
The outputs of B1 to B4 are in a high impedance state.

Secondly, the scan signals CLK1 of the four DUTA1 to A4 in the A column are set to the logic "1" level to put the outputs in a high impedance state, and a clock signal is applied to the scan signal CLK2 in the B column to apply the B signal in the B column. Test four DUTB1-B4. As described above, in the test mode, the test is sequentially performed in units of DUT groups to which scan signals are commonly applied.

In the monitor burn-in device, the function of masking the output judgment of an arbitrary DUT of the DUT coordinates arranged on the BT board and the function of masking the judgment of an arbitrary comparator of a plurality of comparators are provided by a plurality of I / O. O board 2
Have in common.

In the former case, when the DUT is not mounted due to a malfunction of the specific DUT coordinate socket or the like on the BT board 1 or when a fraction is generated in the mounting, the unmounted portion of the DUT is not.
This is to prevent a defect determination from occurring with respect to the coordinates. In the latter case, when the I / O bit configuration of the DUT is not an integer fraction of the number of comparators on the device side per BT board, a defect judgment is not made for unused comparators. is there. In either case, the judgment mask control of the comparator automatically controlled by the device based on the DUT information mounted on the BT board and the BT board wiring information is performed.

By the way, when the number of input / output data bits of the IC memory (hereinafter, referred to as "I / O bit number") is plural, it depends on the customer's IC memory application system. That is not required, and provision of partially good memory is also required.

For example, if a memory having an I / O bit number of 4 bits is defective by 1 bit, that is, if the range of 3 I / O bits is a good product, this IC memory is a partially good memory having an I / O bit number of 3 bits. Is manufactured as.
In order to obtain such a partially non-defective memory, a preliminary test is first performed in lot units in the test process.

In the preliminary test, one lot is classified into a completely non-defective product, a partial non-defective product and a completely defective product, and the partial non-defective product is further classified by defective I / O bit number. The flow is the same as the test flow for a perfectly good product. That is, the partially good product is I /
If the O-bit configuration is, for example, a 4-bit memory, I / O1
There are a maximum of 4 categories from defective bit only to defective 4th bit. Including perfect non-defective products, the preliminary test shows that the sub-lots flowing in the burn-in test and electrical characteristic test in the next process are divided into 5 categories. become.

[0018]

In such a conventional monitor burn-in device, there is a problem in test efficiency when performing a burn-in test (which means a monitor burn-in for detecting an output signal) on the above-mentioned partially non-defective memory.

As shown in FIG. 3, in the wiring of the BT board for the monitor burn-in device, the I / O terminals of a plurality of DUTs are commonly wired to the comparator line.
On the BT board, DUs with different defective I / O bit numbers
T cannot be mixed and mounted.

On the other hand, even if the DUTs having the same defective I / O bit numbers are collected and mounted in units of BT boards, the I / Os configured on the monitor burn-in device side have a one-to-one correspondence with the BT boards. Since there is no function of masking the judgment of the comparator on the O board, it is not possible to install BT board units having DUTs with different defective I / O bit numbers in a mixed manner in the monitor burn-in device.

That is, as a result of the preliminary test, the burn-in test can be performed only in units of DUTs having the same defective I / O bit numbers divided into a plurality of sub-lots. This means that burn-in for one lot requires a test time which is a multiple of the normal burn-in test time, which significantly reduces the processing capacity of the monitor burn-in device.

Therefore, the present invention solves the above problems and efficiently monitors a partially non-defective memory having a defective I / O bit in a monitor burn-in test of an IC memory composed of a plurality of I / O data bits. The purpose is to provide a means that enables a burn-in test.

[0023]

In order to achieve the above object, the present invention performs an aging test while applying a test pattern under a predetermined set temperature environment, and at the same time, under test I
In a monitor burn-in device for judging pass / fail of an output signal of a C memory, a product type code is identified for each I / O board provided corresponding to a burn-in board having the IC memory under test, and based on the code, the product type code is identified. Provided is a monitor burn-in device characterized in that mask control for judging quality of a comparator is performed for each I / O board.

[0024]

According to the present invention, the product type code is recognized for each I / O board formed in one-to-one correspondence with the burn-in board on which the DUT is mounted, and the pass / fail judgment of the comparator is masked for each I / O board. It is possible to carry out a burn-in test including a partial non-defective memory divided into a plurality of sub-lots by a preliminary test in a batch at a time, and an efficient monitor burn-in of the partial non-defective memory can be performed.

[0025]

The present invention will be described below with reference to the drawings.

[0026]

[Embodiment 1] FIG. 1 is an explanatory diagram for explaining the configuration of a first embodiment of the present invention. In the figure, a block diagram of the I / O board 2 and an example of signal connection between the I / O board 2 and the DUT 4 on the BT board 1 are shown.

In the following, a DUT 4 having 2 I / O data bits will be described as an example. On the BT board 1, the B
The product type terminal 5 indicating the type of the partially non-defective memory mounted on the T-board 1, that is, which bit is the defective I / O bit, and which I / O bit to mask the determination is wired. There is. The terminal 5 corresponds to the product ID code.

In FIG. 1, of the product type terminals 5, ID0
Is connected to the ground terminal, ID1 is in an open state, and the DUT4 mounted on the BT board 1 indicates that the I / O first bit is a defective bit in the preliminary test described above.

The ID0 of the product type terminal 5 is a logical "0", and the terminal ID1 in the open state is a logical "1". The information of the product type terminal 5 provided on the BT board 1 is input to the I / O board 2 configured in a one-to-one correspondence with the BT board, and in the test mode after the burn-in start, the determination mask control unit 3 masks the quality judgment of the comparator 6 (in FIG. 1, the comparators respectively connected to the I / O0 and I / O2 terminals) corresponding to the logic “0” of the product type terminal 5.

That is, in the judgment mask control section 3,
2-input AN that outputs a mask control signal to the comparator 6
The D circuit has a signal from the product type terminal 5 provided on the BT board 1 as one input and a strobe signal for activating the comparator 6 as the other input, and the signal from the product type terminal 5 has a logic "0". In the case of ", the strobe signal does not conduct the AND circuit, and the pass / fail judgment of the comparator 6 is masked.

[0031]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 2 shows a block diagram of the monitor burn-in system. This system is composed of a monitor burn-in device 10, an IC insertion machine 11, and a host computer 12 that controls both devices in a comprehensive manner.

Usually, on the BT board 1, there is provided a board ID code in which identification information such as the serial number of the board itself for management is expressed by several bits to ten and several bits.

The BT board 1 mounted on the monitor burn-in device 10 has an IC in the socket on the BT board 1 in the previous stage.
The DUT is mounted by an automatic machine such as the insertion machine 11.

In addition, each DUT has already been distinguished by the defective I / O bit number in the preliminary test performed before this mounting, and when mounted on the BT board by the IC inserting machine 11,
It is known which board ID has which non-defective memory of which type is mounted on the BT board.
The code and the product ID code are paired and stored in the memory in the host computer.

Next, when the mounted BT board is mounted on the monitor burn-in device 10 and the burn-in is started,
The board ID is read for each I / O board, and the monitor burn-in device 10 uses the information to read the board ID.
The internal memory is accessed, the product ID code corresponding to the BT board ID code is recognized, and the product ID code is sent to the determination mask control unit 3 for each I / O board 2 shown in FIG. The judgment can be masked.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to these embodiments, and it goes without saying that various embodiments according to the principles of the present invention are included.

[0037]

As described above, according to the monitor burn-in system of the present invention, the quality judgment of the comparator can be mask-controlled for each I / O board in the system, so that it is divided into a plurality of sub-lots in the preliminary test. Burn-in tests including partial non-defective memory can be performed in batches,
This has the effects of suppressing a decrease in the processing capacity of the monitor burn-in device and enabling more efficient monitor burn-in of the partially non-defective memory.

Further, according to the present invention, the board ID code and the product ID code are stored in the host computer as a pair, and at the time of monitor burn-in, the mask control section of the I / O board is burned to the burn-in board. The corresponding product ID code signal is transmitted, and the I /
This is to realize automatic management of mask control of comparators in O-board units, and to particularly improve the processing efficiency of the monitor burn-in test process for partially non-defective memory.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a wiring diagram of a BT board for a monitor burn-in device.

FIG. 4 is a block diagram of a conventional monitor burn-in device.

[Explanation of symbols]

 1 Burn-in board (BT board) 2 I / O board 3 Judgment mask control unit 4 IC memory under test (DUT) 5 Product type terminal (Product ID code) 6 Comparator 7 Pattern generator 8 Timing generator 9 Judgment mask control unit 10 Monitor burn-in device 11 IC inserter 12 Host computer

Claims (4)

[Claims] 1. An aging test is performed while applying a test pattern under a predetermined set temperature environment, and an IC to be tested is also tested.
In a monitor burn-in device for judging pass / fail of an output signal of a memory, a product type code is identified for each I / O board configured corresponding to the burn-in board having the IC memory under test, and based on the product type code I said
A monitor burn-in device in which the mask control for judging the quality of the comparator is performed for each / O board. 2. A monitor burn-in device in which a product type code identifying means is provided on the burn-in board. 3. The I / O board includes a mask control section for controlling a mask for judging quality of the comparator, and the mask control section is based on a signal level of a product type code identifying means provided on the burn-in board. The monitor burn-in device according to claim 2, wherein a mask of the comparator is controlled. 4. Pair information of a burn-in board identification code and a product type code corresponding to the burn-in board is stored in the storage means of the host computer, and at the time of monitor burn-in,
A product type code signal corresponding to a burn-in board is sent from the host computer to the mask control unit of the I / O board, and the mask control unit controls the mask of the comparator based on the product type code signal. The monitor burn-in device according to claim 3.