JPH0715928B2 - Semiconductor device inspection method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method, and more particularly to a method for inspecting logic semiconductor pellets on a semiconductor wafer.

[Conventional technology]

Conventionally, in order to inspect semiconductor pellets on a semiconductor wafer, particularly logic semiconductor pellets (hereinafter referred to as gate arrays), an inspection pattern corresponding to a logic function selected in a manufacturing process is read and inspected one by one. Has been.
Further, in the method of inspecting two or more types of gate arrays having different logic functions on a semiconductor wafer, first, the inspection apparatus reads out the logic functions of one type of gate array and then an inspection pattern corresponding to the logic functions is read. Repeat all gate arrays on that type of semiconductor wafer, then read another logic function to inspect that type of logic function. In addition, the identification of these code number marks was performed by a person using a metal or stereoscopic microscope.

[Problems to be solved by the invention]

In the above-mentioned conventional inspection method, since the identification of the code number mark corresponding to the logical function is performed by a person, it takes man-hours, and another inspection pattern that does not correspond to the logical function of the gate array to be inspected by mistake. It was often the case that the product was read or the good product was judged to be defective.

It is an object of the present invention to provide a semiconductor device inspection method that solves such problems, reduces inspection man-hours, eliminates inspection errors, and enables correct inspection.

[Means for solving problems]

A semiconductor device inspection method of the present invention is a semiconductor device inspection method for inspecting two or more types of logic semiconductor pellets having different logic functions on a semiconductor wafer, and displays a code number determined in response to the logic function. Mark
The mark is identified by measuring the electrical resistance of the conductor material formed on the surface of the semiconductor pellet and forming the mark in a state where the logic semiconductor pellet is formed on the semiconductor wafer, and a plurality of inspection patterns An inspection pattern corresponding to the mark is selected and inspected.

Another method of inspecting a semiconductor device according to the present invention is the method of inspecting two or more kinds of logic semiconductor pellets having different logic functions on a semiconductor wafer, wherein an impurity layer having a conductivity type opposite to that of the semiconductor wafer is used. Selectively formed, a first electrode is formed on the surface of the impurity layer, and a second electrode is formed on the surface on which the impurity layer is not formed,
A state in which the logic semiconductor pellet is formed on the semiconductor wafer as a mark for displaying a code number determined corresponding to the logic function, and an electric resistance between the first and second electrodes and the semiconductor wafer is formed. It is characterized in that the mark is identified by measuring in step 1, and an inspection pattern corresponding to the mark is selected from among a plurality of inspection patterns to perform the inspection.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 (a) is a plan view for explaining the arrangement of gate arrays on a semiconductor wafer in the semiconductor device inspection method according to the embodiment of the present invention. In the figure, a semiconductor wafer 1 has gate arrays 2 and 3 having different logic functions.
Are aligned and formed. To identify the code number of the gate array on this semiconductor wafer, a first
The numbers are attached as shown in FIG. FIG. 1B is a block diagram showing a method for inspecting a semiconductor device according to the related art of the present invention. In the figure, a mark 4 for identifying a code number is formed on each of the gate arrays 2 and 3 on the semiconductor wafer. Here, it is made of a light-reflecting material, such as aluminum, in combination with long segments 5a, 5c and short segments 5b, 5d. On the other hand, by irradiating the mark 4 with the light 7 from the light source 6 and receiving the reflected light 7'in the light receiving portion 8, the length of the segment is measured as the amount of received light, and the mark 4
The identification unit 9 identifies the combination of the long and short segments. In this case, if the long segment is identified as “1” and the short segment is identified as “0”, the binary number is “1010”.
Can be identified. After transmitting the inspection pattern corresponding to the identified “1010” from the storage unit 10 to the inspection unit 11, the inspection is performed.

FIG. 2 is a plan view for explaining the first embodiment of the present invention, showing another mark different from the mark 4 in FIG. 1 (b). In the figure, the conductor material (aluminum, etc.)
The segment made of two square pads 13,1
It is composed of 3'and the wiring 12 connecting between them. To identify the code number, disconnect the wiring 12 and use the pads 13,1
The presence or absence of disconnection is determined by measuring the electrical resistance between 3 ', and the unmarked state is "1", the disconnected state is "0", and the mark state is identified by a binary number. ,
The inspection pattern was identified in the same manner as in the case of FIG.
The number corresponding to the base number is read from the storage unit 10, and the inspection unit 11 performs the inspection.

FIG. 3 is a sectional view for explaining the second embodiment of the present invention, and shows another mark of the mark 4 in FIG. 1 (b). In the figure, an impurity layer 15 having a conductivity type opposite to that of the semiconductor wafer substrate 14 is selectively formed, an electrode 16 is provided on the surface of the impurity layer 15, and an electrode 17 is provided on the chip surface without impurities.
To provide. If the substrate 14 is N-type and the impurity region 15 is P-type, if the substrate 14 is set to a positive potential and the electrodes 16 and 17 are set to a negative potential, the diode formed by the substrate 14 and the impurity layer reverses the PN junction. By applying a directional voltage, the electrode 16 and the substrate 14
Little current flows between and. A current flows between the electrode 17 where the impurity layer is not formed and the substrate 14. Utilizing this fact, the state of no flow is "1", the state of flow is "0", the state of the mark is identified by a binary number, and the binary number that identifies the inspection pattern in the same manner as in Fig. 1 b). The corresponding one is read from the storage unit 10 to the inspection unit 11, and the inspection unit 11 performs the inspection.

〔The invention's effect〕

As described above, according to the present invention, in two or more types of gate arrays having different logic functions of a semiconductor wafer, the mark of the code number corresponding to the logic function is electrically identified to visually check. The need for identification is eliminated, the number of man-hours for identification can be reduced, and errors such as human error can be eliminated.

[Brief description of drawings]

FIG. 1 (a) is a plan view illustrating the arrangement of gate arrays on a semiconductor wafer used in the semiconductor device inspection method of the embodiment of the present invention, and FIG. 1 (b) is a semiconductor of the related art of the present invention. FIG. 2 is a block diagram showing an inspection method of the apparatus, FIG. 2 is a plan view for explaining the first embodiment of the present invention, and FIG. 3 is a sectional view for explaining the second embodiment of the present invention. . In the figure, 1 ... semiconductor wafer, 2, 3 ... gate
Array, 4 ... mark, 5a, 5b, 5c, 5d ... segment,
6 ... Light source, 7 ... Incident light, 7 '... Reflected light, 8 ... Light receiving part, 9 ... Identification part, 10 ... Storage part, 11 ... Inspection part, 12
...... Wiring, 13, 13 '…… Electrode pad, 14 …… Semiconductor wafer substrate, 15 …… Impurity diffusion layer, 16, 17 …… Electrode.

Claims (2)

[Claims] 1. A method of inspecting a semiconductor device for inspecting two or more kinds of logic semiconductor pellets having different logic functions on a semiconductor wafer, wherein a mark for displaying a code number determined in response to the logic function is provided on the semiconductor. Formed on the surface of the pellet, by measuring the electrical resistance of the conductive material forming the mark in a state where the logic semiconductor pellet is formed on the semiconductor wafer, the mark is identified, and among the plurality of inspection patterns A method for inspecting a semiconductor device, comprising inspecting by selecting an inspection pattern corresponding to the mark. 2. A method of inspecting a semiconductor device for inspecting two or more kinds of logic semiconductor pellets having different logic functions on a semiconductor wafer, wherein an impurity layer having a conductivity type opposite to that of the semiconductor wafer is selectively formed, and A first electrode is formed on the surface of the impurity layer, and a second electrode is formed on the surface on which the impurity layer is not formed to form a mark for displaying a code number determined corresponding to the logic function. First, second
The electrical resistance between the electrode and the semiconductor wafer in a state where the logic semiconductor pellet is formed on the semiconductor wafer, thereby identifying the mark and inspecting a plurality of patterns corresponding to the mark. A method for inspecting a semiconductor device, which comprises inspecting by selecting a pattern.