JPH0715860A - Operation test circuit for digital relay and circuit malfunction detecting method - Google Patents

Abstract

PURPOSE:To prevent an erroneous trip of a breaker and to effectively test a forced operation of relay element of a digital relay by using a forced operation signal of the element to be tested for its operation as an AND signal of output signals of first, second forced operation signal output circuits. CONSTITUTION:First forced operation signal output circuits DN which output forced operation signals for forcibly operating relay elements RN and jacks JN are respectively provided for elements RN of relays. A second forced operation signal output circuit D0 and a jack J0 are provided commonly for all of a plurality of the relay elements, and AND gates AN for carrying out AND of the output signals of the first, second circuits D are provided. Since a forced operation test is executed only when the AND reaches a logical 'high', an erroneous signal output of a trip signal of a breaker is prevented, and an unnecessary power interruption is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation test circuit used when performing an operation test of an output circuit of a digital relay for realizing the function of a protection relay by using a microcomputer, and a failure detection method for the operation test circuit.

[0002]

2. Description of the Related Art FIGS. 2 and 3 show a conventional example of an operation test circuit used to perform an operation test of a relay element of a digital relay. In FIG. 2, X is a power source bus in the digital relay, J _{0 to} J _N are jacks, D _{1 to} D _N are forced operation signal output circuits that output binary signals, B _{1 to} B _N are OR gates, and R _{1 is} to R _N is a relay element, Jack J ₁
~ J _N are connected to the power bus X via jack J ₀ . Also, be provided with respect to the jack J ₁ through J _N, forced operation signal output circuit D ₁ to D _N, OR gate B ₁ .about.B _N of the N relay elements R ₁ to R _N, respectively, Jack → Force The operation signal output circuit is connected to each relay element in the order of OR gate.

Further, the OR gates B _{1 to} B _N are also fed with operation outputs based on the electric quantity of the system from the relay operation units r _{1 to} r _N , and the outputs and the output of the forced operation signal output circuit are provided. logical sum is inputted to the relay element R ₁ to R _N. Here, a conventional example will be described by taking as an example the case where the relay element R ₁ in FIG. 2 is forcibly operated.

In order to test the operation of the relay element R ₁ ,
Common jack J ₀ and insert the test plug and the jack J _1, is energized to the forced operation signal output circuit D ₁ through the jack J ₁ and the common jack J _0. Then, the forced operation signal output circuit D ₁ outputs a logic “high” signal for a certain period of time, and the OR gate B ₁ receiving the input of the logic “high” signal also outputs a logic “high” signal. The signal was directly the compulsory operation signal to the relay element R ₁ .

Further, in the circuit shown in FIG. 3, a forced operation signal output circuit is provided in duplicate for each of the relay elements. That is, the forced operation signal output circuits D _1A and D _1B are connected to the power source bus X via the jack J _1, and the signals output from the forced operation signal output circuits D _1A and D _1B are connected to the AND gate A.
Lead to ₁ to obtain the logical product, and use O as in the circuit shown in FIG.
It was used as a forced operation signal to the relay element R ₁ via the R gate B ₁ . Similarly jack J ₂ through J _N forced operation signal output circuit via the _{(D 2A, D 2B) ~} (D NA, D NB) connected to each power supply bus X, forced operation signal output circuit (D _2A, D _2B ) to (D _NA , D _NB ) output signals AN
Logically ANDed led to the D gate A ₂ to A _N, it was the forced operation signal to the relay element R ₂ to R _N through the OR gate B ₂ .about.B _N. That is, 2 for one jack
Since the forced operation signal output circuit is provided, the forced operation signal output circuit is duplicated.

Now, the conventional example shown in FIG. 3 will be described by taking the case where the relay element R ₁ is forcibly operated as an example.
When a test plug is inserted into the jack J ₁ and the duplicated forced operation signal output circuits D _1A and D _1B are energized, the forced operation signal output circuits D _1A and D _1B output a logical “high” signal for a certain period of time. . When the logical "high" signal is led to the AND gate A ₁ to obtain a logical product, the output of the AND gate A ₁ also becomes a logical "high", and the logical "high" signal is also supplied from the OR gate B ₁ which receives the logical "high" signal. A "high" signal was output, which was the forced activation signal for relay element R ₁ .

[0007]

However, in the circuit shown in FIG. 2, each relay element has only one forced operation signal output circuit. If a logic "high" signal is accidentally output to the device, this will be a forced operation signal and a trip signal will be output to the circuit breaker, resulting in unnecessary power outage.Furthermore, the failure of the forced operation signal output circuit will be monitored. There was a problem that there was no means.

Further, in the circuit shown in FIG. 3, a forced operation signal output circuit is provided in duplicate for each relay element,
The output of the duplicated forced operation signal output circuit is led to an AND gate to obtain a logical product, and the forced operation signal for the relay element is used only when the output of the AND gate becomes logical "high". Even if one of the forced operation signal output circuits that has been activated has malfunctioned and the logical "high" signal is output erroneously, the forced operation signal is not output and The trip signal will not be output accidentally. Further, it is possible to monitor the failure of the forced operation signal output circuit by monitoring the mismatch between the outputs of the duplicated forced operation signal output circuits. However, when the forced operation signal output circuit is energized due to a defect such as an internal short circuit in the jacks J _{1 to} J _N , the same problem as in the circuit shown in FIG. 2 occurs.

The present invention has been made in view of the above-mentioned problems of the prior art. Even if the forced operation signal output circuit malfunctions, the circuit breaker does not trip accidentally and the relay of the digital relay can be reliably operated. An object of the present invention is to provide an operation test circuit of a digital relay capable of performing a forced operation test of an element and a failure detection method for the circuit.

[0010]

In order to achieve the above object, in the first invention, a relay element is forcibly operated in an operation test circuit for performing an operation test of a digital relay having a plurality of relay elements. A first forcible operation signal output circuit for outputting a forcible operation signal for each relay element is provided, and a second forcible operation signal output circuit for outputting a forcible operation signal for forcibly operating the relay element is provided for all relays. One is commonly provided for the elements, and the logical product of the outputs of the first and second forced operation signal output circuits is used as the forced operation signal for the relay element.

Further, the forced operation signal and the operation output based on the amount of electricity from the system are input to the relay element via the OR gate. Further, in the second invention, each forced operation signal output circuit is provided with a monitoring timer for monitoring the duration of the output signal of the forced operation signal output circuit, and the output signals of the first and second forced operation signal output circuits are provided. The duration of the output signal is monitored by the monitoring timer before the logical product of

[0012]

In the first aspect of the invention, the first forcible operation signal output circuit is provided for each relay element, and the second forcible operation signal output circuit is provided.
One forcible operation signal output circuit is provided in common for all of the plurality of relay elements, and the logical product of the outputs of the two forcible operation signal output circuits is used as the forcible operation signal for the relay element. A logical product of the signal output from the operation signal output circuit and the output signal of the second forced operation signal output circuit is taken, and the relay element for performing the operation test only when the AND signal becomes the logic “high” On the other hand, a forced operation signal is output via the OR gate.

Further, in the second invention, by monitoring the duration of the signal output from the forced operation signal output circuit by the monitoring timer, each forced operation is performed before obtaining the logical product in the first invention. The operation check of the signal output circuit is performed. That is, when the forced operation signal output circuit continuously outputs the monitoring timer for a predetermined time or more, the forced operation signal output circuit is determined to be defective.

[0014]

1 is a diagram showing an embodiment of a forced operation signal output circuit of a relay element. The same components as those of the conventional example shown in FIG. There is. In FIG. 1, J _{0 to} J _N are jacks and D _{0 to} D _N
Is a forced operation signal output circuit, A _{1 to} A _N are AND gates,
B ₁ .about.B _N is an OR gate, T ₀ through T _N are monitoring timer.

The forced operation signal output circuits D _{0 to DN} are connected to the power source bus X via jacks J _{0 to} J _N. Further, the jack J ₀ and the forced operation signal output circuit D
₀ is commonly provided to all _N relay elements R _{1 to} RN, and includes jacks J _{1 to} J _N and a forced operation signal output circuit D.
₁ to D _N are provided on each of the relay elements R ₁ to R _N. The AND gates A _{1 to} A _N obtain the logical product of the output of the forced operation signal output circuit D ₀ and the forced operation signal output circuits D _{1 to DN} , and the AND gates A _{1 to} A
The output of the _N are directed to the OR gate B ₁ .about.B _N. The forced operation signal output circuit D is also provided to the monitoring timers T _{0 to} T _N.
Outputs of _{0 to} D _N are derived. This monitoring timer T ₀ ~
The operation of T _N will be described later.

Here, the first invention is the relay element R.₁Strong
A description will be given by taking as an example the case where the control is operated. First, J
Jack J₀And Jack J₁Insert the test plug into and
Forced operation signal output circuit D₀, D₁Energize. Then strong
Control signal output circuit D₀, D₁From each logic "ha
B signal is AND gate A₁Is output to the AN
D gate A₁Outputs a logical "high" signal. The
Logic "high" signal is OR gate B ₁Forced operation via
Relay element R as the issue₁Entered in.

The relay element Similarly, when R ₁ is forcibly operated relay elements other than the common jack J ₀ and the output subject to relay element R ₂ to R _N Jack J ₂ provided on-the forced operation signal Inserting a test plug into J _N causes the forced operation signal output circuits D ₀ and D _{2 to} D _N to output logical “high” signals to the AND gates A _{2 to} A _N. Then, the logical "high" signal is output from the OR gate B ₂ ~.
Relay elements R ₂ to R _N as a forced operation signal through the B _N
Entered in.

[0018] In the second invention, the monitoring timer T ₀ through T _N provided for forced operation signal output circuit D ₀ to D _N, respectively, as shown in FIG. 1, the forced operation signal output circuit D ₀ ~ The signal output from D _N is monitored. The output signals of the forced operation signal output circuits D _{0 to} D _N before the logical product is obtained by the AND gates A _{1 to} A _N are input to the monitoring timers T _{0 to} T _N, and the duration of the output signals is monitored. .

A predetermined time T is set in advance in the monitoring timers T _{0 to} T _N, and when the output signal is continuously output for the time T or more, the output signal is continuously output forcibly. The operation signal output circuit is determined to be defective, and an alarm indicating defective operation is output to the outside.

[0020]

According to the first aspect of the invention, each of the plurality of relay elements is provided with a forced operation signal output circuit and a jack, and further, one forced operation signal output circuit and one common to all of the plurality of relay elements. One jack is provided, and the logical product of the outputs of the two forced operation signal output circuits is obtained. Therefore, the forced operation signal output circuit for each relay and two systems of jacks are provided. A trip signal of the circuit breaker will not be erroneously output due to a defect or an internal short circuit of one jack, and unnecessary power failure can be avoided.

According to the second aspect of the invention, the output of the duplicated forced operation signal output circuit is monitored for its duration before the logical product is obtained, thereby monitoring each forced operation signal output circuit. Even if one of the forced operation signal output circuits has a defect, an alarm is output to the outside at the stage before the detection of the defect calculates the logical product.
It is possible to prevent the forced operation signal output from the ND gate from being output to the relay element due to the failure of the forced operation signal output circuit or the jack.

[Brief description of drawings]

FIG. 1 is a diagram showing an operation test circuit of a digital relay according to the present invention.

FIG. 2 is a diagram showing a conventional digital relay operation test circuit.

FIG. 3 is a diagram showing a conventional digital relay operation test circuit.

[Explanation of symbols]

X power busbar R ₁ to R _N relay elements r ₁ ~r _N relay computation unit J ₀ through J _N Jack D ₀ to D _N forced operation signal output circuit A ₁ to A _N the AND gate T ₀ through T _N monitoring timer D _1A , D _1B ~D _NA, D _NB forced operation signal output circuit

Claims (2)

[Claims] 1. A digital relay operation test circuit for performing an operation test of a digital relay including a plurality of relay elements, wherein a signal is provided for each of the plurality of relay elements and outputs a signal for forcibly operating the relay elements. First to do
A forced operation signal output circuit, and a second forced operation signal output circuit that is provided in common to the plurality of relay elements and outputs a signal for forcibly operating the relay elements, Of the plurality of relay elements, the logical product of the signal output from the first forced operation signal output circuit connected to the relay element to be subjected to the operation test and the output signal of the second forced operation signal output circuit is obtained. An operation test circuit for a digital relay, wherein the AND signal is used as a forced operation signal for a relay element that is a target of the operation test. 2. The circuit failure detection method for a digital relay operation test circuit according to claim 1, wherein each forced operation signal output circuit is provided with a monitoring timer for monitoring the duration of the output signal of the forced operation signal output circuit. , The duration of the output signal is monitored by the monitoring timer before the logical product of the output signals of the first and second forced operation signal output circuits is obtained, and the output signal continues for a predetermined time or more. A circuit failure detection method characterized in that, when it is output, the forced operation signal output circuit that outputs this output signal is determined to be defective.