JPH07154753A - Image display controller - Google Patents

Abstract

PURPOSE:To separately display plural NTSC image signals with a simple configuration by arranging them at the plural divided areas of a high-vision monitor. CONSTITUTION:A parallel processing means 3 parallelly reads respective image data stored in image data storage means NM1-NMK and stores them in a high-speed storage means 5. An image signal output means 7 reads and outputs the data stored in the high-speed storage means 5 at the speed requested by the high-vision monitor. Even when the reading speed of the image data storage means NM1-NMK is slower than the reading speed of this high definition television monitor, the image data for each camera can be separately displayed on this high-vision monitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen display control device, and more particularly to a technique for arranging and displaying a plurality of image data in respective regions of a region-divided display device.

[0002]

2. Description of the Related Art A conventional monitoring system 101 is shown in FIG. The monitoring system 101 is a system in which a plurality of monitoring cameras are installed at a plurality of places in a factory or the like and displayed on a monitor in a centralized control room or the like to monitor for any abnormality. In the monitoring system 101, one monitor M
1 is divided into 16 areas (areas A to P), and images from 16 monitoring cameras CA1 to CA16 are displayed in the areas A to P of the monitor M1.

In this system, image data sent from a plurality of surveillance cameras can be displayed on one monitor, so that it is not necessary to prepare a plurality of monitors, and the system configuration as a whole. It will be easy.

However, in the above-mentioned surveillance system, since the image data from each surveillance camera is displayed in the 1/16 area of the monitor M1, the pixels become rough and the display becomes very difficult to see.

In order to solve such a problem, the conventional NT
It is also conceivable to adopt a high-definition type camera and monitor that can obtain higher resolution than the SC type. By doing so, a clearer image using the NTSC system can be obtained and monitoring becomes easier.

However, since such a high-definition camera and high-definition monitor are still low in popularity, not only are they expensive, but providing a plurality of high-definition cameras and high-definition monitors complicates the entire system.

An object of the present invention is to solve the above problems and provide a screen display control device capable of obtaining a clear image with a simple structure.

[0008]

According to another aspect of the screen display control apparatus of the present invention, the image data storage means for storing image data from a plurality of NTSC type cameras for each image data, and the image data storage means. Output each image data as an image display signal to the high-definition monitor at a speed required by the high-definition monitor so that the stored image data for each camera is arranged and displayed in a plurality of divided areas of the high-definition monitor. Display control means for

In the screen display control device of claim 2,
The image data storage means stores the stored data in NTS.
The display control means is an NTSC memory capable of reading at a speed required by the C monitor, and the display control means stores the stored data in the high-speed storage means capable of reading the stored data and the image data storage means. Parallel processing means for reading the respective image data in parallel and storing them in the high-speed storage means, and image signal output means for reading and outputting the data stored in the high-speed storage means at the speed required by the high-definition monitor. It is characterized by having.

In the screen display control device of claim 3,
1) The high-speed storage means is a line memory including a first half portion formed of a plurality of blocks and a second half portion formed of a plurality of blocks, and a line memory having a storage capacity for one line of the high-definition monitor. , RGB
Of the two line memories, the first line memory is for odd pixels, and the other line memory is the second line memory for even pixels. 2) The writing and reading of data are alternately performed in the first line memory and the second line memory, and 3) the parallel processing means performs the above-mentioned operation for each block in the first half of the two line memories. When the read image data is stored in parallel, the image signal output means serially reads out each block in the latter half of the two line memories, and 4) the parallel processing means: In the case where the read image data is stored in parallel in each block of the latter half of the two line memories, the image signal output means includes the former half of the two line memories. Be read out serially for each block, characterized in that the performed for each component of RGB.

In the screen display control device of claim 4,
1) The divided areas of the high-definition monitor are m in the vertical direction.
2) The NTSC memory is composed of m × n small substrates corresponding to the divided areas, and the line of the input NTSC image data is the line. While thinning out the data so that the number is m / 2 of the number of lines on one screen of the high definition system,
Regarding the data after thinning, R component, G component, and B component
3) The parallel processing means converts each of the RGB components into a digital signal, and stores the digital signal. Image data of n columns are read in parallel, odd pixels are stored in the first line memory in parallel and n pixels are stored in the second line memory in parallel, and 4) the image signal output means is When image data for a specific one line is stored in the first line memory and the second line memory for each of the RGB components, the following 41) and 4 will be given.
Repeating the process of 2), 41) Continuing to the image data, for the next one line of image data, odd pixels are parallel to the first line memory and even pixels are parallel to the second line memory for n columns. 42) by alternately reading the image data stored in the two line memories, the digital data is output at a speed required by the high-definition monitor, and the output digital data is converted into analog data. , Is output to the high-definition monitor.

According to a fifth aspect of the present invention, there is provided a screen display control device having image data storage means for storing a plurality of image data for each image data, and at least one line of image data storage capacity of the display means. High-speed storage means capable of reading at a speed required by the display means, parallel processing means for reading each image data stored in the image data storage means in parallel and storing in the high-speed storage means, storage in the high-speed storage means An image signal output means for reading out and outputting the generated data at a speed required by the display means is provided.

[0013]

In the screen display control device of the first aspect, the image data storage means stores the image data from the plurality of NTSC type cameras for each image data. The display control means uses the image data as image display signals so that the image data for each camera stored in the image data storage means is displayed in a plurality of divided areas of the high-definition monitor. Output to the high-definition monitor at the speed required by the monitor. Thereby, the image data of each camera is arranged and displayed in the plurality of divided areas of the high-definition monitor.

In the screen display control device of claim 2,
The parallel processing means reads the respective image data stored in the image data storage means in parallel and stores them in the high speed storage means. Therefore, even if the reading speed of each image data stored in the image data storage means is slower than the reading speed of the high-definition monitor, the image data of each camera is arranged and displayed in a plurality of divided areas of the high-definition monitor. be able to.

In the screen display control device of claim 3,
The writing and reading of data are performed alternately in the first line memory and the second line memory, and the parallel processing means writes the read image data for each block in the first half of the two line memories. , Are stored in parallel, the image signal output means reads out serially for each block in the latter half of the two line memories. On the other hand, when the parallel processing means stores the read image data in parallel in each of the blocks in the latter half of the two line memories, the image signal output means controls The blocks in the first half of the line memory are serially read.

Therefore, even if the reading speed of the line memory is half the reading speed required by the high-definition monitor, the image data of each camera can be arranged and displayed in a plurality of divided areas of the high-definition monitor. it can. Further, since the reading and writing are separately performed in the first half and the latter half, the reading is performed serially and the writing is performed in parallel. Even if the method is different, the data reading and writing can be accurately performed.

In the screen display control device of claim 4,
The NTSC memory thins out the input NTSC image data so that the number of lines becomes m / 2 of the number of lines in one screen of the high-definition system. This makes it possible to properly display the NTSC image data in the vertical m-row divided area.

Further, the parallel processing means parallelizes the image data for the divided areas for the n columns from the small substrates for the divided areas for the n columns arranged in the same row for each of the RGB components. The odd pixels are stored in the first line memory in parallel and the even pixels are stored in the second line memory for n columns in parallel. The image signal output means, for each of the RGB components, the first line memory and the second line memory.
When the specific one line of image data is stored in the line memory of, the following process is repeated. Subsequent to the image data, with respect to the image data of the next one line, odd-numbered pixels
Of the image data stored in the two line memories alternately by storing the image data in the line memory in parallel for n columns to output the digital data at a speed required by the high-definition monitor, and output the digital data. Is converted into analog data and output to the high-definition monitor.

As described above, at the time of writing, the image data for the divided regions for n columns is read in parallel for n columns,
By storing odd-numbered pixels in the first line memory in parallel with the even-numbered pixels in the second line memory by n columns and reading the first line memory and the second line memory alternately during reading. , Even if the small substrate cannot be read at the speed required by the high-definition monitor, and by using the line memory that can be read at half the speed required by the high-definition monitor, the image data of each camera can be read by a plurality of the high-definition monitor. It can be arranged and displayed in the divided areas.

In the screen display control device of claim 5,
The parallel processing means reads the respective image data stored in the image data storage means in parallel and stores them in the high speed storage means. The high-speed storage means has a storage capacity of at least one line of image data of the display means. The image signal output means reads out and outputs the data stored in the high speed storage means at a speed required by the display means. As a result, the respective image data are arranged and displayed in the plurality of divided areas of the high-definition monitor.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Explanation of Functional Block Diagram] An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a screen display control device 1
Indicates. The screen display control device 1 includes an image data storage means 2
And a display control means 9. The image data storage unit 2 stores image data from a plurality of NTSC type cameras (not shown) for each image data. The image data storage means 2 is composed of an NTSC memory.
The NTSC memory is a memory that can read the stored data at a sufficient reading speed for the NTSC monitor.

In the display control means 9, the image data for each camera stored in the plurality of image data storage means (NM1 to NMK) is arranged and displayed in a plurality of divided areas of a high-definition monitor (not shown). As described above, each of the image data is output as an image display signal to the high-definition monitor at a speed required by the high-definition monitor. The details of the display control means 9 will be described. Display control means 9
Comprises a high speed storage means 5, a parallel processing means 3 and an image signal output means 7.

The high-speed storage means 5 is constructed so that the stored data can be read at the speed required by the high-definition monitor. The parallel processing means 3 is the image data storage means 2
The respective image data stored in are read in parallel and stored in the high speed storage means 5. The image signal output means 7 reads out the data stored in the high speed storage means 5 at the speed required by the high-definition monitor and outputs it.

Specifically, the high-speed storage means 5 has a line memory having a storage capacity for one line of the high-definition monitor for two lines for each RGB component. In addition, the plurality of divided areas of the high-definition monitor are configured by m rows in the vertical direction and n columns in the horizontal direction. The NTS
The C memory is composed of m × n small boards corresponding to the divided areas, and the number of lines of the input NTSC image data is m / 2 of the number of lines of one screen of the high-definition system. So that the R component, G component, and
And the digital signal for each B component is converted and stored.

Further, the parallel processing means 3 uses the image data storage means NM1 to NMK for the divided areas of n columns arranged in the same row for each of the RGB components to obtain the image data for the divided areas of n columns. Are read in parallel for n columns, and odd (ODD) pixels are stored in the first line memory, and even (EVEN) pixels are stored in the second line memory for n columns in parallel. That is, half of the first line memory stores ODD pixels and half of the second line memory stores EVEN pixels.

The image signal output means 7 stores image data for one specific line in each half area of the first line memory and the second line memory for each of the RGB components. The following processing is repeated. Next to the image data, for the image data of the next one line, ODD pixels are arranged in the remaining area of the first line memory, and EVEN pixels are arranged in the remaining area of the second line memory in parallel for n columns. To memorize. Also already 2
The image data stored in one line memory
By alternately reading the D pixel and the EVEN pixel, digital data is output at a speed required by the high-definition monitor, the output digital data is converted into analog data, and the analog data is output to the high-definition monitor.

As described above, at the time of writing, the image data for the divided regions for n columns is read in parallel for n columns,
The ODD pixels are stored in the half area of the first line memory, the EVEN pixels are stored in the half area of the second line memory for n columns in parallel, and at the time of reading, the first line memory and the first line memory are stored. The line memory of No. 2 is read alternately. As a result, even if the small board cannot be read at the speed required by the high-definition monitor,
Further, even if a line memory that can be read at half the speed required by the high-definition monitor is used, the image data for each camera can be arranged and displayed in a plurality of divided areas of the high-definition monitor.

Further, two line memories are provided for each RGB component, and writing and reading are divided into the first half and the latter half to perform writing for n columns in parallel, and reading is performed serially. Even if the operation method is different, the data can be accurately read and written.

In this way, the image data for each camera can be arranged and displayed in a plurality of divided areas of the high-definition monitor simply by providing high-speed storage means for two lines of the high-definition monitor for each RGB component. it can.

In the present embodiment, since the image data of each camera can be arranged and displayed in a plurality of divided areas of the high-definition monitor by using the NTSC type camera, a clear image can be displayed with a simple structure. Obtainable.

Further, by providing a high-speed line memory having a storage capacity for one line of the high-definition monitor for each of the RGB components, the image data from the NTSC camera is arranged in a plurality of divided areas of the high-definition monitor. Can be displayed.

[Outline of 24-division display] FIG. 2 shows image data of 24 NTSC type cameras, which is 6 horizontal × 4 vertical = 2.
An example of the hardware constitutions of the screen display control apparatus displayed on the high-definition monitor divided into four is shown.

First, the outline of the image display control device shown in FIG. 2 will be described. In this image display control device, 2
As shown in FIG. 3, the image data from the four NTSC cameras are numbered and displayed on one high-definition monitor in 24 divisions. In the present embodiment, the output to the high-definition monitor is performed by 1920 pixels horizontally × 960 lines vertically (2 fields). Therefore,
As shown in FIG. 3, when the high-definition monitor is divided into 24 parts, each small screen is composed of horizontal 320 pixels × vertical 240 lines. Since interlacing is also performed in a high-definition monitor, one field is 480 lines, and for each small screen, one field is 120 vertical.
Become a line.

As shown in FIG. 2, the present image display control device is provided with 24 small boards K1 to K2 corresponding to each channel.
In addition to 4, the high-speed line memories L1 and L2 capable of reading at the speed required by the high-definition monitor,
It has a total of 6 lines for each RGB component.

As shown in FIG. 4, the line memory L1 is
Memory for odd number (ODD) pixels, first half LF1
And the latter half LB1. Line memory L2
Is a memory for even (EVEN) pixels, and is composed of a first half LF2 and a second half LB2.

Writing and reading to and from the high-speed line memories L1 and L2 are performed as follows. First, writing will be described with reference to FIG. Set line1 of the first line of all channels on the same line to 6
Simultaneously with the channels, the first half of the line memories L1 and L2 (LF1 and LF2) are written. Ie channel 1
In parallel with writing the first to 320th pixels in the first line (see α), channels 3, 5, 5, 7, 9 and 11 arranged in the same row as channel 1 For, write the 1st to 320th pixels (see β, γ). That is, when the writing of the first line of the first channel is completed, the first line of the high-definition monitor (1920
(Pixel) writing will be completed.

It should be noted that the writing of the 320 pixels is O
Alternately write DD pixels to the first line memory L1 and EVEN pixels to the second line memory L2.

As described above, while writing to the first half LF1 and LF2, the data already written to the second half LB1 and LB2 are sequentially read and displayed on the high-definition monitor. Specifically, the ODD pixel written in the latter half LB1 of the ODD pixel line memory L1 and the latter half L of the EVEN pixel line memory L2.
The EVEN pixels written in B2 are read alternately, and the 1st to 320th pixels of the first line of the channel 1 are read. Next, in the same manner, the 1st to 320th pixels on the first line of the channel 3 are read out. Channel 5, Channel 7, Channel 9, and Channel 1
The same applies to 1 (see δ).

When this reading is completed, in the same manner as described above, the writing of the second line of the channel 1, channel 3, channel 5, channel 7, channel 9, and channel 11 is performed to the first half LF1 and LF2. To do. When the display of the channels arranged in the first row is completed by repeating the reading of the first line in parallel with the writing of the second line, that is, 120 lines which are one field. When the display of is finished, the next line (the second line, channel 2,
Writing and reading are similarly repeated for channel 4, channel 6, channel 8, channel 10, and channel 12).

In this way, the high-definition monitor 1
When the display of four columns (480 lines) which is a field is completed, the second field is similarly displayed. In this way, 960 lines corresponding to 2 fields are displayed on the high-definition monitor. As a result, the image data provided by 24 NTSC cameras can be displayed on the high-definition monitor.

Since it is necessary to apply three RGB components in parallel to the high-definition monitor, the writing and reading are performed for each of the RGB components.

Further, in this embodiment, as described above,
Writing is done in parallel and reading is done serially.
Therefore, a line memory for two lines of the first half and the second half is required for each of the RGB components. Further, the reason why the ODD pixel and the EVEN pixel are alternately written in different line memories at the time of writing is that the line memory used is only half the reading speed of the high-definition monitor. If the line memory used has a reading speed higher than that of the high-definition monitor, such alternate writing is not necessary.

[Description of Each Part] Next, each part of the image display control apparatus shown in FIG. 2 will be described. As shown in FIG. 5, each small board has an NTSC-RGB decoder 31, A / A
It has a D conversion unit 33, a field buffer 35, a SYNC separate & line lock type feed lock 37, and a field buffer write controller 39.

The NTSC-RGB decoder 31 receives the NTSC image signal as shown in FIG.
R component, G component, B component are extracted from the SC image signal,
It is given to the A / D converter 33. The A / D converter 33 converts the extracted image data for each of the R component, G component, and B component into 6.
It is sampled at 25 MHz and converted into 8-bit digital data. R component converted to digital data,
The image data of G component and B component is stored in the field buffer 35.
Memorized in. The image data of the second field of each NTSC image signal (data of lines 241 to 480) is not stored. The reason for this will be described later.

In this way, the digital data for the R, G and B components are stored in the field buffer 35 as shown in FIG. In FIG. 8, R
_The three values _inside the brackets of _(1,1,1) are
Indicates the number of channels, the number of lines, and the number of pixels. That is, R _(1,1,1) is the first channel, first line,
The first pixel is shown, and R _(1,3,320) is the 320th pixel of the third line of the first channel. The same applies to the G component and the B component.

The field buffer 35 has two areas A and B, as shown in FIG. This is because the high-definition monitor also interlaces, so that the data of the first field is stored in the area A and the data of the second field is stored in the area B.

The SYNC separate & line lock type phase lock 37 extracts a synchronizing signal (horizontal, vertical) from the input NTSC signal. The field buffer write controller 39 generates the A / D clock (6.25 MHz) shown in FIG. 6 based on the clock given from the clock 57 (see FIG. 2) and the synchronization signal,
It is given to the A / D converter 33, and the FIFO clock (25
MHz) is generated and given to the field buffer 35.
In this way, the data for each of the RGB components shown in FIG. 6 is stored in the field buffer 35.

In this way, the NTSC input data shown in FIG. 7 is stored as digital data for the R, G and B components as shown in FIG. Image data is given in parallel to each small board, and the data as shown in FIG. 8 (240 lines × 320 pixels × 3 colors)
Exists for 24 channels.

Next, the line memory LM shown in FIG. 2 will be described. The line memory LM includes a line memory RL for the R component, a line memory GL for the G component, and a line memory BL for the B component. FIG. 9 shows the line memory RL for the R component. The line memory RL is composed of a line memory RLA which is a first line memory and a line memory RLB which is a second line memory.

The line memory RLA is composed of a line buffer group RLA1 and a line buffer group RLA2, and the line buffer group RLA1 is composed of line buffers RLA1 (1) to line buffer RLA1 (6). The same applies to the line buffer RLA2. Also,
The line memory RLB is similar to the line memory RLA.

Each line buffer has a FI whose reading speed is slightly faster than half the reading speed of the HDTV monitor.
It is an FO type line buffer. In addition, its storage capacity is 1 line buffer for HDTV 1 line (19
One sixth of 20 pixels) of data (320 pixels) can be stored.

Channels arranged in the same row (see FIG.
For example, for channel 1, channel 3, channel 5, channel 7, channel 9, and channel 11, the data from the field buffer of each small board is written in parallel to the line memory LM. For example, the relationship between the writing line buffer and each channel is as follows.

CH1 (ODD pixel): RLA1 (1) CH1 (EVEN pixel): RLB1 (1) CH3 (ODD pixel): RLA1 (2) CH3 (EVEN pixel): RLB1 (2) CH5 (ODD pixel): RLA1 (3) CH5 (EVEN pixel): RLB1 (3) CH7 (ODD pixel): RLA1 (4) CH7 (EVEN pixel): RLB1 (4) CH9 (ODD pixel): RLA1 (5) CH9 (EVEN pixel): RLB1 (5) CH11 (ODD pixel): RLA1 (6) CH11 (EVEN pixel): RLB1 (6) Thus, the ODD pixels of the first line of the six channels are parallel to RLA1 (1) to RLA1 (6). )
Written on the first line of 6 channels EVEN
Pixels are written in parallel to RLB1 (1) -RLB1 (6). That is, the first lines of the six channels are written in each half area using two line memories.

FIG. 10 shows a state in which data is written in the line memory in this way. In FIG. 10, the data of FIG. 8 corresponds to the R component line buffer groups RLA1 and RLB.
1, G component line buffer groups GLA1, GLB1, B
Separated into the component line buffer groups BLA1 and BLB1,
Data for one high-definition line (1920 pixels) is stored.

For example, for the R component, R _(1,1,1) , R ₍ 1,1,3 ₎ , ..., R are stored in the line buffer group RLA1.
_(1,1,319) becomes R _(1,1,2) in the line buffer group RLB1,
_{R (1,1, 4), ····} , R (1,1,320) is stored.
The same applies to other channels in the same row. Also,
The G component and the B component are similarly stored.

In this way, for each of the RGB components,
Data for one high-definition line (1920 pixels) is divided into ODD pixels and EVEN pixels and written into two line memories. This means that each half of the 2-line memory is used.

When reading, the ODD pixel and the EVEN pixel are read alternately from the two line memories. For example, for the R component, the line buffer group RLA1 and the line buffer group RLB1 shown in FIG. 9 are read alternately. Specifically, the line buffer group R shown in FIG.
LA1 of R _(1,1,1), R ₍₁ line buffer group _{RLB1,
1, 2),} R _(1,1,3 line buffer group _RLA1), R _(1,1,4 line buffer group RLB1), ····, of the line buffer group RLB1 and R _(1,1,320) Read sequentially. Thus, R _(1,11,320) of the line buffer group RLB1
Read up to. Digital data read is 3ch
Is converted into analog data by the D / A converter 29 (see FIG. 2) and output to the high-definition monitor.

Further, in the present embodiment, in parallel with the reading of one line, the writing of the next one line is performed in the other half of the two line memories. For example, if the first line is being read, the second line is written in parallel with it. That is, in parallel with reading from the line buffer group RLA1 and the line buffer group RLB1 shown in FIG.
Line buffer group RLA2 and line buffer group RL
Writing to B2 is performed. The writing method is the same as the case of writing to the line buffer group RLA1 and the line buffer group RLB1, and the description thereof will be omitted.

When the lines of one field (120 lines) of the channels arranged in the first row are processed by repeating the above processing, the channels arranged in the second row (channels 2, 4, 6, 8). , 10, 12) are similarly processed. By performing such processing up to the fourth line, the display for one field is completed.

As described above, in this embodiment, the image data is output at the speed required by the high-definition monitor by using the field buffer of each child board for NTSC which cannot read at the reading speed required by the high-definition monitor. can do.

Next, the write controller (LWCONT) 21 shown in FIG. 2 will be described with reference to FIG. The write controller (LWCONT) 21 includes a line buffer write controller 55, a field buffer read controller 51, a line lock type phase lock 53, and an oscillator 57. Oscillator 57 to 3
When the clock of 3 MHz is given, the line lock type phase lock 53 operates as a read controller (LRCON).
T) 25 (see FIG. 2) outputs the clock CK1 synchronized with the high-definition synchronizing signal. Where 3
The high-definition HSYNC is designed to give the clock CK1 of 3 MHz for 29.6 μs and 29.
1920 pixels (1 line) x (1 /
This is because 6) × (3) = 960 pixels can be read out.

The above "1/6" is set because six small screens are written in parallel in each line buffer, and the above "x3" is set in RGB of serial data. This is because it is necessary to write the three components in parallel to the line memory.

The clock is supplied to the field buffer read controller 51. The field buffer read controller 51 supplies the clock to the 24-channel field buffer, and further determines which row of 6 channels corresponding to the small screen arranged in the same row is selected. The switching signal CHm is output to the multiplexer 41. Further, the field buffer read controller 51 gives a read signal RE to the field buffers of channels 1 to 24.

The line buffer write controller 55 is supplied with the clock CK1 from the line lock type phase lock 53, and further, the read controller 25.
A high-definition synchronizing signal is given from (see FIG. 2).
The line buffer write controller 55 outputs the write signal WE. The write signal WE has a write signal RWE for the R component, a write signal RWE (E) for the EVEN pixel, and a write signal R for the ODD pixel.
WE (O). The same applies to the G component and the B component. In addition, the line buffer write controller 55
The switching signal CHG1 is output to the switching unit 54 that switches whether to use the first half or the second half of the line memory.

Next, the operation of writing the image data in the field buffer into the line memory will be described with reference to FIGS. In FIG. 11, the line buffer groups RLA1 and RLA2 are shown separately for the sake of explanation.

The description of writing will be made on the case where the R component data of the first channel field buffer 35K1 among the RGB components is written into the R component line memory RLA and line memory RLB.

Field buffer read controller 5
1 indicates the high-definition sync signal HS as shown in FIG.
The read signal RE is applied to the field buffer 35K1 of the channel 1 in accordance with YNC. The read signal RE can be read at the LOW level.

When the clock CK1 is applied, the field buffer 35K1 outputs the DATA signal to the multiplexer 41 at that timing. Further, the field buffer read controller 51 uses the switching signal CHm.
Is output. As a result, the multiplexer 41 outputs the channel 1 data to the demultiplexers 431 and 432.

The demultiplexers 431 and 432 take out only the R component from the supplied data and output it to the demultiplexers 45R1 and 45R2. Demultiplexer 4
The 5R1 and 45R2 distribute the supplied data for ODD pixels and EVEN pixels and output the data to the line buffer groups RLA1, RLA2, RLB1 and RLB2.

Line buffer write controller 55
Is based on the clock CK1, and as shown in FIG. 12, a write signal RWE for R component ODD pixels.
(O) Write signal GWE for G component ODD pixel
(O), B component ODD pixel write signal BWE
(O), R component EVEN pixel write signal RWE
(E), G component write signal GWE for EVEN pixel
(E), B component write signal RWE for EVEN pixel
(E) is sequentially output.

The switching unit 54 receives the switching signal CHG1 at L level.
If it is at the OW level, the write signal E is given to the first half (line buffer group RLA1 and line buffer group RLB1) of the line memory, and if it is at HIGH level, the write signal E is sent to the latter half of the line memory (line buffer group RL
A2 and line buffer group RLB2).

When this write signal E is given, data is written at the timing of the clock CK1. In this way, the data in the field buffer 35K1 is transferred to the line buffer group RLA1 and the line buffer group RL.
Written to B1. Note that such writing is simultaneously performed on the other five channels arranged in the same row as the channel 1 as described above.

When the next synchronizing signal HSYNC is given (when one line is completed), the switching signal CHG1 is
Switch from LOW level to HIGH level. As a result, the switching unit 54 supplies the write signal WRE, which has been given to the first half (line buffer group RLA1 and line buffer group RLB1) of the line memory, to the latter half of the line memory (line buffer group RLA2 and line buffer group RLA).
LB2).

Field buffer read controller 5
1 from the read controller 25 shown in FIG.
When the ONT switching signal is received, the multiplexer 41
The switching signal CHm is output to. As a result, the data of the channels arranged in the second row is given to the line memory from the channels arranged in the first row.

FIG. 16 shows a timing chart of switching every 120 lines as described above. In this way, the data of the channels arranged in all the rows (1Y to 4Y) can be read.

Next, the small board data processing unit 231 (see FIG.
Refer to). Small board data processing unit 231
Connects the line memory with the corresponding four field buffers. FIG. 13 shows a block diagram of the small board data processing unit 231. The small board data processing unit 231 is 4 to 1
Multiplexer 41, 1 to 3 multiplexer 43A,
1 to 2 demultiplexers 45R, 45G, and 45
It has B.

The 4to1 multiplexer 41 switches the 8-bit data to be output from the first row to the fourth row each time the switching signal CHm is applied. Since this 8-bit data is given in RGB time series, 1 to 3
The demultiplexer 431 divides into RGB components. Furthermore, 1to2 demultiplexers 45R1, 45
G1 and 45B1 store 8-bit data for each of the RGB components in line memories RLA, GLA, for ODD pixels.
Line memories RLB, G for BLA and EVEN pixels
It is given by dividing into LB and BLB.

In this embodiment, the small substrate processing section has a total of 6 rows as shown in FIG.

Next, the read controller (LRCONT) 25 shown in FIG. 2 will be described with reference to FIG. The read controller 25 includes a line buffer read controller 73, a high-definition sync signal generator 77,
DAC-related control signal generator 75, LWCONT
A switching signal generator 71 and an oscillator 78 are provided.

When a clock of 74.25 MHz is given from the oscillator 78, a high-definition sync signal generator 77
Outputs a high-definition sync signal (horizontal / vertical).
The DAC-related control signal generator 75 outputs this HDTV synchronization signal to the DAC 29 (see FIG. 2), and D
The AC 29 performs D / A conversion based on the supplied high-definition sync signal. The LWCONT switching signal generator 71 outputs the LWCONT switching signal when receiving the horizontal synchronization signal HSYNC by the number of lines of the channels arranged in the same row (120 lines per field).

Line buffer read controller 73
Outputs the 74.25 MHz clock signal CK2 to the line memory. In addition, the line buffer read signal L
Outputs RE1 to LRE6. The line buffer read controller 73 outputs a switching signal CHG2 to a switching unit 76 that switches between using the first half of the line memory and the second half of the line memory.

Next, the read operation from the line memory will be described with reference to FIGS. 14 and 15. In FIG. 14, line buffers RLA1 (1) to RLA for R components are used.
This will be described using LA1 (6) and RLB1 (1) to RLB1 (6). The capacity of the line buffer groups RLA1 and RLB1 is one high-definition line (1920 pixels).

Line buffer read controller 73
Outputs a clock signal CK2 and line buffer read signals LRE1 to LRE6, as shown in FIG. Since the line buffer read signals LRE1 to LRE6 can be read at the LOW level, in the case shown in the figure, 1X to 6 are sequentially output at the timing of the clock CK2.
Read up to X.

Specifically, R _{(1,1,1) of} the line buffer RLA1 (1) and the line buffer RLB1 (1) shown in FIG.
R _{(1,1,2) of} the line buffer RLA1, (1) R _{(1,1,3) of} the line buffer RLB1 (1) of R _(1,1,4) ,
..., Read sequentially with R _{(1,1,320) of} the line buffer RLB1 (1). Next, as shown in FIG. 15, since the read signal LRE2 becomes LOW level, R _{(3,1,1) of} the line buffer RLA1 (2 ₎ and the line buffer RLB1
(2) R ₍ 3,1,2 ₎ , ..., Line buffer RLB1
_Read R _(3,1,320) in (2). Repeat this one by one,
_Read up to R _(1,11,320) .

The switching signal CHG2 output from the line buffer read controller 73 is opposite to the switching signal CHG1 as shown in FIG. As a result, when data is being written to the line buffer groups RLA1 and RLB1, reading is performed from the line buffer groups RLA2 and RLB2, and the line buffer group R
When writing to LA2 and RLB2,
Reading is performed from the line buffer groups RLA1 and RLB1.

Next, the line buffer data processing unit 27 shown in FIG. 2 will be described with reference to FIG. The line buffer data processing unit 27 uses the 6to1 multiplexer 61, 2t.
It includes an o1 multiplexer 63R, 63G, and 63B.

The 6to1 multiplexer 41 has the configuration shown in FIG.
The data shown in is sequentially displayed from the first column (1X) to the sixth column.
Data is given while switching to the column (6X).
At that time, an ODD pixel and an EV for each component of RGB
Both data of EN pixel are read at the same time,
2to1 multiplexer 63R, 63G, 63B is OD
The data of the D pixel and the EVEN pixel are alternately switched and output.

[Other Application Examples] In the present embodiment, the image memory from 24 NTSC cameras is temporarily stored in order to display it on a 24-division high-definition monitor using the conventional NTSC memory. After writing to the high-speed line memory, the data is read so as to match the reading speed of the high-definition monitor. But,
Without being limited to such a configuration, as shown in FIG. 18, high-speed image memories matching the readout speed of the HDTV monitor may be used for the number of NTSC cameras. In this example, the display control means 9 only needs to switch the image data storage means 81a to 81n, and the line memory is not required.

In this embodiment, the data of 2 fields of NTSC image data is not used. This is about 2 of the high definition system is the NTSC system.
It has 4/2 = 2 because it has double scanning lines and is vertically divided into four in the above embodiment. That is, vertical m
In order to display the image data of the NTSC system in the line division area, the small board thins out the data so that the number of lines of each small screen is m / 2 of the number of lines of one screen of the high definition system. Good. Therefore, the number of divisions in the vertical direction can be adjusted by adjusting the number of lines to be thinned out. For example, if it is divided into eight, it is only necessary to thin out four lines from the NTSC image data into one line. For example, you can thin out 3 lines into 1 line. At this time, the image display can be made smooth by performing data interpolation.

In this embodiment, 24 NTs are used.
The image data from the SC camera is displayed on a 6 × 4, 24-division high-definition monitor, but the number of divisions in the horizontal direction is based on the NTSC image data signal
It can be changed by changing the number of samplings at the time of D / D conversion.

As described above, not only 24 divisions but also 16 divisions or 48 divisions are possible.

In this embodiment, the case where the image data from the memory for the NTSC camera whose image data read speed is slow is displayed on the high-definition monitor whose reading speed is fast has been described. It can be applied to the case where image data stored in a slow memory is output to a display device having a high read speed.

[0093]

According to the screen display control device of the first aspect, the image data storage means stores the image data from a plurality of NTSC type cameras for each image data.
The display control means uses the image data as image display signals so that the image data for each camera stored in the image data storage means is displayed in a plurality of divided areas of the high-definition monitor. Output to the high-definition monitor at the speed required by the monitor.
Thereby, the image data of each camera is arranged and displayed in the plurality of divided areas of the high-definition monitor. Therefore, in the screen display control device according to claim 2, which can provide a screen display control device capable of obtaining a clear image with a simple structure, the parallel processing means is stored in the image data storage means. Each image data is read in parallel and stored in the high-speed storage means. Therefore, even if the reading speed of each image data stored in the image data storage means is slower than the reading speed of the high-definition monitor, the image data of each camera is arranged and displayed in a plurality of divided areas of the high-definition monitor. be able to. Accordingly, it is possible to provide a screen display control device that can obtain a clear image with a simpler structure.

In the screen display control device of claim 3,
The writing and reading of data are performed alternately in the first line memory and the second line memory, and the parallel processing means writes the read image data for each block in the first half of the two line memories. , Are stored in parallel, the image signal output means reads out serially for each block in the latter half of the two line memories. On the other hand, when the parallel processing means stores the read image data in parallel in each of the blocks in the latter half of the two line memories, the image signal output means controls The blocks in the first half of the line memory are serially read.

Therefore, even if the reading speed of the line memory is half of the reading speed required by the high-definition monitor, the image data of each camera can be arranged and displayed in a plurality of divided areas of the high-definition monitor. it can. Further, since reading and writing are separately performed in the first half and the latter half, data can be read and written accurately even if the reading and writing methods are different. Accordingly, it is possible to provide a screen display control device that can obtain a clear image with a simpler structure.

In the screen display control device of claim 4,
The NTSC memory thins out the input NTSC image data so that the number of lines becomes m / 2 of the number of lines in one screen of the high-definition system. This makes it possible to properly display the NTSC image data in the vertical m-row divided area.

Further, the parallel processing means parallelizes the image data for the divided regions of the n columns from the small substrates for the divided regions of the n columns arranged in the same row for each of the RGB components. The odd pixels are stored in the first line memory in parallel and the even pixels are stored in the second line memory for n columns in parallel. The image signal output means, for each of the RGB components, the first line memory and the second line memory.
When the specific one line of image data is stored in the line memory of, the following process is repeated. Subsequent to the image data, with respect to the image data of the next one line, odd-numbered pixels
Of the image data stored in the two line memories alternately by storing the image data in the line memory in parallel for n columns to output the digital data at a speed required by the high-definition monitor, and output the digital data. Is converted into analog data and output to the high-definition monitor.

As described above, at the time of writing, the image data for the divided regions for the n columns is read in parallel for n columns,
By storing odd-numbered pixels in the first line memory in parallel with the even-numbered pixels in the second line memory by n columns and reading the first line memory and the second line memory alternately during reading. , Even if the small substrate cannot be read at the speed required by the high-definition monitor, and by using the line memory that can be read at half the speed required by the high-definition monitor, the image data of each camera can be read by a plurality of the high-definition monitor. It can be arranged and displayed in the divided areas. That is, it is possible to provide a screen display control device capable of obtaining a clear image with a simpler structure.

In the screen display control device of claim 5,
The parallel processing means reads the respective image data stored in the image data storage means in parallel and stores them in the high speed storage means. The high-speed storage means has a storage capacity of at least one line of image data of the display means. The image signal output means reads out and outputs the data stored in the high speed storage means at a speed required by the display means. Thereby, the image data of each camera is arranged and displayed in the plurality of divided areas of the high-definition monitor. That is, it is possible to provide a screen display control device capable of obtaining a clear image with a simpler structure.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an image display control device 1 according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a hardware configuration of an image display device 1.

FIG. 3 is a diagram showing an input channel number layout when a screen of a high-definition monitor is divided into 24 parts.

FIG. 4 is a diagram for explaining writing to and reading from a line memory.

FIG. 5 is a configuration diagram of a small board K1.

FIG. 6 is a diagram showing a timing chart of data conversion in the A / D conversion unit 33.

FIG. 7: Input NTSC data (analog data)
FIG.

8 is a diagram showing digital data stored in a field buffer 35. FIG.

FIG. 9 is a diagram showing a line memory RL for R component.

FIG. 10 is a diagram showing a state in which data is written in a line memory.

FIG. 11 is a diagram for explaining a write operation to a line memory.

FIG. 12 is a timing chart of a write operation to a line memory.

FIG. 13 is a configuration diagram of a small board data processing unit 231.

FIG. 14 is a diagram for explaining a read operation from a line memory.

FIG. 15 is a timing chart of a read operation from the line memory.

FIG. 16 is a timing chart of switching every 120 lines.

FIG. 17 is a diagram showing a configuration of a line buffer data processing unit.

FIG. 18 is a functional block diagram of an image display control device according to another embodiment.

FIG. 19 is an overall configuration diagram of a conventional monitoring system 101.

[Explanation of symbols]

 3 ... Parallel processing means 5 ... High-speed storage means 7 ... Image signal output means K1 to K24 ... Small substrate LM ... ... Line memory

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/00 S 9471-5G 5/14 A 9471-5G 5/36 520 L 9471-5G 530 E 9471-5G F 9471-5G H04N 5/93 7/015 7/18 U

Claims (5)

[Claims] 1. An image data storage means for storing image data from a plurality of NTSC type cameras for each image data, wherein the image data for each camera stored in the image data storage means is stored in a plurality of HDTV monitors. Display control means for outputting the image data as image display signals to the high-definition monitor at a speed required by the high-definition monitor so as to be arranged and displayed in the divided areas. Control device. 2. The screen display control device according to claim 1, wherein the image data storage means stores the stored data in NTS.
The display control means is a high-speed storage means capable of reading the stored data at the speed required by the high-definition monitor, and is stored in the image data storage means. Each image data,
Parallel processing means for reading in parallel and storing in the high-speed storage means, and image signal output means for reading and outputting the data stored in the high-speed storage means at a speed required by the high-definition monitor, Screen display control device. 3. The screen display control device according to claim 2, wherein: 1) the high-speed storage means is a line memory including a first half part composed of a plurality of blocks and a second half part composed of a plurality of blocks, A line memory having a storage capacity for one line of the high-definition monitor is set to RGB
Of the two line memories, the first line memory is for odd pixels, and the other line memory is the second line memory for even pixels. 2) The writing and reading of data are alternately performed in the first line memory and the second line memory, and 3) the parallel processing means performs the above-mentioned operation for each block in the first half of the two line memories. When the read image data is stored in parallel, the image signal output means reads serially to each block of the latter half of the two line memories, 4) the parallel processing means, When the read image data is stored in parallel in each of the blocks in the latter half of the two line memories, the image signal output means is arranged in the first half of the two line memories. Screen display control unit and performs reading in series, to each component of RGB for each block of. 4. The screen display control device according to claim 3, wherein 1) the plurality of divided areas of the high-definition monitor have a length of m.
The rows and the columns are arranged in n columns. 2) The NTSC memory has m ×
The input NTSC consists of n small boards.
The image data of the system is thinned out so that the number of lines becomes m / 2 of the number of lines of one screen of the high-definition system, and the thinned data is digital for each of the R component, G component, and B component. 3) The parallel processing means, for each of the RGB components, the parallel processing means outputs image data for the divided regions of the n columns from the small substrate for the divided regions of the n columns arranged in the same row. n columns are read in parallel, odd pixels are stored in the first line memory in parallel, and even pixels are stored in the second line memory in n columns in parallel, and 4) the image signal output means is for each RGB component. When the specific one line of image data is stored in the first line memory and the second line memory, the following processes 41) and 42) are repeated, 41) continuing the image data. hand , For the next one line of image data, odd pixels are stored in the first line memory in parallel for even columns in the second line memory for n columns, 42) the image stored in two line memories By alternately reading the data, the digital data is output at the speed required by the high-definition monitor, the output digital data is converted into analog data, and the analog data is output to the high-definition monitor. apparatus. 5. A screen display control device for displaying a plurality of image data by arranging and displaying the plurality of image data in each area of the display means, wherein the image data storage means stores the plurality of image data for each image data. A high-speed storage unit having at least one line of image data storage capacity of the display unit and capable of being read at a speed required by the display unit, each image data stored in the image data storage unit,
Parallel processing means for reading in parallel and storing in the high-speed storage means, image signal output means for reading and outputting the data stored in the high-speed storage means at a speed required by the display means, Screen display control device.