JPH07154686A - Picture processing unit - Google Patents

Abstract

PURPOSE:To fade a binary picture and other pictures by forming a control signal from a binary picture signal stored in a digital memory and controlling a level of the binary picture signals and the other picture signals based on the control signal. CONSTITUTION:An output digital signal of a multiplier circuit 10 to a GCA(gain control amplifier) all side is converted into an analog signal by a D/A converter circuit 12 and fed to the GCAa 11, in which a level of the binary signal from a digital memory 6 is controlled based on the output signal. On the other hand, a digital signal outputted from a multiplier circuit 10a toward a GCAb 15 is given to a complement circuit 13, where a complement number is taken and the result is converted into an analog signal by a D/A converter 14, and outputted to the GCAb 15. The GCAb 15 controls a level of a picture signal from the image pickup part 1 based on the output signal from the D/A converter circuit 15. Then output signals from the D/A converter circuit 17 and the GCAb 15 are added by an adder circuit 17 and the binary signal outputted from the digital memory 6 is synthesized with a picture signal from the image pickup part 1 and the result is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device having a digital memory.

[0002]

2. Description of the Related Art Conventionally, as this type of device, an image processing device having a digital memory for binarizing and recording an image signal taken in by an imaging means is known, but is read from the imaging device. A device capable of synthesizing a binary image from a digital memory with a multivalued image is considered.

Further, as this kind of image processing apparatus, an image processing apparatus capable of operating a fade function in which a rear scene is gradually superimposed on a front scene when a screen is changed is considered.

Further, in the case of the image processing apparatus having the above-mentioned fade function, a multi-valued image taken from the image pickup section is recorded in a memory, and the multi-valued image is read out from the memory in synchronization with a video signal from the image pickup section. After controlling the levels of the image signal and the video signal from the image pickup unit respectively, the two are added to realize a normal image fade.

[0005]

However, as described above, in the image processing apparatus having the digital memory,
When a binary image signal stored in a digital memory is combined with a video signal, it is simply combined with the video signal, and no binary image fades in / out in the combined state.

In consideration of the above-mentioned problems, the present invention forms a control signal from a binary image signal stored in a digital memory and combines the binary image signal read from the digital memory with another image signal. It is an object of the present invention to provide an image processing device capable of fading in and fading out.

[0007]

SUMMARY OF THE INVENTION In order to solve the problems conventionally held and to achieve the above object, the present invention is an image processing apparatus equipped with a digital memory capable of storing a binarized image signal. 2 read from the digital memory
Means for generating a first signal for changing the composition ratio of the value image signal and the other image signal, and a control signal by calculating the second signal and the first signal according to the binary image signal And a synthesizing means for synthesizing the binary image signal and the other image signal according to the control signal.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an image processing apparatus which is a first embodiment of the present invention.

In FIG. 1, an image signal obtained by an image pickup unit 1 such as a CCD is binarized by a binarizing circuit 5 into, for example, two types of white and black to become a binary signal. Note that here, the binarized image signal is, for example, 1 if white.
If it is black, it is set to 0. The binarized signal is stored in the digital memory 6, and the writing / reading thereof is controlled by the memory control circuit 4 as described later.

The image signal from the image pickup section 1 is also sent to the sync separation circuit 2, where the horizontal and vertical sync signals in the image signal are extracted and output to the timing circuit 3. The timing circuit 3 generates a timing signal for memory control based on these synchronization signals and outputs it to the memory control circuit 4. The memory control circuit 4 writes the above-mentioned binarized signal in the digital memory 6 according to the signal from the digital memory operation switch 7.

The fade switch 8 is operated when performing an image fade, and the fade signal generation circuit 9 generates a fade signal based on the signal from the fade switch 8 as described later and outputs it to the multiplication circuit 10. The multiplication circuit 10 multiplies the binary signal read from the digital memory 6 by a predetermined value, and outputs it to the D / A conversion circuit 12 and the complement circuit 13. The complement circuit 13 takes the complement of the input signal and outputs it to the D / A conversion circuit 14. The GCAs 11 and 15 are gain control amplifiers, which control the levels of the output signals from the digital memory 6 and the image pickup unit 1 based on the output signals from the D / A conversion circuits 12 and 14, respectively. The output signal from the GCAa 11 is converted into an analog signal by the D / A conversion circuit 16, added with the output signal from the GCAb 15 by the adder circuit 17, and output from the output terminal 18.

The binary signal stored in the digital memory 6 as described above is read by the memory control circuit 4 after the storage of the binary signal from the binarization circuit 5 is completed, and is always read thereafter. . Further, since writing / reading of the binary signal is performed based on the timing signal from the timing circuit 3, the binary signal is synchronized with the image signal from the image pickup unit 1.

The operation for fading the image signal in such a configuration will be described.

While the button 8a of the fade switch 8 is being pressed, the signal a shown in FIG. 2 (a) is output from the fade switch 8. The signal a is sent to the fade signal generation circuit 9, where an n-bit digital signal b having the value shown in FIG. 2B is generated. 2 (c) is shown in FIG.
A part of (b) is enlarged and shown in a period H in FIG. 2 (c) is a signal corresponding to one field period of the image signal.

The binary signal read from the digital memory 6 and the signal b from the fade signal generation circuit 9 are output to the multiplication circuit 10. The multiplication circuit 10 multiplies the binary signal by the signal b. Here, since the binary signal is 1 or 0, and the signal b is an n-bit digital signal, the output signal of the multiplication circuit 10 is an n-bit digital signal. The state of the output digital signal of the multiplication circuit 10 is shown in FIG.

This output digital signal is output to the D / A conversion circuit 12 and the complement circuit 13, and based on this digital signal, an image signal obtained from the image pickup section 1 and a binary signal output from the digital memory 6. Control the level of each. The digital signal output from the multiplication circuit 10 to the GCAa11 side is converted into an analog signal by the D / A conversion circuit 12 and sent to the GCAa11. The output signal of the D / A conversion circuit 12 is shown in FIG. The GCAa 11 controls the level of the binary signal from the digital memory 6 based on this output signal. The binary signal after level control is converted into an analog signal by the D / A conversion circuit 16 and output to the addition circuit 17.

On the other hand, the digital signal output from the multiplication circuit 10 to the GCAb 15 side is complemented by the complement circuit 13 and then converted into an analog signal by the D / A converter 14 to obtain the GCAb.
It is output to 15. The output signal of the D / A conversion circuit 14 is shown in FIG. In GCAb15, the D / A conversion circuit 1
The level of the image signal from the image pickup unit 1 is controlled based on the output signal of No. 4. Then, the D / A conversion circuit 16 and the GC
The output signal of Ab15 is added by the adder circuit 17, and the binary signal output from the digital memory 6 is output in a state of being combined with the image signal from the imaging unit 1. With such a configuration, even if the button 8a of the fade function switch 8 is pressed when there is no binary signal in the digital memory 6, the image signal from the imaging unit 1 is output as it is.

Since the digital signal b is output while the button 8a of the fade switch 8 is being pressed, the binary image is automatically faded out when the button 8a is stopped. In the case of this fade-out, the operation itself of the device is the same as that in the case of fade-in. Here, the fade-in / fade-out time is the period T in FIG. 2B. The time during which the images are combined can be adjusted by the time during which the button 8a of the fade function switch 8 is pressed.

As described above, in the present embodiment, the binary signal can be faded in a state where the binary image recorded in the digital memory and the image captured by the image capturing section are combined. is there.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram of an image processing apparatus according to a second embodiment of the present invention. Members having the same or similar functions as in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be given. Is omitted.

In FIG. 3, reference numeral 19 is a color designating circuit, which is a circuit for designating a color when synthesizing the binary signals from the digital memory 6, and the fade control circuit 22 is
This is a circuit that specifies the operation of image fade. Control circuit 2
0 controls the memory signal processing circuit 21 and the GCAa11 and GCAb15 based on the output signals from the color designating circuit 19 and the fade control circuit 22 to perform various fade functions as described later. Further, the signal processing circuit 23 performs predetermined signal processing on the output image signal from the imaging unit 1 to convert it into an RGB signal and outputs it to the GCAb 15.

The binary signal stored in the digital memory 6 as described above is read by the memory control circuit 4 and output to the memory signal processing circuit 21. The memory signal processing circuit 21 converts the binary signal into an analog signal on the basis of the output signal from the control circuit 20 which has received the signal from the color designating circuit 19 and performs signal processing to obtain the signal of the designated color. Output to GCAa11 in the form of RGB.

The image signal processing apparatus of this embodiment has a plurality of fade functions in addition to the normal binary signal fade as described above. Hereinafter, these fade functions will be described.

First, the fade of the normal binary signal as described above will be described.

In this case, the fade control circuit 2
When the 2 button 22a is pressed, a signal indicating a normal fade is output to the control circuit 20. The control circuit 20 outputs the signal c shown in FIG. 4A to the GCAa 11 based on this signal. The GCAa 11 controls the level of the output signal from the memory signal control circuit 21 based on this signal c and outputs it to the synthesizing circuit 24. Further, the control circuit 20 outputs the signal d shown in FIG. 4B to the GCAb 15, and the GCAb 15 controls the level of the output signal from the signal processing circuit 23 based on this signal d and outputs it to the synthesizing circuit 24. Synthesis circuit 2
Reference numeral 4 synthesizes the output signals from the GCAa11 and GCAb15 and outputs the synthesized signal to the output terminal 18. In this way, by operating the button 22a of the fade control circuit 22, it is possible to perform normal binary signal fade.
Further, if the color is designated by the color designating circuit 19, they are combined. 2
It is also possible to add a desired color to the value signal.

Next, a horizontal fade in which a binary image gradually emerges in the horizontal direction will be described.

In this case, the fade control circuit 2
When the 2 button 22b is pressed, a signal indicating a horizontal fade is output to the control circuit 20. The control circuit 20 outputs the signal e shown in FIG. 5 to the GCAa 11 based on this signal and the horizontal synchronizing signal from the synchronizing separation circuit 2.

Here, the signal e will be described. FIG. 5 shows how the signal e output from the control circuit 20 changes with time for one line for each predetermined field.
That is, assuming that the signal e for every 10 fields is shown in FIGS. 5A to 5D, the level of the output signal from the memory signal processing circuit 21 is set for each line in the first 10 fields after the button 22b is pressed. It is changed as shown in FIG. In FIG. 5A, the level is lower on the left side of one screen, and the level is higher toward the right side. Then, as shown in FIG.
As shown in (b) to (d), the signal level is changed for each line. The GCAa 11 changes the level of the output signal from the memory signal processing circuit 21 in this way and outputs it to the synthesizing circuit 24.

The control signal of the GCAb15 is the same as the signal d described above. In this way, by operating the button 22b of the fade control circuit 22, the horizontal fade can be performed.

Next, a vertical fade in which a binary image gradually emerges in the vertical direction will be described.

In this case, the fade control circuit 2
When the 2 button 22c is pressed, a signal indicating a vertical fade is output to the control circuit 20. Based on this signal and the vertical sync signal from the sync separation circuit 2, the control circuit 20 performs GCA.
The signal f shown in FIG. 6 is output to a11.

Here, the signal f will be described. FIG. 6 shows how the signal f output from the control circuit 20 changes with time for one field for each predetermined field. That is, in FIG. 6A, the level of the signal of the upper line in the screen for one field is low, and the level increases toward the lower part. Here, FIG.
Assuming that (d) shows the signal f for every 10 fields,
The first 10 fields are changed as described above, and the signal level of each field is changed every 10 fields as shown in FIGS. 6 (b) to 6 (d). The GCAa 11 changes the level of the output signal from the memory signal processing circuit 21 in this way and outputs it to the synthesizing circuit 24.

The control signal of the GCAb 15 is the same as that of the signal d described above. By operating the button 22c of the fade control circuit 22 in this way, vertical fade can be performed.

Further, in the above-described embodiment, only the horizontal fade / vertical fade is performed, but the control circuit 20 causes the signal e
It is also possible to perform the diagonal fading by controlling the AGCa 11 by combining the signal and the signal f. Further, as an application of this oblique fade, effects such as which part on the screen the binary image is faded in to, and which part of the screen the image is left to the end to be combined can be considered.

The designation of these fade start positions can be designated by operating the operating section 22d of the fade control circuit 22. Considering the case where the binary image is faded in, the operator operates the operation unit 22d to specify the portion where the binary image is faded in by moving a cursor (not shown) on the screen. When the control circuit 20 receives the signal in which the fade start portion is designated, the GCAa11 is controlled in the same manner as in the case of the vertical fade and the horizontal fade as described above so that the binary image emerges from the designated portion. The level of the binary image signal output from the memory signal processing circuit 21 is controlled. And
By synthesizing the level-controlled binary signal in the synthesizing circuit 24, it is possible to obtain an image signal in which the binary image is faded from the designated portion.

Further, 2 is applied to each of the above-mentioned vertical fade, horizontal fade, diagonal fade and partial designation fade.
It is possible to color the value image.

As described above, in this embodiment, it is possible to realize a special fade function such as horizontal fade / vertical fade in addition to the normal fade of a binary image. It is also possible to color the binary image to be combined.

Next, a case where the present invention is applied to a digital VTR will be described.

FIG. 7 is a block diagram showing the configuration of the main part of a digital VTR for recording / reproducing an image signal in the form of a digital signal.

In FIG. 7, reference numeral 1 is an image pickup section similar to that of the above-described embodiment, and 25 is a fade section having substantially the same configuration as that of FIG. The output signal from the fade unit 25 is converted into a digital signal of, for example, about 8 bits by the A / D conversion circuit 26, and the information amount is compressed by the compression unit 27. In the compression unit 27, the DCT circuit 27a divides the digital signal from the A / D conversion circuit 26 into blocks for each predetermined number of pixels (here, 64 pixels of 8 pixels × 8 pixels) (hereinafter referred to as D
CT block), known DCT (Discrete Cosine Tran)
sformation: Discrete cosine transform) is applied to transform the signal from the pixel domain to a signal in the frequency domain. The digital signal subjected to DCT is VLC (Variable Length Coding)
Variable length coding is performed by the circuit 27b. VLC circuit 27b
The digital signal encoded by is output from the output terminal 30 to a signal processing unit (not shown) in the subsequent stage.

The signal representing the frequency component of each DCT block from the DCT circuit 27a is the motion detection (M
It is also output to the D: Motion Detect) circuit 28. The motion detection circuit 28 determines whether there is a motion in the DCT block or not based on the input signal level of the high frequency region of each DCT block, and outputs the determination result to the fade control circuit 29. Fade control circuit 29
Uses the operation unit 29a to specify various fade functions as described above and a motion adaptive fade as will be described later, and performs a fade operation.

The motion adaptive fade in this embodiment having the above structure will be described below. It should be noted that in the motion adaptive fade of the present embodiment, it is assumed that the image that is the background of the fade is faded so that a moving portion remains until the end. This is because a moving part is likely to be an important part in the captured image.

When a motion adaptive fade is designated by the operation unit 29a of the fade control circuit 29, the fade control circuit 29 selects a DCT block with a motion in the background image of the binary image synthesized by the fade unit 25. It is detected based on the motion determination result from the motion detection circuit 28. Then, by designating a moving part as a part to be left to the end, the control is the reverse of the above-described part designation fade, that is, a binary image is synthesized so as to synthesize a binary image from the part farthest from the moving part. Control the level of and fade.

In this way, by detecting a moving part on the background screen based on the judgment result of the motion detecting circuit,
It is possible to perform a motion adaptive fade that leaves a moving part at the end.

[0047]

As described above, according to the present invention, a control signal is formed from a binary image signal stored in a digital memory, and a binary image signal and another image signal are generated based on this control signal. By controlling the level, it is possible to fade the binary image and another image.

Further, by finely controlling the level of the binary image signal from the digital memory, it is possible to perform various fades such as horizontal fade and vertical fade.

Further, by designating a portion where the binary image is faded in and out, and controlling the level of the binary image so that the designated portion or the designated portion is finally synthesized, the various fades can be performed. In addition, a partial designation fade can be performed.

Further, according to the present invention, it is possible to perform a motion adaptive fade in which a moving portion is detected in an image which becomes a background of a fade and a binary image is combined so that the portion remains until the end.

[Brief description of drawings]

FIG. 1 is a diagram showing an image processing apparatus as a first embodiment of the present invention.

FIG. 2 is a diagram showing a level control signal of each image signal in the first embodiment.

FIG. 3 is a diagram showing an image processing apparatus as a second embodiment of the present invention.

FIG. 4 is a diagram showing a level control signal of each image signal in the second embodiment.

FIG. 5 is a diagram showing a level control signal of a binary image signal in the second embodiment.

FIG. 6 is a diagram showing a level control signal of a binary image signal in the second embodiment.

FIG. 7 is a digital VTR as a third embodiment of the present invention.
3 is a block diagram showing the configuration of the main part of FIG.

[Explanation of symbols]

 2 sync separation circuit 4 memory control circuit 5 binarization circuit 6 digital memory 7 digital memory operation switch 8 fade switch 11 gain control amplifier 15 gain control amplifier 20 control circuit 21 memory signal processing circuit 22 fade control circuit

Claims (5)

[Claims] 1. An image processing apparatus comprising a digital memory capable of storing a binarized image signal, for changing a synthesis ratio of a binary image signal read from the digital memory and another image signal. Means for generating a first signal, means for forming a control signal by calculating a second signal according to the binary image signal and the first signal, and the means for generating the control signal according to the control signal. An image processing apparatus comprising: a synthesizing unit for synthesizing a value image signal and the other image signal. 2. The image processing apparatus according to claim 1, wherein the first signal is a gradually increasing or gradually decreasing signal for giving an image fade function. 3. An image processing apparatus having a digital memory capable of storing a binarized image signal, for changing a synthesis ratio of a binary image signal read from the digital memory and another image signal. And a synthesizing means for synthesizing the binary image signal and the other image signal according to the control signal, and a changing means for changing the control signal at a predetermined cycle. An image processing device characterized by the above. 4. An image processing apparatus having a digital memory capable of storing a binarized image signal, wherein the combination ratio of the binary image signal read from the digital memory and another image signal is changed. Control signal generating means for generating the control signal, synthesizing means for synthesizing the binary image signal and the other image signal according to the control signal, and changing means for changing the control signal in a predetermined cycle. A control means for controlling a predetermined portion in the other image, wherein the control signal generating means controls the binary image signal from the portion designated by the designating means with respect to the other image signal. An image processing apparatus, which generates a control signal for controlling to start composition. 5. An image processing apparatus having a digital memory capable of storing a binarized image signal, for changing a synthesis ratio of a binary image signal read from the digital memory and another image signal. Control signal generating means for generating a control signal, a synthesizing means for synthesizing the binary image signal and the other image signal according to the control signal, and a motion for detecting a moving portion in the other image. A control means for controlling the control signal generating means so that the binary image signal is finally combined with the other image signal in a portion having a motion detected by the motion detecting means. An image processing device characterized by generating a signal.