JPH07154249A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain the phase locked loop circuit selecting the changeover of desired output frequency interval with a fast rising by connecting a multiplier to an output of a frequency divider being a component of the phase locked loop circuit so as to increase a phase comparison frequency. CONSTITUTION:A multiplier 9 is connected to an output of a frequency divider 4 and its output is given to a phase comparator 3. In this case, when an output frequency is set to 150MHz and a phase comparison frequency is set to 100kHz, a frequency division number of the frequency divider 4 is set to 60000 to make the channel frequency interval to be 30kHz and 12.5kHz, an output of the frequency divider 4 is set to 2.5kHz, and a multiple factor of the multiplier 9 is set to 40, then the phase comparison frequency is set to 100kHz. Through the constitution above, the output frequency is varied at an interval of 2.5kHz by varying the frequency division number of the frequency divider 4 to make the channel frequency interval correspondent to both the frequencies of 30kHz and 12.5kHz.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of the phase pull-in time of a phase locked loop.

[0002]

2. Description of the Related Art FIG. 2 shows a block diagram of a conventional phase locked loop circuit. In this phase locked loop circuit, the output signal of the reference oscillator 1 is input to the frequency divider 2, and the output signal of the frequency divider 2 is added as the reference input signal of the phase comparator 3 '. The phase difference output of the phase comparator 3 is input to the charge pump 8 and converted from a digital signal to an analog signal,
It is input to the voltage controlled oscillator 5 through the low pass filter 7. The output of the voltage controlled oscillator 5 is used as the output 6 and at the same time is input to the frequency divider 4. The output of the frequency divider 4 is input to the comparison input of the phase comparator 3.

This is a conventionally used phase locked loop circuit, which outputs a frequency signal determined by the frequency division ratio of the frequency divider 2 and the frequency divider 4. Here, in order to obtain a phase locked loop circuit having a high response speed, there is a method of increasing the phase comparison frequency by decreasing the frequency division number of the frequency dividers 2 and 4.

[0004]

However, in the above-mentioned configuration of the prior art, if the phase comparison frequency is simply increased to increase the response speed (for example, 100 KHz),
When switching the output frequency of the voltage controlled oscillator,
There is a drawback that switching cannot be performed with a switching width of the phase comparison frequency or less (for example, 100 KHz interval or less). On the other hand, the specifications of the channel spacing are
For example, there are 30KHz and 12.5KHz, but in order to support both of them, the phase comparison frequency is 2.5KHz.
It is necessary to set to Hz. Therefore, in order to satisfy the specifications of the channel spacing, there is a conflicting problem that the phase comparison frequency cannot be increased and the response speed cannot be increased. In view of such circumstances, it is an object of the present invention to provide a phase locked loop circuit capable of switching required output frequency intervals and having a fast rising edge.

[0005]

In order to achieve the above-mentioned object, the present invention is configured to increase the phase comparison frequency by connecting a multiplier to the output of a frequency divider constituting a phase locked loop. is there.

[0006]

[Operation] As a result, the phase comparison frequency can be increased while keeping the output frequency switching width small.
It is possible to configure a phase-locked circuit that can switch the required output frequency interval and that has a fast rise.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the respective units 1 to 8 are the same as the conventional phase locked loop circuit shown in FIG. In the present invention, the multiplier 9 is connected to the output of the frequency divider 4 and its output is connected to the phase comparator 3. Here, the output frequency is 150 MHz and the phase comparison frequency is 100 KHz.
Then, the channel frequency interval is 30 KHz and 12.
To correspond to 5 KHz, the frequency division number of the frequency divider 4 is 60
000, the output of the frequency divider 4 is 2.5 KHz, and the multiplication factor of the multiplier 9 is 40 times, the phase comparison frequency is 100 K.
It becomes Hz. In this configuration, if the frequency division number of the frequency divider 4 is changed, the output frequency can be changed at 2.5 KHz intervals, and the channel frequency interval is set to 30 KHz.
Both 5 KHz can be supported. In addition, since the phase comparison frequency is 100 KHz in this configuration, the response speed of the phase locked loop can be remarkably increased, although it is not 40 times higher than when the phase comparison frequency is 2.5 KHz.

An example of the improved rising characteristic according to the present invention is shown by the solid line in FIG. As shown in this FIG.
A fast rise time of 5 ms or less, which was above ms, is achieved.

[0009]

According to the present invention, a required output frequency interval can be switched and a phase locked loop with a fast rise time can be realized, and the effect is remarkable. Moreover, since the means of the present invention is extremely simple, not only the circuit scale can be small, but also the economy is excellent, and its application range is wide.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional phase locked loop circuit.

FIG. 3 is a characteristic diagram showing a rise of a phase locked loop.

[Explanation of symbols]

 1 Reference Oscillator 2 Divider 3 Phase Comparator 4 Divider 5 Voltage Controlled Oscillator 6 Output 7 Low Pass Filter 8 Charge Pump 9 Multiplier

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9182-5J H03L 7/10 A

Claims (1)

[Claims] 1. An output signal of a voltage controlled oscillator is frequency-divided by a frequency divider, the frequency-divided signal and a reference frequency signal are phase-compared by a phase comparator, and the voltage control transmission is performed by a difference signal of the phase comparison result. A phase synchronization circuit for performing synchronization control of a frequency divider, comprising a multiplier between the output stage of the frequency divider and the input stage of the phase comparator.