JPH07153280A - Layout structure of associative memory - Google Patents

Abstract

PURPOSE:To perform retrieving operation at high speed by arranging plural memory cells constituting plural memory words at both sides of a coincidence line corresponding to each memory words. CONSTITUTION:In memory cells 110-i, 110-j,..., 110-m, 110-n..., memory cells of bits being adjacent one another holding a diffusion layer 140 between them at the upper and lower sides as shown in the figure are alternately arranged. Thereby, the diffusion layer 140 may be shortened, and electric charges previously charged can be discharged at high speed by that of shortened amount, and retrieving operation is improved. Also, a poly silicon layer 240 corresponding to a word line is divided into two layers with this layout. Thereby, by making two layers of the poly silicon layer 240 active, it can be also constituted so that memory cells of bits of odd numbers and memory cells of bits of even numbers in one memory word can be accessed each other independently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory in which stored data is stored in a plurality of memory words, reference data is input, and predetermined stored data is stored using the input reference data. Associative memory that searches for words (A
Sociative Memory, Content Addressable Memory; Content Addressable M
The present invention relates to a layout structure on a semiconductor chip.

[0002]

2. Description of the Related Art In recent years, an associative memory having the above search function has been proposed. FIG. 2 is a circuit block diagram showing an example of the associative memory. The associative memory 10 is provided with a large number of memory words 11a, 11b, ..., 11n, each consisting of 5 bit memory cells arranged in the lateral direction of the figure, with 5 bits as one word. The associative memory 10 also includes a reference data register 12 into which one word of reference data is input and latched. The reference data latched in the reference data register 12 has a bit pattern of all or a predetermined part and each memory word. Of the data stored in 11a, 11b, ..., 11n, the bit pattern of the corresponding portion is compared with the bit pattern of the corresponding portion, and each memory word 1 is compared.
, 1n among the match lines 14a, 14b, ..., 14n provided corresponding to the respective 1a, 11b, ..., 11n, the memory words 11a, 11b ,.
, 14n corresponding to 1n, a match signal of logic "1" (here, 5.0 V) is output, and logic "0" is output to the other match lines 14a, 14b, ..., 14n. 'Mismatch signal is output.

Here, each flag line 14a, 14b, ...
14n are '0', '1', '0', '0',
It is assumed that signals of "1", ..., "0" have been output. This signal is input to the priority encoder 15.
The priority encoder 15 outputs a match line that outputs a logic "1" match signal (here, two match lines 14b and 14e; here, a match line that outputs a logic "1" match signal). The address signal AD corresponding to the highest priority matching line having the highest priority among the matching lines) is output. Here, the lower the alphabet of the subscript, the higher the priority. Therefore, the matching line 14b is the highest priority matching line here. The address signal AD corresponding to the highest priority matching line 14b output from the priority encoder 15 is input to the address decoder 16 as necessary. The address decoder 16 decodes the input address signal AD to provide word lines 17a, 17b, corresponding to the respective memory words 11a, 11b, ..., 11n.
, 17n corresponding to the input address signal AD, any one of the word lines (here, word line 17
An access signal (here, a signal of logic "1") is output to b). As a result, the data stored in the memory word 11b corresponding to the word line 17b to which the access signal is output is read to the output register 18.

As described above, the associative memory 10 searches the contents (stored data) stored in a large number of memory words 11a, 11b, ..., 11n by using all or a predetermined part of the reference data. Is a memory that can obtain the address of a memory word in which the stored data that matches is stored and read out the entire stored data stored in the memory word.

Various circuit configurations have been proposed for the match search of the associative memory, and some examples will be described here. Figure 3
It is a detailed circuit diagram showing an example of one memory word in the associative memory provided with the circuit structure proposed by the present applicant in Japanese Patent Application No. 4-169302.

The memory word 11 is composed of five memory cells 11-1, 11-2, ..., 11-5 having the same structure. Each memory cell 11-1, 11-2, ...,
In 11-5, the output of each other is connected to the input of each other,
The first inverter 20-1, 20-2, ..., 20-5 and the second inverter 21-1, 21-2, ..., 21-5 are provided, and these inverters 20-1, 21-21 are provided.
1; 20-2, 21-2; ...; 20-5, 21-5 to each memory cell 11-1, 11-2 ,. Information is stored.

Further, each memory cell 11-1, 11-2,
, 11-5, the first inverters 20-1, 20
The outputs of −2, ..., 20-5 are transmitted through the N-channel transistors 22-1, 22-2 ,.
, 23-5, and gates of the transistors 22-1, 22-2, ..., 22-5 are connected to the word line 24. The outputs N of the second inverters 21-1, 21-2, ..., 21-5 are channel transistors 25-1, 25-2 ,.
5 through bit bar lines 26-1, 26-2, ..., 26
It is connected to -5, and these transistors 25-1 and 25-2
The gates 5-2, ..., 25-5 are also connected to the word line 24. Further, each memory cell 11-1, 11-2,
, 11-5, bit lines 23-1, 23-2,
..., 23-5 and bit bar lines 26-1, 26-2, ...,
26-5, two N-channel transistors 27-1 and 28- connected in series to each other so as to connect between them
1; 27-2, 28-2; ...; 27-5, 28-5 are arranged, and each of these two transistors 27-1,
28-1; 27-2, 28-2; ...; 27-5, 28-
One of the transistors 27-1, 27-2,
The gate of 27-5 is the first inverter 20-1 or 20-2.
0-2, ..., 20-5 output, the other transistor 28
The gates of -1, 28-2, ..., 28-5 are connected to the outputs of the second inverters 21-1, 21-2, ..., 21-5.

The match line 14 is connected to each memory cell 11-
1, 11-2, ..., 11-5 corresponding to N-channel transistors 36-1, 36-2 ,.
Are provided and their transistors 36-1, 3
, 6-5 are connected to each other in series, and their transistors 36-1, 36-2, ..., 36-5 are connected.
Has two transistors 27-1, 28-
1; 27-2, 28-2; ...; 27-5, 28-5.

Further, another transistor 36-0 is connected in series to the match line 14, and the match line 1
4 is grounded through the transistor 36-0. The gate of the transistor 36-0 is connected to the control line 30. In the associative memory including the memory word having such a structure and its peripheral circuits, the matching search is performed as follows.

It is assumed that information of logic "1" is stored in the memory cell 11-1. That is, in this case, the output side of the first inverter 20-1 is in the logic "1" state and the output side of the second inverter 21-1 is in the logic "0" state. It is assumed that logic "1" is searched for in memory cell 11-1. That is, the bit line 23-1 is set to logic "1" and the bit bar line 26-1 is set to logic "0".
The word line 24 is held in the state of logic "0". In this case, the logic "1" voltage is applied to the gate of the transistor 27-1, and the logic "1" signal of the bit line 23-1 is applied to the gate of the transistor 36-1. It will be in the'on 'state. That is, when the bit information stored in the memory cell 11-1 and the bit information in the reference data input via the bit line 23-1 and the bit bar line 26-1 match, the corresponding transistor 36-1 Turns on.

The memory cell 11-2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20-2 is in the logic "0" state and the output side of the second inverter 21-2 is in the logic "1" state. It is assumed that the memory cell 11-2 is also searched for logic "1". That is, the bit line 23-2 is set to logic "1" and the bit bar line 26-2 is set to logic "0".
In this case, logic “0” is passed through the transistor 28-2.
The signal on the bit bar line 26-2 in the state of is applied to the gate of transistor 36-2, which will therefore remain in the'off 'state. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Further, regarding the masked bits,
As shown in the memory cell 11-5, the bit line 23-5,
Both of the bit bar lines 26-5 are set to logic "1".
In this case, the transistor 27-5 or the transistor 2-5 depends on whether the information of logic "1" or the information of logic "0" is stored in the memory cell 11-5.
Any of 8-5 will be in the'on 'state, which causes
In either case, transistor 36-5 will be in the "on" state.

In the search, the control line 30 first becomes logic "0", the transistor 32 becomes "on", the match line 14 on the input side of the inverter 31 is precharged, and then the control line 30 becomes logic "1". Then, the transistor 32 is turned off, precharge is stopped, and the transistor 36-0 is turned on.

At this time, the information stored in the memory cell and the input search information match in all the memory cells forming this memory word 11 (the masked bits as described above are regarded as a match). In this case, all the transistors 36-1, 36-2, ..., 36-5 are in the “on” state, the precharged charges on the match line 14 are discharged, and the match signal of logic “1” is output from the inverter 31. To be done.

As described above, in the case of the structure shown in FIG.
The match line 14 is precharged prior to the search, and only if there is a match in the search, the transistors 36-0, 36-
Since it is discharged via 1, 36-2, ..., 36-5, in most cases, only a small part of a large number of match lines is discharged for each search.
Most match lines stay precharged,
Therefore, the number of matching lines that need to be precharged at the time of the next search can be small, and the power consumption associated with the search can be suppressed.

FIG. 4 is a circuit diagram showing one memory word of the associative memory proposed by the present applicant in Japanese Patent Application No. 5-216424. The components corresponding to the components of the circuit shown in FIG. 3 are denoted by the same numbers as those given in FIG. 3, and only the differences will be described. The memory word shown in FIG. 4 has two N-channel transistors 27-1, 28-1; 27-2, 28-2 for each memory cell in the memory word shown in FIG.
...; instead of 27-5 and 28-5, two P-channel transistors 37-1 and 38-1; 37-2 and 38-
2; ...; 37-5 and 38-5 are provided. Each of these two P-channel transistors 37-1, 38-
1; 37-2, 38-2; ...; One of the transistors 37-1, 37-2, ..., 37 of 37-5, 38-5
The gate of -5 is the second inverter 21-1, 21-
, ..., 21-5 are connected to the outputs of the other transistors 38-1, 38-2 ,.
, 20-5 are connected to the outputs of the inverters 20-1, 20-2 ,.

Also, transistors 36-0, 3 connected in series with each other between the match line 14 and the ground GND.
, 36-5, a P-channel transistor 39 is arranged between the transistor 36-0 and the transistor 36-1. The gate of the transistor 39 is diode-connected to the transistor 36-0 side.

In the associative memory having the memory word having such a structure and its peripheral circuit, the matching search is performed as follows. The memory cell 11-1 has a configuration shown in FIG.
As in the case of the above description, it is assumed that the information of logic '1' is stored. That is, in this case, the first inverter 20-
The output side of 1 is in the state of logic "1", and the output side of the second inverter 21-1 is in the state of logic "0".

It is assumed that logic "1" is searched for in memory cell 11-1. That is, the bit line 23-1 is set to logic "1" and the bit bar line 26-1 is set to logic "0". The word line 24 is held in the state of logic "0". In this case, a voltage of logic "0" is applied to the gate of the transistor 37-1, and the bit line 23
A logic "1" signal of -1 is applied to the gate of transistor 36-1, which causes transistor 36-1 to be in the "on" state. That is, the bit information stored in the memory cell 11-1 and the bit line 23-1, the bit bar line 26-1
When the bit information in the reference data input via the same matches, the corresponding transistor 36-1 is'on '.
It becomes a state.

The memory cell 11-2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20-2 is in the logic "0" state and the output side of the second inverter 21-2 is in the logic "1" state. It is assumed that the memory cell 11-2 is also searched for logic "1". That is, the bit line 23-2 is set to logic "1" and the bit bar line 26-2 is set to logic "0".
In this case, logic "0" is passed through the transistor 38-2.
The signal on the bit bar line 26-2 in the state of is applied to the gate of transistor 36-2, which will therefore remain in the'off 'state. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Regarding the masked bits,
As shown in the memory cell 11-5, the bit line 23-5,
Both of the bit bar lines 26-5 are set to logic "1".
In this case, the transistor 37-5 or the transistor 3-5 depending on whether the information of logic "1" or the information of logic "0" is stored in this memory cell 11-5.
Any of 8-5 will be in an'on 'state, which will cause transistor 36-5 to be in an'on' state in either case.

In the search, the control line 30 first becomes the logic "0", the transistor 32 becomes the "on" state, the match line 14 on the input side of the inverter 31 is precharged, and then the control line 30 becomes the logic "1". Then, the transistor 32 is turned off, precharge is stopped, and the transistor 36-0 is turned on.

At this time, the information stored in the memory cell and the input search information match in all the memory cells forming the memory word 11 (the masked bits as described above are regarded as a match). In this case, all the transistors 36-1, 36-2, ..., 36-5 are in the “on” state, the charge precharged on the match line 14 is discharged, and the inverter 31 outputs a signal of logic “1”. It

As described above, in the case of the structure shown in FIG.
As in the case of the structure shown in FIG. 3, the match line 14 is precharged prior to the search and is discharged only when a match is found by the search, so that the match line 14 that needs to be precharged during the next search is The number is small, and the power consumption associated with the search is kept low. FIG. 5 shows FIG. 3 and FIG.
FIG. 9 is a schematic diagram showing a layout on a semiconductor chip of a plurality of memory cells forming one memory word 11 shown in FIG. Here, one memory word is illustrated as being composed of eight or more memory cells.

A plurality of memory cells ... 110-i, 11
0-j, ..., 110-m, 110-n, ... are formed in a row arranged in a row on the left and right sides of the drawing, and their memory cells ..., 11-i, 11-j ,. -K,
A diffusion layer 140 corresponding to the coincidence line 14 shown in FIGS. 3 and 4 extends along. In the diffusion layer 140, each memory cell ... 110-i, 110-j ,.
m, 110-n, ..., Polysilicon layers corresponding to the gates of the transistors 36-1, 36-2, ..., 36-5 shown in FIGS. 3 and 4, 360-i, 360-j ,.
, 360-m, 360-n, ... Extend so as to traverse the diffusion layer 140, and the polysilicon layer of the diffusion layer 140 ... 360-i, 360-j ,.
Each transistor is formed in each portion which 60-n, ... Crosses.

Further, a plurality of memory cells ... 110-
The polysilicon layer 240 extends over i, 110-j, ..., 110-m, 110-n ,. The polysilicon layer 240 corresponds to the word line 24 shown in FIGS. 3 and 4, and the transistors 22-1 and 25-25 shown in FIGS.
1; 22-2, 25-2; ...; 22-5, and the polysilicon layer forming the gate of 25-5 is used as the wiring of the coincidence line 14 as it is to suppress the layout area.

Further, in the vertical direction of the figure, metal wirings corresponding to the bit lines 23-1, 23-2, ..., 23-5 shown in FIGS. 3 and 4, 230-i, 230-j ,. 23
0-m, 230-n, ... And metal wirings corresponding to the bit bar lines 26-1, 26-2, ..., 26-5 shown in FIGS. 3 and 4, 260-i, 260-j ,. …, 26
0-m, 260-n, ...

[0028]

The coincidence line 14 shown in FIGS. 3 and 4 has the same layout as the diffusion layer 14 shown in FIG.
Although it is preferable to form the diffusion layer 140 with 0, the diffusion layer 140 has a high wiring resistance, and it takes time to discharge the precharged charges, which causes a problem that the search operation speed decreases. . In order to improve the search operation speed, it is desirable to shorten the wiring length of the diffusion layer 140, but each memory cell ... 110-i,
There is a limit in suppressing lateral pitches of 110-j, ..., 110-m, 110-n ,.

In view of the above circumstances, it is an object of the present invention to provide a layout structure of an associative memory in which a search operation is speeded up.

[0030]

A layout structure of an associative memory according to the present invention which achieves the above object, includes a plurality of memory cells each of which stores 1-bit data. A semiconductor chip of an associative memory in which stored data composed of a set of bit data is stored, reference data is input, and the input reference data is used to search for a memory word in which predetermined stored data is stored. In the layout structure above,
(1) Each match line is provided corresponding to each of the plurality of memory words, and outputs a match signal indicating whether or not predetermined storage data is stored in each memory word at the time of search, 2) A plurality of memory cells forming each of the plurality of memory words are arranged on both sides of each match line corresponding to each memory word.

[0031]

In the layout structure of the associative memory of the present invention, since the memory cells are arranged on both sides of the match line, the length of the match line can be reduced to about half. Therefore, the search operation speed is improved. Further, the polysilicon layer 240 shown in FIG. 5, which corresponds to the word line 24 shown in FIGS. 3 and 4, also has a large wiring resistance, which causes a decrease in operating speed.
For this reason, conventionally, a metal layer was used for lining, a layout area was increased, and a severe condition was imposed on the layout itself, if necessary. However, according to the present invention, the word line is divided into two. However, the length is reduced to about half, which also contributes to the improvement of the operation speed.

Further, according to the present invention, since the word line is divided into two, it is possible to independently activate each one of the two word lines, and thus, for example, only even bits of the memory word are activated. , Or only odd bits can be accessed independently of each other.

[0033]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram showing a layout structure on a semiconductor chip of an associative memory according to an embodiment of the present invention. In FIG. 1, for the sake of clarity, the difference in layout is overcome,
Elements corresponding to the elements of the layout structure shown in FIG. 5 are designated by the same reference numerals in FIG. 5, and only different points will be described.

The memory cell shown in FIG. 1 ... 110-
i, 110-j, ..., 110-m, 110-n, ...
, Memory cells of adjacent bits are alternately arranged above and below in FIG. 1 across the diffusion layer 140 (match line 14; see FIGS. 3 and 4). Therefore, the diffusion layer 140
Is about half the length of the layout shown in Fig. 5,
The precharged charges are discharged at a high speed, and the search operation speed is improved.

With this layout, the polysilicon layer 24 corresponding to the word line 24 (see FIGS. 3 and 4) is also formed.
0 is divided into two. Therefore, when the two polysilicon layers 240 (word lines 24) are activated separately, for example, when the polysilicon layer 240a is activated, an odd-numbered bit memory cell can be accessed, and the polysilicon layer can be accessed. When 240b is activated, memory cells of even bits can be accessed,
As described above, the odd-bit memory cells and the even-bit memory cells in one memory word can be independently accessed.

Further, with the layout shown in FIG.
Bit line ..., 230-i, 230-j, ..., 230-
m, 230-n, ... And bit bar line ..., 26
0-i, 260-j, ..., 260-m, 260-n, ...
Are laid out in a mutually interleaved manner as shown in the figure, for example.

[0037]

As described above, according to the layout structure of the associative memory of the present invention, the length of the matching line can be reduced to almost half, and therefore the search operation speed can be improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a layout structure on a semiconductor chip of an associative memory according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an example of an associative memory.

FIG. 3 is a detailed circuit diagram showing an example of one memory word in the associative memory.

FIG. 4 is a circuit diagram showing another example of one memory word of the associative memory.

5 is a schematic diagram showing a layout of a plurality of memory cells forming one memory word shown in FIGS. 3 and 4 on a semiconductor chip. FIG.

[Explanation of symbols]

110-i, 110-j, 110-m, 110-n memory cell 140 diffusion layer (matching line) 240 word line 230-i, 230-j, 230-m, 230-n bit line 260-i, 260- j, 260-m, 260-n bit bar line 360-i, 360-j, 360-m, 360-n polysilicon layer

Claims (1)

[Claims] 1. Storage data consisting of a set of the 1-bit data is stored in each of a plurality of memory words each consisting of a plurality of memory cells each storing 1-bit data, and reference data is input. In the layout structure on the semiconductor chip of the associative memory that searches the memory word in which the predetermined storage data is stored using the input reference data, the layout is arranged corresponding to each of the plurality of memory words. The plurality of memory cells forming each of the plurality of memory words are provided with respective match lines that output a match signal indicating whether or not predetermined storage data is stored in the respective memory words during a search. The layout structure of the associative memory, wherein the associative memory is arranged on both sides of the match line corresponding to each memory word.