JPH07152805A - Verifying method for resistance pattern - Google Patents

Abstract

PURPOSE:To provide a method which can fast end correctly verify a resistance pattern. CONSTITUTION:When the layout of a semiconductor integrated circuit is designed, the resistance value of a resistance pattern 3 is calculated based on the length, the width, the coordinate position, etc., of the pattern 3. Then the resistance value of the pattern 3 is compared with the design resistance value for correction of the pattern 3. In this verifying method of the pattern 3, the data on the length, the width, the coordinate position, etc., of each pattern 5 of a semiconductor correction circuit are stored after the layout of the semiconductor integrated circuit is set. So that the resistance value of the pattern 3 is calculated by an arithmetic circuit, etc., based on those stored data when the pattern 3 is verified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying a resistance pattern in a layout design of a semiconductor integrated circuit by CAD.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, a resistance portion is constructed as shown in FIG. That is, in FIG. 2, the resistance portion 1 of the semiconductor integrated circuit is provided with the resistance pattern 3 routed as shown in the drawing on the surface of the semiconductor substrate 2.

Here, the resistance pattern 3 has a linear pattern portion 3a formed in the region of the block 5 extending from the electrode portion 4 along the peripheral edge of the resistance portion 1, and the block 5
A pattern portion 3b formed to reciprocate in the vertical direction in the area of the block 6 adjacent to the block 6 and a pattern portion 3c formed to reciprocate in the lateral direction in the area of the block 7 on the right side of the block 6. It is routed through to the electrode portion 8 through.

The resistance portion 1 of the semiconductor integrated circuit thus configured is usually formed by a layout design by CAD, and when verifying the resistance value of the resistance pattern of the resistance portion 1. The resistance pattern is verified as shown in FIG.

That is, in FIG. 3, a semiconductor integrated circuit is first designed by CAD, and after the design is completed, the resistance pattern 3, that is, the length of each resistance pattern 3a, 3b, 3c,
By measuring the width, coordinate position, etc., and calculating the resistance value by calculation based on the measured values of the length, width, etc.,
The calculated resistance value is compared with the design resistance value, and the resistance pattern is corrected based on the result of this comparison, and the resistance pattern is verified again, that is, the length and width of the resistance pattern are measured and the resistance value is determined. By performing the verification of calculating and comparing with the design resistance value and repeating the above work,
The resistance value of the actual resistance pattern can be brought close to the design resistance value. Thus, the resistance value of the resistance pattern 3 is verified.

[0006]

However, in such a resistance pattern verification method, the length, width, etc. of the resistance pattern 3, that is, the resistance patterns 3a, 3b, 3c are measured manually. Further, since the calculation of the resistance value based on the measured value after that is also performed manually, the time for the above measurement and calculation becomes long, and the accuracy is particularly high because the measurement is performed manually. There was a problem that I could not do it.

In view of the above points, the present invention has made it possible to verify a resistance pattern quickly and accurately.
It is intended to provide a method for verifying a resistance pattern.

[0008]

According to the present invention, the resistance value of a resistance pattern is designed based on data such as length and width of the resistance pattern and coordinate position in the layout design of a semiconductor integrated circuit. In the method of verifying the resistance pattern, the calculated resistance value is compared with the design resistance value to correct the resistance pattern. After the layout of the semiconductor integrated circuit is set, the semiconductor integrated circuit is set. The data such as the length, width, coordinate position, etc. of each resistance pattern is stored, and when the resistance pattern is verified, the resistance value of the resistance pattern is calculated based on the stored data. It is achieved by a method of verifying a resistance pattern, which is calculated by

[0009]

According to the above structure, the length, width, and
The data such as the coordinate position can be obtained by storing the data at the time of layout design, and the calculation of the resistance value of the resistance pattern can be performed by the arithmetic circuit based on the storage data. The measurement of data such as the length, width, and coordinate position of the resistance pattern, and the calculation of the resistance value based on these data can be automatically acquired without manual labor and can be easily calculated by the arithmetic circuit.

Therefore, the time required for the entire process of verifying the resistance pattern can be extremely shortened and can be performed more accurately. Furthermore, the design efficiency of the entire semiconductor integrated circuit can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. FIG. 1 shows an embodiment of a method for verifying a resistance pattern of a semiconductor integrated circuit according to the present invention. Here, the resistance pattern to be verified is the resistance pattern 3 shown in FIG. 2 as in the conventional case.

In FIG. 1, a semiconductor integrated circuit is first designed by CAD, and the CA of the length, width, coordinate position, etc. of the resistance pattern 3, that is, each resistance pattern 3a, 3b, 3c is CA.
The data in the D design is stored in, for example, a RAM or another appropriate auxiliary storage device. Thus, the design is completed, and thereafter, the resistance value is calculated by the automatic calculation by the arithmetic circuit based on the stored data. The acquisition of the resistance value of the resistance pattern described above is performed automatically by a computer or the like, that is, without the need for manpower.

Then, as in the conventional case, the calculated resistance value is manually compared with the designed resistance value, and the resistance pattern is corrected based on the result of the comparison, and the resistance pattern is verified again. That is, the length and width of the resistance pattern are measured, the resistance value is calculated, and the comparison with the design resistance value is verified again. By repeating the above work, the actual resistance value of the resistance pattern becomes the design resistance value. You can get closer.

In the above-mentioned embodiment, the verification of the resistance pattern is described, but in the case of a conductive pattern wiring made of aluminum, for example, it is necessary to add logical information to each wiring at the time of designing. Thus, it is possible to verify the wiring resistance value and capacitance of this conductive pattern wiring.

[0015]

As described above, according to the present invention, it is possible to provide an extremely excellent method for verifying a resistance pattern, which enables the verification of the resistance pattern to be performed quickly and accurately. .

[Brief description of drawings]

FIG. 1 is a schematic view showing an embodiment of a resistance pattern verification method according to the present invention.

FIG. 2 is a schematic diagram showing a shape of a resistance pattern of a general semiconductor integrated circuit.

FIG. 3 is a schematic diagram showing an example of a conventional method for verifying the resistance pattern of FIG.

[Explanation of symbols]

 1 resistance part of semiconductor integrated circuit 2 semiconductor substrate 3 resistance pattern 4, 8 electrode part

Claims (1)

[Claims] 1. When designing a layout of a semiconductor integrated circuit,
The resistance value of the resistance pattern is calculated based on the data such as the length width and the coordinate position of the resistance pattern, and the calculated resistance value and the designed resistance value are compared to correct the resistance pattern. In the resistance pattern verification method, after the layout of the semiconductor integrated circuit is set, data such as the length, width, coordinate position, etc. of each resistance pattern of the semiconductor integrated circuit is stored and used for verifying the resistance pattern. In the method for verifying a resistance pattern, the resistance value of the resistance pattern is calculated by an arithmetic circuit or the like based on the stored data.