JPH07152468A - Key matrix input device - Google Patents

Abstract

PURPOSE:To reduce the number of output ports at a microcomputer by providing a means for storing the potentials of key input signal lines at a key matrix. CONSTITUTION:Signal lines P101-P104 are the signal lines of respective ports at an input/output port 1, connected to the input side of a key matrix 3 and normally set at a ground potential by a pull-down resistor 2. A diode 6 is connected to the signal lines P101-P104, and a storage device 5 is composed of a flip-flop and controlled by a signal line P01. An output port 7 is composed of a single buffer and controls the storage device 5 by using the signal line P01. When the key of the key matrix 3 is pressed, the potential is stored in the storage device 5, and the output of the storage device 5 is connected to the signal lines P101-P104 by the diode 6 for preventing backward current. On the other hand, corresponding to the signal of the output port 7 connected to the control signal line P01, it is controlled whether stored contents are held or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key matrix input device, and more particularly to a key matrix device controlled by a microcomputer.

[0002]

2. Description of the Related Art A conventional key matrix input device for a microcomputer 20, as shown in FIG. 4, is connected to a key matrix 3 and an input / output port 1 for performing a key scan.
And an input port 8 for reading each scan result in the input / output port 1, and the input / output port 1 is fixed at a low level (a voltage at which the input port can be judged to be 0 as a logical value) when a key is not pressed. And a pull-down resistor 2 for

The input / output port 1 is provided with a plurality of unit circuits each including two buffers that output each other's inputs. These buffers are controlled so that only one buffer operates depending on the input / output. The input port 1 includes a plurality of unit circuits each including one buffer. The key matrix 3 is provided with keys of 4 rows and 4 columns, and is electrically connected by being pressed.

Next, this operation will be described with reference to FIG. 5 which is a timing chart of key scanning and reading of a conventional key matrix input device. The signal lines P101 to P1 will be described below.
The waveform of 04 is a signal line waveform of each port of the input / output port 1, and the waveforms of the signal lines P11 to P14 are signal line waveforms of each port of the input port 8. The key scan method using the input / output port 1 is to set any one signal line to a high level (input port 1) at the same timing (T1 to T4).
Is set to be an output of a logic value of 1) and all the others are set as inputs, and the ports set as outputs are sequentially switched and repeated.

The key is judged by the signal line P1 of the input port 8.
When any one of the ports 1 to P14 detects a high level, it is determined by the values of the signal lines P101 to P104 of the input / output ports which are outputting at the same timing. Now key 3
The key scan and read timings when 1 is pressed are as shown in FIG. That is, at the timing T2, the signal line P11 becomes high level, so the key 31
It is determined that is pressed.

As shown in FIG. 6, there is also a key matrix input device in which the number of ports is reduced by providing a selector 11 for switching the input line of the key matrix according to the output level of the output port 7. This selector 11 is PN
A plurality of P and NPN transistors are used as one set.
A signal from the output port 7 turns on only one transistor in the selector 11. By doing this, the signal line P
Only two of 11 and P12 are required, which is half of the case of FIG.

[0007]

All such conventional key matrix input devices require an input / output port 1 dedicated to a key scan and an input port 8 dedicated to reading a scan result, and a large number of ports are required. There is a drawback that becomes.

[0008]

A key matrix input device of the present invention comprises an input / output port whose input / output can be switched,
A key matrix having a plurality of switches placed at each intersection of the key input signal line and the key output signal line connected to the input / output port, and means for storing the potential of the key input signal line of the key matrix. It is characterized by

[0009]

1 is a circuit diagram showing a key matrix input device according to a first embodiment of the present invention, and FIG. 2 is a timing diagram showing the key scan and read timing of this key matrix input device.

In FIG. 1, this embodiment is the same as FIG. 4 except that it has a pull-down resistor 2, a storage device 5, and a diode 6 and that it has only one output port 7. Omit it. The diode 6 is connected to each of the signal lines P101 to P104, the storage device 5 is composed of a plurality of flip-flops, and is controlled by the signal line P01. Output port 7 consists of only one buffer,
Each flip-flop in the memory device 5 is controlled by only one signal line P01.

In FIG. 2, signal lines P01 and P101-
Regarding the logic level and the input / output relation of P104, it is shown for each timing T11 to T13.

The signal lines P101 to P104 are signal lines for the respective ports of the input / output port 1, are connected to the input side of the key matrix 3, and are normally at the grad potential by the pull-down resistor 2. When a key of the key matrix 3 is pressed, the potential is stored in the storage device 5 composed of a latch circuit connected to the output side. Normally, the pull-down resistor 4 provides the ground potential. The output of the storage device 5 is supplied to the signal line P1 by the diode 6 for preventing reverse current.
01 to P104. Further, by the signal of the output port 7 connected to the control signal line P01, it is controlled whether or not the stored content is held.

Next, the operation of this embodiment will be described with reference to FIG. In FIG. 2, the key scan method by the input / output port 1 is based on the timing Tn1 (T11, T21,
In T31, T41), set any one signal line to high
Set the level output port and all other input ports. Further, the timing Tn2 (T12, T22,
At T32, T42), the output port 7 stores the potential in the memory device 5. The key is determined at timing Tn3 (T1
3, T23, T33, T43), all the input / output ports 1 are used as input ports, and when any one of the input ports detects a high level, it is performed. All the keys can be detected by repeating the operations at timings Tn1 to Tn3 from P101 to P104. The key scan and read timings when the key 31 is pressed are as shown by the signal line P101.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. 3, in this embodiment, the output port 7 and the storage device 5 of FIG.
3 is the same as that of FIG. Where capacitor 1
0 is provided between the signal line and the ground. The diode 9 is connected in series to each of the signal lines P101 to P104.

[0015]

As described above, by using the key matrix input device of the present invention, the number of output ports of the microcomputer can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the relationship between key scan and read timing of the key matrix input device of this embodiment.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional key matrix input device.

FIG. 5 is a timing diagram showing a relationship between key scan and read timing of a conventional key matrix input device.

FIG. 6 is a block diagram of another example of a conventional key matrix input device.

[Explanation of symbols]

 1 Input / output port 2,4 Pull-down resistance 3 Key matrix 5 Storage device 6,9 Diode 7 Output port 8 Input port 10 Capacitor 11 Selector 20 Microcomputer 31 key

Claims (1)

[Claims] 1. A key matrix having an input / output port whose input / output can be switched, and a plurality of switches placed at respective intersections of a key input signal line and a key output signal line connected to the input / output port; And a means for storing the potential of the key input signal line of the key matrix.