JPH0715014A - Formation of gate electrode of mos field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a gate electrode forming method of a MOS field effect transistor wherein generation of notch is prevented and a microstructural MOS field effect transistor can be manufactured. CONSTITUTION:A gate oxide film 2 composed of SiO2 is formed on a semiconductor substrate 1, and a conductor film 3 composed of TiN or TiC is formed on the gate oxide film 2. A poly silicon film 4 is formed on the conductor film 3, and resist 5 is selectively formed on the poly silicon film 4. The poly silicon film 4 except the part covered with the resist 5 is eliminated by, e.g. high density plasma etching. Thereby the poly silicon film 4 left under the resist 5 is turned into a gate electrode 6. The resist 5 is eliminated. In the process for eliminating the resist, the exposed conductor film 3 is oxidized and an insulating film 7 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS for forming a gate electrode by dry etching such as plasma etching.
The method for forming the gate electrode of the field effect transistor
In particular, the present invention relates to a method for forming a gate electrode of a MOS field effect transistor suitable for manufacturing a miniaturized MOS field effect transistor.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional LDD (Lightly Doped).
Drain) MOS field effect transistor (MOS)
It is sectional drawing which shows (FET).

A field oxide film 12 is selectively formed on the surface of the semiconductor substrate 11, and the surface of the substrate is divided into a plurality of element formation regions by the field oxide film 12. Further, a source region 13 and a drain region 14 are formed separately from each other on the substrate surface of the element formation region. Furthermore, SiO ₂ is formed on the substrate surface in the element formation region.
A gate insulating film 15 made of is formed. In addition, electric field relaxation regions 13 a and 14 a having a lower impurity concentration than the source region 13 and the drain region 14 are provided at the end portions of the source region 13 and the drain region 14 which face each other.

A gate electrode 16 made of polysilicon is selectively formed on the gate oxide film 15 in the region between the source region 13 and the drain region 14. And
Sidewall protective films 17 are formed on both sides of the gate electrode 16. In addition, for example, an insulating film 18 is formed on the entire upper surface of the substrate.
An interlayer insulating film formed by laminating a and 18b is formed. Aluminum wiring (not shown) is formed in a predetermined pattern on the interlayer insulating film, and the aluminum wiring is formed by filling an opening selectively provided in the interlayer insulating film with aluminum. 19
Is electrically connected to the source region 13 and the drain region 14 via. The aluminum wiring is covered with an insulating film 18c.

In the MOS field effect transistor having such a structure, a predetermined voltage is applied between the source region 13 and the drain region 14 and the gate electrode 16 is also applied.
When a voltage is applied to the substrate, an inversion layer (channel) is formed on the substrate surface immediately below the gate electrode 16, and a current flows between the source region 13 and the drain region 14 via this channel. The current flowing through the source region 13 and the drain region 14 changes according to the voltage value applied to the gate electrode 16.

FIG. 3 is a sectional view showing a method of forming a gate electrode of a conventional MOS field effect transistor. First,
After forming the gate oxide film 15 on the semiconductor substrate 11, a polysilicon film 16a is formed on the entire surface. Next, a resist solution is applied to the entire surface of the polysilicon film 16a, and exposure and development processes are performed to leave the resist 20 in a desired gate electrode pattern.

Next, the polysilicon film 16a is etched by plasma etching using a reactive gas such as Cl ₂ . As a result, the polysilicon film 16a other than the portion covered by the resist 20 is removed, and the resist 20
The polysilicon film 16a left under the gate becomes a gate electrode. After that, the resist 20 is removed. As a result, the gate electrode is completed.

By the way, as shown in FIG. 3, since the upper half of the field oxide film 12 projects from the substrate surface,
Polysilicon film 1 at the end of field oxide film 12
The thickness T _{2 of} 6a is the polysilicon film 16 on the element formation region.
It is thicker than the thickness T ₁ of a. Therefore, in order to completely remove the polysilicon film 16a other than the portion covered by the resist 20 by vertical processing of normal dry etching, the polysilicon film 16a in the flat portion is removed.
It is necessary to continue the etching even after the removal of the above to remove the polysilicon film 16a at the end portion of the field oxide film 12. Therefore, when forming the gate electrode, generally, etching is performed to remove a polysilicon film having a thickness twice that of T ₁ (hereinafter referred to as 100% over-etching).

[0009]

However, the above-mentioned conventional method for forming a gate electrode has the following problems. In recent years, miniaturization of MOS field effect transistors has been promoted in response to higher density of semiconductor devices. Therefore, an etching method using high-density plasma such as ECR (Electron Cyclotron Resonance) etching has come to be used for forming the gate electrode. However, with the miniaturization of the gate electrode, as shown in FIG. 4, a processing abnormality occurs in which the lower portion of the gate electrode 16 is etched in the horizontal direction. This abnormal processing is called a notch. In the present application, when the height of the gate electrode is A and the notch amount is B, the notch ratio is defined as (B / A).

FIG. 5 is a schematic sectional view showing a gate processing evaluation sample (line and space: hereinafter referred to as L / S). The L / S is obtained by arranging resists 20 having a predetermined width on the polysilicon film at a constant pitch, and the etching conditions and the like are evaluated by the shape of the gate electrode 16 after etching. From the experiment using this L / S, as shown in FIG. 6, the notch has the gate electrode 16 at the end of the plurality of arranged gate electrodes 16.
It is known that there are cases where it occurs only in one case and cases where it occurs in all the gate electrodes 16 as shown in FIG. 7. It is also known that a finer gate electrode pattern is more likely to cause a processing abnormality. When the notch occurs, the gate length that determines the characteristics of the transistor cannot be set to a desired length, which causes variations in transistor characteristics and also causes a reduction in manufacturing yield.

The present invention has been made in view of the above problems, and can be applied to the manufacture of a fine MOS field effect transistor, can prevent the occurrence of notches, and improve the manufacturing yield of the MOS field effect transistor. An object of the present invention is to provide a method of forming a gate electrode of a MOS field effect transistor that can be used.

[0012]

A method of forming a gate electrode of a MOS field effect transistor according to the present invention comprises a step of forming a gate oxide film on a semiconductor substrate and a step of forming a gate oxide film on the gate oxide film as compared with polysilicon. A step of forming a base film made of a conductor having a large chemical bonding force, a step of forming a polysilicon film on the base film, a step of forming a resist on the polysilicon film in a predetermined pattern, and a dry step. A step of performing etching to leave the polysilicon film only under the resist and remove the polysilicon film in other regions.

[0013]

The present inventors conducted various experimental studies to clarify the mechanism of notch generation. That is, first, 100% over-etching was performed while changing the substrate temperature variously, and the relationship between the notch and the substrate temperature was investigated. FIG. 9 is a graph showing the temperature dependence of the notch ratio, with the substrate temperature on the horizontal axis and the notch ratio on the vertical axis. However, as the etching conditions, the microwave output is 250 W, the Cl ₂ gas flow rate is 20 sccm, the pressure is 0.85 mTorr, and the RF (high frequency) bias (Vpp) is 100 V. As is clear from FIG. 9, the notch ratio does not change even when the substrate temperature changes, and the temperature dependence peculiar to the chemical reactivity (radical) is not seen. From this, it was found that the notch generation is an ion-driven reaction.

Next, the notch amount was examined by changing the L / S pattern. As a result, it was found that among the plurality of arranged gate electrodes, the notch is more likely to occur in the gate electrode located at the end portion, and the notch is more likely to occur in the one in which the pattern is connected to another pattern. .

Next, when the notch on the processed wafer was examined, it was found that the notch occurred regardless of whether the plasma was uniform or nonuniform. When these notch amounts were plotted against the logarithm of electron dissociation, they became almost straight lines. From this, it was found that the notch amount is a function of the electron density. It was also found that the notch does not occur until the gate oxide film below the polysilicon film is exposed by etching, but occurs after the gate oxide film is partially exposed.

From the results of these experiments, the inventors of the present application
The notch generation mechanism was considered as follows. That is,
During plasma etching, the semiconductor substrate is negatively charged. As shown in FIG. 8A, the velocity of electrons 23 that enter the semiconductor substrate against the sheath potential decreases in the vertical direction due to the electric repulsive force of the substrate 11, and thus the electrons 23 are applied to the resist 20 that is an insulator. Easy to be absorbed. For this reason,
The resist 20 is negatively charged. As a result, the resist 2
The potential of the polysilicon film 16a in contact with 0 changes to a positive potential so as to cancel the charge-up of the resist. Further, since the polysilicon film 16a is conductive, the portion not in contact with the resist 20 is kept at a negative potential so as not to change the potential of the entire polysilicon film 16a.

When the etching progresses and the gate oxide film 15 is partially exposed as shown in FIG. 8B, the positive ions penetrating into the gate oxide film 15 are accumulated and the gate oxide film 15 is locally exposed. Positively charged areas 22 are generated. In this case, since the electron 23 having a negative charge has a small mass,
In addition, since the vertical velocity decreases due to the repulsive force due to the potential of the substrate 11 and the lateral velocity component relatively increases, the traveling direction changes and collides against the side wall such as the resist wall and is absorbed. The gate oxide film 15 is hardly reached.

FIG. 10 is a schematic diagram showing the repulsive force of static electricity received by the ions 24 from the charged region 22 generated in the gate oxide film. The ions 24 receive a force F ₁ toward the substrate surface due to the sheath potential. Further, the repulsive force F ₂ is electrically received from the positively charged charging area 22. Therefore, the substantial force F ₃ received by the ion 24 is represented by the vector sum of F ₁ and F ₂ . The electrostatic repulsive force F ₂ is represented by the following formula 1 where e is the elementary amount of electricity, Q is the charge of the charged region 22, and r is the distance between the charged region 22 and the ions.

[0019]

[Formula 1] F ₂ = (e + Q) / r ²

Therefore, the force F ₃ received by the ions increases in inverse proportion to the distance r ² between the charged area and the ions. Further, as shown in FIG. 11, the horizontal force F _x3 received by the ions is represented by F _x3 = cos θ. Therefore, ion 2
The horizontal force F _x3 received by 4 becomes maximum when θ = 0 °.

In normal etching, as shown in FIG.
As shown in (b), the resist that is an organic film and the reaction by-products generated by the reaction adhere to the sidewalls of the polysilicon layer and play the role of the sidewall protection film 25 that prevents lateral etching. Therefore, the lateral etching does not proceed unless the horizontal energy of the ions 24 is a certain value or more. When the ions 24 approach the charged region 22, the energy of the ions 24 in the horizontal direction increases and exceeds the predetermined value, so that etching progresses and a notch occurs.

It is considered that the notch is generated in this way, but during the progress of notch formation, it is considered that the following action is added in addition to the action of the charging region described above. That is, as shown in FIG. 8C, the plasma electrons 23 incident on the substrate are absorbed by the resist 20, which is an insulator. As a result, when the resist 20 is negatively charged, the polysilicon film 16 in the portion contacting the resist 20 is charged.
a Positive charges are collected on the upper part, and negative charges are collected on the lower part to compensate for electrical neutrality. As a result, the bottom of the negatively charged polysilicon film 16a and the positively charged charging region 2
An electric field is locally generated between the two. By this electric field,
The ions 24 are accelerated horizontally.

The inventors of the present application obtained an empirical formula shown in the following formula 2 from these experiments and consideration.

[0024]

NR = C · exp (−r / n _e ) where NR; notch generation ratio C; constant r; amount proportional to etching pattern width n _e ; electron density

From this empirical formula, it is possible to explain that notches are more likely to occur in high density plasma, and the notches are more likely to occur as the pattern width of the polysilicon electrode is narrower.

As described above, it has been found that the notch is generated by locally forming a charged region on the gate oxide film. Therefore, in the present invention, first, an underlayer made of a conductor having a larger chemical bonding force than that of polysilicon is formed on the gate oxide film. Next, a polysilicon film is formed on this base film, and this polysilicon film is dry-etched to form a gate electrode. In this etching process, even if the polysilicon film is partially removed,
Since the base film made of a conductor is provided under the polysilicon film, formation of a charged region where charges are partially accumulated is avoided. Therefore, the occurrence of notches can be prevented. In addition, in order that the base film is not removed by etching, it is necessary that the chemical bonding force of the conductor is larger than that of polysilicon.

Further, TiN or TiC is used as the base film.
When (titanium carbide) is used, it is oxidized in the resist removing step after etching and becomes a TiO-based insulator, so that the step of removing the base film after etching is unnecessary. Therefore, the conductor forming the base film is preferably TiN or TiC.

[0028]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIGS. 1A to 1D are sectional views showing a method of forming a gate electrode of a MOS field effect transistor according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 1 (a), a gate oxide film 2 made of SiO ₂ is formed on the semiconductor substrate 1, TiN or T on the gate oxide film 2
The conductor film 3 made of iC is formed with a thickness of, for example, 50 to 100Å. Further, the polysilicon film 4 is formed on the conductor film 3.

Next, as shown in FIG. 1B, a resist 5 is formed in a desired gate electrode shape on the polysilicon film 4.

Next, as shown in FIG. 1C, the polysilicon film 4 is etched by high density plasma etching to remove the polysilicon film 4 other than the portion covered with the resist 5. As a result, the polysilicon film remaining below the resist 5 becomes the gate electrode 6. In this etching step, since the conductor film 3 is formed on the gate oxide film 2, it is possible to avoid the occurrence of a local charged region on the substrate. Therefore, it is possible to prevent a notch from being formed under the gate electrode 6. Also, TiN and T
Since iC has a larger chemical bonding force than polysilicon, the conductor film 3 made of TiN or TiC is hardly etched.

Next, as shown in FIG. 1D, the resist 5 is removed. In the step of removing the resist 5, the portion of the conductor film 3 not covered with the gate electrode 6
Is oxidized and converted into an insulator to become an insulating film 7. The insulating film 7 is partially etched by a contact hole etching in a later step as needed. In this way, the gate electrodes 6 are electrically isolated from each other.

In this embodiment, as described above, since the conductor film made of the TiN or TiC film is provided below the polysilicon film, the occurrence of notches can be avoided and the gate electrode can be miniaturized. You can

Next, the results obtained by actually forming the gate electrode according to the above-mentioned embodiment and examining the presence or absence of the notch will be described.

First, a conductor film 3 made of TiN was formed on the gate oxide film 2 to a thickness of about 100 Å. Then, a polysilicon film 4 having a thickness of 1.0 μm was formed on the conductor film 3. Next, a resist 5 was selectively formed on the polysilicon film 4. The pattern width of the resist 5 is 0.3 μm.

Next, the polysilicon film 4 was overetched by 100% by a high density plasma etching method. As a result, the polysilicon film other than the region covered with the resist 5 was removed to obtain the gate electrode 6. The etching condition at this time is that the etching rate is 4500.
Å / minute. In addition, the selection ratio (T
Etching amount of polysilicon for iN conductor film 1)
Is thirty.

Then, the resist 5 was removed. In this resist removal process, TiN in the portion not covered with the gate electrode 6 was oxidized to become an insulator, and the insulating film 7 was formed.

With respect to the gate electrode thus formed, the presence or absence of a notch was examined. As a result, no notch was observed, and a gate electrode having a desired shape could be obtained. Further, when the insulating property of the insulating film 7 was examined, it was found to be good insulating property.

The TiN film formed in this embodiment also has the function of preventing the diffusion of impurities. Also, this T
Since the iN film becomes a TiO-based compound having a high dielectric constant by oxidation, it can be used as a dielectric of a DRAM capacitor, for example. Further, when it is not preferable that the high-dielectric insulator remains on the gate oxide film by oxidizing the TiN film, the TiN film may be removed by an aqueous solution chemical reaction. Furthermore, as the conductor film, Ti
Instead of the N film, another conductive ceramic film may be formed.

Furthermore, a conductive resist may be used as the resist. Also in this case, the same effect as that of the above-described embodiment can be obtained.

[0041]

As described above, the MOS according to the present invention
In the method of forming the gate electrode of the field effect transistor, since a base film made of a conductor is formed on the gate oxide film and a polysilicon film is formed on this base film, the occurrence of notches is avoided even if the gate electrode is miniaturized. can do. Therefore, the present invention can improve the manufacturing yield of miniaturized MOS field effect transistors, and is extremely useful for high integration of MOS field effect transistors.

[Brief description of drawings]

1A to 1D are MOs according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of forming the gate electrode of the S-type field effect transistor in the order of steps.

FIG. 2 is a cross-sectional view showing a conventional MOS type field effect transistor having an LDD structure.

FIG. 3 is a cross-sectional view showing a method of forming a gate electrode of a conventional MOS field effect transistor.

FIG. 4 is a schematic diagram showing a conventional problem.

FIG. 5 is a schematic cross-sectional view showing a gate processing evaluation sample.

FIG. 6 is a schematic cross-sectional view showing an example of a notch generation state.

FIG. 7 is a schematic cross-sectional view showing another example of a notch generation state.

8A to 8C are schematic diagrams showing how notches are generated.

FIG. 9 is a graph showing the temperature dependence of the notch ratio.

FIG. 10 is a schematic diagram showing the repulsive force of static electricity received by ions from a charged region generated in a gate oxide film.

FIG. 11 is a schematic diagram showing a horizontal force received by ions.

[Explanation of symbols]

 1, 11; semiconductor substrate 2, 15; gate oxide film 3; conductor film 4, 16a; polysilicon film 5, 20; resist 6, 16; gate electrode 7; insulating film 12; field oxide film 13; source region 14 Drain region 22; charged region 23; electron 24; ion

Front page continuation (72) Inventor Takashi Kinoshita 1-5-5 Takatsukadai, Nishi-ku, Kobe-shi, Hyogo Kobe Steel Works, Ltd. Kobe Research Institute

Claims (3)

[Claims] 1. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a base film made of a conductor having a greater chemical bonding force than polysilicon on the gate oxide film, A step of forming a polysilicon film on the ground film, a step of forming a resist on the polysilicon film in a predetermined pattern, and a step of performing dry etching to leave the polysilicon film only under the resist and to remove other regions. And a step of removing the polysilicon film. A method of forming a gate electrode of a MOS field effect transistor. 2. The method for forming a gate electrode of a MOS field effect transistor according to claim 1, wherein the base film is made of TiN. 3. The method of forming a gate electrode of a MOS field effect transistor according to claim 1, wherein the base film is made of TiC.