JPH0714982A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a high-performance and high-density large scale integrated circuit device with excellent yield by accurately aligning and laminating semiconductor layers whereupon a plurality of semiconductor integrated circuits are formed. CONSTITUTION:A semiconductor integrated circuit device layer is formed by laminating a flat quartz substrate 30, which permeates ultraviolet rays, on the major surface of the semiconductor integrated circuit device formed on a semiconductor substrate with adhesive 20 and by thinning the layer. The thin layer and a separately prepared semiconductor substrate 11 mounted with a semiconductor integrated circuit device are aligned and laminated by high- accuracy using ultraviolet rays. An aligning device provided with a mechanism which corrects pattern deformation caused by film forming process, etc., in the whole area of the semiconductor substrate and allows correct aligning is used. After the second lamination, the first adhesive is melted so as to release the quartz substrate and a laminated semiconductor integrated circuit device is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor integrated circuit device using an SOI (silicon on insulator) substrate, a method of manufacturing the same, and a manufacturing apparatus thereof.

[0002]

2. Description of the Related Art An insulating film is formed on a single crystal semiconductor substrate on which a semiconductor device is formed, an amorphous semiconductor thin film is deposited through the insulating film, and the semiconductor substrate is used as a crystal nucleus by laser annealing or the like. A method for producing a semiconductor device on the semiconductor thin film after monocrystallizing the semiconductor thin film is disclosed in JP-A-62-
No. 203359. FIG. 27 shows a sectional view of a semiconductor device manufactured by this method. In the figure, if single crystallization of the second semiconductor integrated circuit layer 202 can be realized in the entire region, a laminated structure semiconductor device having an ideal structure as a semiconductor device can be manufactured. The advantage of the above method is that it is possible to manufacture a semiconductor device on the second semiconductor integrated circuit layer 202 by matching with the first semiconductor integrated circuit layer 201 and to form an interlayer wiring 205 with the first semiconductor integrated circuit layer 201. However, the structure is suitable for miniaturization. Here, 203 is an insulating layer, 211 is a first wiring layer,
221 is a wiring layer of the second layer, 212 is an active region of the first layer,
222 denotes an active region of the second layer, and 213 denotes a gate electrode of the first layer.

However, in the method of performing single crystallization by irradiating the amorphous film with laser or electron beam, the single crystallization is limited to the very vicinity of the crystal nucleus region, and the single crystal on the insulating film 203 separated from the crystal nucleus region. The second semiconductor integrated circuit layer 202 is only polycrystallized, and a large-scale and high-performance semiconductor device is
It is difficult to manufacture all over the semiconductor integrated circuit layer 202. Further, in the above method, not only the recrystallization heat treatment for the second semiconductor integrated circuit layer 202 but also the high temperature heat treatment for manufacturing the semiconductor device for the second semiconductor integrated circuit layer 202 is performed for the first semiconductor integrated circuit layer 201. It is inevitable that it will be given. Therefore, it becomes difficult to keep the diffusion layer impurity distribution in the first semiconductor integrated circuit layer 201 as steep, and an ultrafine semiconductor device is provided in the first semiconductor integrated circuit layer 20.
It is difficult to configure it as 1. The above-mentioned drawback is the biggest problem in satisfying the requirement of stacking for the purpose of increasing the capacity of elements having the same access speed, which is not so large in power consumption as the memory cell array. In order to configure the access speeds of the stacked semiconductor devices to be the same, it is necessary that the stacked semiconductor devices are manufactured under the same heat treatment condition as well as the element shape and have the same characteristics. The circuit layer 201 is inevitably subjected to an extra high temperature heat treatment process.

In order to secure the crystallinity of the semiconductor thin film, two single crystal semiconductor substrates having a semiconductor device or a semiconductor integrated circuit device are bonded and one of them is thinned by polishing or the like. Hayashi et al. "Y. Hayashi, et al.," Fabrication of
Three-Dimensional IC Using Cumulatively Bonded IC
(CUBIC) Technology "1990 Symposium on VLSI Tech.,
p 95 (1990)). A cross-sectional view of a semiconductor device manufactured by this method is shown in FIG. In FIG. 1, 2 is an element isolation insulating film, 90 to 92 are electrodes connected to a semiconductor device, and 94 and 95 are surface protective insulating films. The insulating adhesives 96 and 99, their openings 97, and the metal pool 93 are formed on the second semiconductor substrate 101 side, and the metal bumps 98 are formed on the first semiconductor substrate 100 side.

[0005]

In the above-mentioned prior art, the first semiconductor substrate 100 and the second semiconductor substrate 101 are used.
The semiconductor device configured in each of the above is electrically connected by the metal pool 93 and the metal bump 98, but the semiconductor substrate 100 or 101 used for manufacturing the semiconductor device is 500 μm.
Since the thickness of m or more and the thickness that is too thick to transmit ultraviolet or visible light, the alignment between the opening 97 and the metal bump 98 has a longer wavelength, and infrared rays that can pass through the semiconductor substrate have been used. Therefore, there is a problem in alignment accuracy, and it is difficult to align a pattern of several μm or less. That is, it is impossible from the viewpoint of commercialization to aim at the pattern-to-pattern connection of 1 μm or less, as in the case of stacking ultra-highly integrated high-density semiconductor devices.

An object of the present invention is to provide a high-performance and ultra-high-density integrated circuit device at a high yield and at a low price. Another object of the present invention is to provide a semiconductor device manufacturing method capable of dramatically improving alignment accuracy in semiconductor device manufacturing and stacking large-scale semiconductor integrated circuit layers in the vertical direction with ultra-high accuracy. It is to be. Another object of the present invention is SOI.
An object of the present invention is to provide a substrate bonding apparatus capable of aligning a substrate with a precision of 10 to 100 times that of a conventional one.

[0007]

The above objects are achieved by the following. A first semiconductor integrated circuit device manufactured by the first
This semiconductor substrate is bonded to another substrate using the first adhesive. The first semiconductor substrate is thinned from the back surface side by grinding and polishing to form a first semiconductor integrated circuit device layer, which is bonded to a transparent quartz substrate using a second adhesive. From this state, only the first adhesive is dissolved in the solvent of the first adhesive to transfer the first semiconductor integrated circuit device layer to the transparent quartz substrate. The first semiconductor integrated circuit device layer is strictly aligned with the second semiconductor integrated circuit device or the semiconductor integrated circuit device layer, which is separately manufactured, and is bonded using the third adhesive. In the above alignment, if the first semiconductor integrated circuit device layer is made thin enough to have a thickness of several μm or less, the quartz substrate has a transmittance of 50% or more with respect to ultraviolet rays, and since the quartz substrate can sufficiently transmit the ultraviolet rays, It is possible to use a high precision mask aligning device. The solvent for the second adhesive may be made of a material that does not dissolve the third adhesive.

What must be taken into consideration when adhering the thinned semiconductor integrated circuit device layer to another semiconductor integrated circuit device or a semiconductor integrated circuit device layer is that the film formation in the film is caused by continuous film formation on the semiconductor substrate. 10c for intrinsic and thermal stress
About 1 μm per m, a large distortion from the initial pattern,
This is to make precise alignment between semiconductor integrated circuit devices difficult. In order to correct the above pattern distortion and perform precise alignment and adhesion, the first method of the present invention is to apply an external force to one or both substrates to which the semiconductor integrated circuit device to be aligned is adhered. Then, the method of correcting the distortion was used. As another method, a method of adhering semiconductor integrated circuit devices having the same film-forming structure as the sectional structure is adopted. In this case, the amount of strain generated by film formation is the same in any semiconductor integrated circuit device, and the misalignment due to strain is eliminated. When the semiconductor integrated circuit device layers adhered by the above method were further adhered, the cross-sectional structures of the respective layers to be adhered were made the same.

[0009]

According to the present invention, a high-precision mask alignment device using an ultraviolet light source can be used as in the case of manufacturing an ultra-fine semiconductor integrated circuit device, so that it is as high as a conventional semiconductor integrated circuit device. It is possible to stack semiconductor integrated circuit devices with high accuracy. Therefore, by using the method of the present invention, it is possible to realize a semiconductor integrated circuit device having a higher degree of integration with the conventional semiconductor device manufacturing apparatus. Here, since the manufacturing process can be divided and only the good semiconductor layers can be laminated to complete the semiconductor integrated circuit device, manufacturing defects can be significantly reduced as compared with the conventional integrated manufacturing. That is, it is possible to provide a highly integrated semiconductor integrated circuit device at a low price. Further, since it is possible to separately configure the constituent elements of the semiconductor integrated circuit device in each of the semiconductor layers to be stacked and to complete the integrated semiconductor device by stacking, it is possible to make each semiconductor layer in advance. It is possible to laminate in a desired combination at a desired time. Therefore,
It will be possible to quickly respond to demand. Further, as in the case of application to the complementary transistor, it is possible to omit the steps such as the semiconductor layer conduction type location conversion, and the number of manufacturing steps can be reduced. According to the present invention, in stacking semiconductor integrated circuit devices having the same semiconductor device region, even if there is a defective semiconductor device portion, the defective portion is deselected,
By selecting a semiconductor device portion on another layer, it can be operated as a good semiconductor integrated circuit device. That is, the decrease in the yield of non-defective products, which increases as the area of the semiconductor integrated circuit device increases, can be greatly improved by the stacked structure. Others According to the present invention, the constituent elements can be completely separated, and the parasitic bipolar effect in the complementary transistor, that is, the interference between adjacent elements such as a latch-up phenomenon and the malfunction such as malfunction due to α-ray irradiation are almost completely eliminated. Can be resolved. According to the present invention, a plurality of semiconductor integrated circuit devices having the same characteristics can be stacked by using the same heat treatment process to increase the capacity.

[0010]

EXAMPLES The present invention will now be described in more detail with reference to examples. For convenience of description, the description will be made with reference to the drawings, but attention must be paid because the main part is shown enlarged. In order to simplify the description, the material of each part, the conductivity type of the semiconductor layer, and the manufacturing conditions will be defined and described, but the present invention is not limited to the material, the conductivity type of the semiconductor layer, and the manufacturing conditions. Of course.

(Embodiment 1) FIGS. 2 to 5 are sectional views showing a first embodiment of a semiconductor integrated circuit device according to the present invention in the order of manufacturing steps. Plane orientation (100), resistivity 50Ωc
m, diameter 12.5 cm, p conductive type single crystal silicon (Si) substrate 200 using a known method on the main surface of 200 n
An m-thick thermal oxide film was selectively formed at a desired location to form the element isolation insulating film 2. Then, 6 on the substrate surface of the desired active region
A gate insulating film 3 having a thickness of nm is formed to form a gate insulating film 3 and then the gate insulating film in a desired region is selectively removed. 9 was formed. Further, the N-type low resistance diffusion layers 6, 7 and 8 were formed using the gate electrode 4 as a mask, and then the electrode protective insulating film 10 was deposited over the entire surface (FIG. 2).

The wax 20 melted from the state shown in FIG. 2 is applied on the entire surface of the electrode protection insulating film 10 to form a transparent quartz substrate 30.
Glued to. Then, the back side of the Si substrate 1 is ground to a thickness of 10 μm by a high precision grinding machine, and further mechanical / chemical polishing is performed to thin the Si substrate 1 to the surface defined by the back surface of the element isolation insulating film 2. Let For the polishing, a Si substrate is placed on a polishing cloth provided on a rotating disk and the substrate is 1.9 × 10 ⁴ Pa.
The polishing was performed while supplying the polishing liquid to which ethylenediamine / pyrocatechol was added under the pressure of, and the polishing speed of the inter-element isolation insulating film 2 exposed as the polishing progressed was S
It was much slower than i and was 1/10 ⁴ times or less. Therefore, the single-crystal Si substrate 1 is completely flattened by the above polishing, and the single-crystal Si substrate 1 is insulated from each other by the element isolation insulating film 2.
A single crystal ultra-thin film Si having a thickness of 0 nm was obtained. After that, a protective insulating film 16 was formed on the polished surface (FIG. 3).

In the state shown in FIG. 3, the main surface of the second Si substrate 11 prepared separately up to the state shown in FIG. 2 and the protective insulating film 16 are accurately positioned by using an aligning device described later. After the matching, a fluorine-based resin was bonded as the adhesive layer 21. The thickness of the adhesive layer 21 was about 2 μm.
After that, the second Si substrate 11 was heated to 100 ° C. to dissolve the wax 20, peeled from the quartz substrate 30, and the remaining wax was washed and removed with acetone. The above wax removing step has no influence on the adhesive layer 21 made of a fluororesin (FIG. 4).

From this state, the terminal electrode 9 formed on the ultrathin Si layer 1, the element isolation insulating film 2, the adhesive layer 21, and the S
The Si substrate 1 is penetrated through the electrode protection insulating film and the like on the i substrate 11.
The connection wiring 17 was formed by providing an opening reaching the terminal electrode 15 on the first electrode and then depositing a selective metal in the opening. Further, the wiring 18 based on the desired circuit configuration is provided to complete the semiconductor integrated circuit device (FIG. 5).

In the semiconductor integrated circuit device manufactured according to the above-described manufacturing method, the alignment accuracy between the semiconductor layers formed is ± as compared with the conventional stacked semiconductor integrated circuit device.
It could be improved to 0.5 μm, which is 10 times. As a result, the opening width is 0.5 μm and the width of the terminal electrode 15 is 1.5 μm.
Since the layers can be connected by μm, the area required for forming bumps and pools for connecting the layers is not needed, and the basic circuit unit can be directly integrated in the stacking direction to achieve high integration. We were able to greatly improve the degree of freedom in design. The dramatic improvement in the alignment accuracy in the stacking direction in this embodiment is achieved by highly accurate alignment with the underlying semiconductor integrated circuit device to be bonded because the transparent semiconductor integrated circuit device layer made of an ultrathin film and transparent quartz can transmit ultraviolet rays. Based on what is possible.

As the semiconductor integrated circuit device according to the present embodiment, the semiconductor integrated circuit device layers made of the memory cell array were laminated. Each semiconductor integrated circuit device layer was manufactured by the same heat treatment manufacturing process, and the access speed etc. The same characteristics can be obtained regardless of the layers, and the operation by improving the non-defective rate and shortening the maximum wiring length compared to the conventional semiconductor integrated circuit device in which the memory cell array of the same capacity is formed on the same plane. Speed improvements have been achieved.

The transmission delay time can be used as a general characteristic of the semiconductor integrated circuit device.

(Embodiment 2) FIGS. 6 to 8 show a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the semiconductor integrated circuit device according to the example in the order of manufacturing steps. On the Si substrate 1 manufactured up to the electrode protection insulating film 10 according to the first embodiment, polycrystalline Si having a thickness of 3 μm is formed.
After the film 22 is deposited, its surface has a mean square roughness of 0.3.
Mechanical polishing was performed so that the thickness became less than nm, and the surface was flattened.
From this state, the transparent quartz plate 30 is adhered to the transparent quartz plate 30 by the melted wax 20 according to the first embodiment, and the back surface of the Si substrate 1 is thinned to form a single crystal ultra-thin film Si defined on the back surface of the inter-element isolation insulating film 2. The protective insulating film 12 was formed on the back surface (FIG. 6).

In the state of FIG. 6, the main surface of the single-crystal Si substrate 11 and the protective insulating film 12 which are separately manufactured up to the deposition of the thick polycrystalline Si film 24 and the flattening polishing of the surface by the same manufacturing method as in FIG. After performing accurate alignment using the alignment device described later, a fluororesin was bonded as the adhesive layer 23. The thickness of the adhesive layer 23 was about 0.5 μm (FIG. 7).

Thereafter, the second Si substrate 11 is heated to 100 ° C.
Then, the wax 20 was melted and peeled from the quartz substrate 30, and the remaining wax was removed by washing with acetone and the polycrystalline Si film 22 was selectively etched. The above wax removing step has no influence on the adhesive layer 23 made of a fluororesin. Next, on the electrode wiring 9 formed on the single crystal ultra-thin film Si layer 1, the electrode wiring 9 and the adhesive layer 2 are formed.
3 and penetrates the electrode protective insulating film and the like on the Si substrate 11,
The connection wiring 17 is formed by providing an opening reaching the electrode wiring 15 on the Si substrate 11, performing insulation treatment on the side wall of the opening, and then depositing and patterning a metal film on the opening. . Further, the wiring 18 based on the desired circuit configuration is provided to complete the semiconductor integrated circuit device (FIG. 8).

In the semiconductor integrated circuit device manufactured based on the above manufacturing method, the alignment accuracy between the semiconductor layers formed is ±± compared with the conventional stacked semiconductor integrated circuit device.
It could be improved to 0.3 μm, which is 20 times. As a result, it is possible to connect the layers with an opening width of 0.4 μm and a width of the electrode wirings 15 and 17 of 1.0 μm, and a region for forming the bump and the pool for the interlayer connection is not required. The basic circuit unit can be highly integrated to the extent that it can be directly constructed in the stacking direction, and the degree of freedom in circuit design can be greatly improved. The dramatic improvement in the alignment accuracy in the stacking direction in this embodiment is achieved by highly accurate alignment with the underlying semiconductor integrated circuit device to be bonded because the transparent semiconductor integrated circuit device layer made of an ultrathin film and transparent quartz can transmit ultraviolet rays. Based on what is possible. Further, the alignment accuracy can be further improved as compared with the case of the first embodiment, because the unevenness of the surfaces to be bonded is extremely flattened, and thus the adhesive layer 2
It is considered that the lamination was possible without generating bubbles even when 3 was made thin.

(Embodiment 3) FIGS. 9 to 11 are sectional views showing a semiconductor integrated circuit device according to a third embodiment of the present invention in the order of manufacturing steps. A single-crystal Si substrate 1 on which the surface of the thick polycrystalline Si film 24 has been flattened and polished according to the second embodiment is prepared separately with a wax 25.
Pasted on. After that, the single crystal Si substrate 1 was thinned from the back surface side, and an ultrathin film single crystal Si layer was formed based on Example 1 so that the film thickness was defined on the back surface of the element isolation insulating film 2 (FIG. 9). .

Ultra-thin film single crystal Si manufactured up to the state of FIG.
A polyvinyl alcohol film 26, which is a water-soluble adhesive, was applied to the back side of the layer 1 and attached to a transparent quartz substrate 30. After that, the mirror surface Si substrate 40 was heated to 100 ° C., the wax 25 was melted and peeled from the quartz substrate 30, and the remaining wax was washed and removed with acetone. The polyvinyl alcohol film 26 is not affected by the acetone cleaning (FIG. 10).

A separately prepared single crystal S obtained by performing flattening polishing on the surface of the thick polycrystalline Si film 27 according to the second embodiment.
The i substrate 11 was directly bonded to the ultrathin film single crystal Si layer 1 in the state of FIG. 10 and the polycrystalline Si surfaces. In the above-mentioned bonding, the mutual alignment was carried out on the basis of the precision alignment device described later as in the second embodiment. The single crystal Si substrate 1
1 is an N-type low resistance diffusion layer 6 based on the first embodiment,
7 and 8 were formed in advance. After the above direct bonding,
By immersing the single crystal Si substrate 11 in water, the water-soluble adhesive 26 was dissolved and separated from the transparent quartz substrate 30, and heat treatment for improving adhesive strength was performed at 900 ° C. for 30 minutes. After that, a gate insulating film was formed on the surface of the single crystal ultra-thin film Si layer 1, and then a hole was formed in the inter-element isolation insulating film 2 having the gate electrode 4 extended. Further, the second gate electrode 13 is formed into a single crystal ultra-thin film Si so as to match the gate electrode 4.
The low resistance diffusion layers 61, 62 and 63 were formed on the layer 1 and using the second gate electrode 13 as a mask. Next, on the electrode wiring 9 formed in the single crystal ultra-thin film Si layer 1,
Electrode wiring 9, polycrystalline Si layers 24 and 27, and Si substrate 11
After forming an opening penetrating the upper electrode protection insulating film and the like and reaching the electrode wiring 15 on the Si substrate 11, the side wall of the opening is insulated, and a metal film is deposited and a pattern is formed in the opening. By doing so, the connection wiring 17 was formed. Furthermore, the wiring 18 and the electrode protection insulating film 10 based on the desired circuit configuration
To form a semiconductor integrated circuit device (see FIG. 1).
1).

In the semiconductor integrated circuit device manufactured according to the above-described manufacturing method, the alignment accuracy between the semiconductor layers formed is ± as compared with the conventional stacked semiconductor integrated circuit device.
It could be improved to 0.3 μm, which is 20 times. As a result, the basic circuit units can be highly integrated to the extent that they can be directly configured in the stacking direction without the need for the areas required for forming bumps and pools for interlayer connection, and the degree of freedom in circuit design is greatly increased. I was able to improve. The dramatic improvement in the alignment accuracy in the stacking direction in this embodiment is achieved by highly accurate alignment with the underlying semiconductor integrated circuit device to be bonded because the transparent semiconductor integrated circuit device layer made of an ultrathin film and transparent quartz can transmit ultraviolet rays. Based on what is possible.

Further, in the semiconductor integrated circuit device according to the present embodiment, since the method of directly laminating without using an adhesive is used, the gate electrode 13 and the diffusion layer 61 are laminated after lamination.
To 63 and the like can be manufactured. Therefore, the stacked semiconductor integrated circuit device layers can be configured such that current control is performed from above and below the ultra-thin Si layer, and the current becomes three times larger than that of the conventional structure transistor structure, that is, the speed is increased in the vertical direction. It became possible together with integration.

(Embodiment 4) FIG. 12 is a sectional view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. In Example 3, instead of the semiconductor substrate 11 to which the semiconductor integrated circuit device layer 1 was to be bonded, the ultrathin semiconductor integrated circuit device layer 1 manufactured according to the method described in Example 3 was directly bonded. The semiconductor substrate 31 was used. In the semiconductor integrated circuit device layer 1, the gate electrode 19 and other electrodes are preconfigured. In FIG. 9, the mirror surface Si substrate 40 and the single crystal Si substrate 1 are bonded by the wax 25. However, in the semiconductor integrated circuit device of this embodiment, the main surface of the mirror surface Si substrate 31 having the thermal oxide film 29 formed on the main surface. And single crystal S
It was directly bonded to the surface of the flattened and polished polycrystalline Si film 28 on the i substrate 1 without an adhesive. After that, heat treatment for improving the adhesive strength is performed at 900 ° C. for 30 minutes, and then thinned from the back surface side of the single crystal Si substrate 1 to form the inter-element isolation insulating film 2
A semiconductor integrated circuit device layer 1 whose thickness is regulated on the bottom surface was formed. Thereafter, a gate insulating film is formed on the new main surface of the semiconductor integrated circuit device layer 1 and an opening is formed at a desired position in the element isolation insulating film 2 region, and then the electrodes including the gate electrode 5 and the gate electrode 5 are formed. A low resistance diffusion layer was formed by self-alignment. Subsequently, an electrode protection insulating film and a thick polycrystalline Si film were deposited on the entire surface, and the surface of the polycrystalline Si film was polished flat. A separately prepared ultra-thin film semiconductor integrated circuit device including the polycrystalline Si film surface on the semiconductor substrate 31 manufactured based on the above-described method and the gate electrode 4 and the like on the quartz substrate 30 with polyvinyl alcohol bonded as the adhesive 26. The polycrystalline Si surface in layer 1 (FIG. 10) was directly bonded without an adhesive. In the above-mentioned bonding step, the alignment between the ultrathin film semiconductor integrated circuit device layers was carried out by using a precision alignment device described later as in the second or third embodiment. After the bonding step is completed, the transparent quartz plate 30 is separated by removing the adhesive 26 with polyvinyl alcohol, heat treatment for improving the adhesive strength,
Further, the second gate electrode 13, the diffusion layer and the like were formed on the bonded single crystal ultra-thin film Si layer according to the third embodiment. From this state, the single-crystal ultra-thin film S that has been embedded by penetrating the diffusion layer formed in the single-crystal ultra-thin film Si layer exposed on the main surface and the polycrystalline Si layer formed at the bottom of the diffusion layer
Apertures were made to reach the electrodes on the i-layer. Finally polycrystalline Si
After the insulating treatment on the side surface, a semiconductor integrated circuit device was completed by selectively forming a metal film in the opening, forming a wiring based on a desired circuit configuration, and an electrode protective insulating film (FIG. 12).

In the semiconductor integrated circuit device manufactured by the above-described manufacturing method, the alignment accuracy between the semiconductor layers formed in comparison with the conventional stacked semiconductor integrated circuit device is similar to that of the semiconductor integrated circuit device according to the third embodiment. Can be improved by 20 times or more, and the area required for forming bumps and pools for interlayer connection can be reduced. As a result, it was possible to achieve a high degree of integration before the basic circuit units could be formed in the stacking direction, and the degree of freedom in circuit design could be greatly improved. The dramatic improvement in the alignment accuracy in the stacking direction in this embodiment is achieved by highly accurate alignment with the underlying semiconductor integrated circuit device to be bonded because the transparent semiconductor integrated circuit device layer made of an ultrathin film and the transparent quartz substrate can emit ultraviolet rays. Based on the fact that

Further, in the semiconductor integrated circuit device according to this embodiment, since all the laminated semiconductor integrated circuit device layers are formed by direct bonding without using an adhesive, a structure requiring high temperature heat treatment such as diffusion layer formation. Can be performed after the laminating step. As a result, it becomes possible to form gate electrodes for current control on the upper and lower sides of the semiconductor layer in any of the layers of the laminated semiconductor integrated circuit device, and the operation speed is higher than that of the semiconductor integrated circuit device of the third embodiment. Was realized. That is, as compared with the semiconductor integrated circuit device having the conventional structure, super-high integration and super-high speed by stacking can be realized at the same time.

(Fifth Embodiment) FIG. 13 is a sectional view showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention. Regarding the formation of the ultrathin film semiconductor integrated circuit device layer 1 to be directly bonded to the semiconductor substrate 31 in the fourth embodiment, the ground potential is set prior to the deposition of the polycrystalline Si film 28 forming the bonding surface with the semiconductor substrate 31. After forming a desired opening in the electrode protective insulating film on the terminal portion 7 to be applied, a first laminated film 42 of a low resistance polycrystalline Si film and a tungsten (W) silicide film is formed on the entire surface.
Was formed. Then, after depositing the second electrode protection insulating film on the entire surface, the deposition of the polycrystalline Si film 28 and its flattening polishing and the like were performed according to the fourth embodiment. In addition, the above-mentioned Example 4
After forming the gate electrode 13 in the manufacturing process of 1., when forming an opening penetrating the upper ultra-thin film semiconductor integrated circuit device layer, a base is formed in a terminal portion to which a ground potential is applied in the upper ultra-thin film semiconductor integrated circuit device layer. An opening reaching the laminated film 42 was formed by penetrating the ultra-thin semiconductor integrated circuit device layer and the connecting metal film was embedded in the opening. Further, the above-mentioned Example 4
In the manufacturing process of step 1, after depositing the electrode protection insulating film 41 on the main surface of the upper ultra-thin film semiconductor integrated circuit device layer, the desired terminal portion 62 of the upper and lower ultra-thin film semiconductor integrated circuit device layers to which the power supply potential should be applied. Then, a second laminated film 43 of a low resistance polycrystalline Si film and a tungsten (W) silicide film was formed again on the entire surface. Finally, the first and second laminated films,
42 and 43 were connected at desired locations so that the ground potential and the power source potential were applied respectively (FIG. 13).

The semiconductor integrated circuit device manufactured by the above manufacturing method also has the features of ultra-high integration and ultra-high speed in the stacking direction of the semiconductor integrated circuit device according to the fourth embodiment. Further, in the semiconductor integrated circuit device according to the present embodiment, higher speed operation can be realized as compared with the fourth embodiment. In the semiconductor integrated circuit device of this embodiment, any of the power supply voltage applying terminals and the ground potential applying terminals on the chip are connected to a conductor layer formed in a planar shape over the entire upper and lower portions of the semiconductor integrated circuit device layer. There is. As a result, the ground resistance and the power supply resistance are defined by the layer resistance from the voltage supply point to each terminal, and the wiring is based on the effective length and width of the routed wiring from the voltage supply point to each terminal as in the conventional semiconductor integrated circuit device. The ground resistance and the power supply resistance were significantly reduced compared to the case where the resistance was specified. The effect of reducing the ground resistance and the power supply resistance is more effective as the area occupied by the semiconductor integrated circuit device increases.

(Sixth Embodiment) In the fifth embodiment, only the N-channel type MOS transistor is provided in the ultrathin film semiconductor integrated circuit device layer directly bonded to the semiconductor substrate 31 via the polycrystalline Si film 28, and the ultrathin film is used. An ultra thin film semiconductor integrated circuit device layer formed by stacking layers on the semiconductor integrated circuit device layer has only P-channel type MOS transistors, and a semiconductor integrated circuit device having complementary type MOS transistors is manufactured in a stacked structure. Reference numeral 7 is a ground potential application terminal, and 62 is a power supply potential application terminal. N for complementary MOS transistor
The connection between the channel and the P-channel transistor was made by the interlayer connection wiring 17 between the ultrathin films.

In the semiconductor integrated circuit device manufactured according to the above manufacturing method, the N-channel type MOS transistor and the P-channel type MOS transistor are formed in separate ultra thin films, and therefore, like the conventional complementary MOS transistor configuration. A manufacturing process that separates the semiconductor substrate into regions (referred to as well regions) where transistors of each conductivity type are formed, and an occupied region for that are reduced, so that manufacturing cost is reduced and higher integration is realized. did it. In addition, since transistors of different conductivity types are completely separated by layers, mutual interference between adjacent elements such as latch-up phenomenon is completely eliminated.

(Embodiment 7) FIGS. 14 to 15 are sectional views showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention in the order of manufacturing steps. A groove having a desired pattern shape is formed from the main surface side of the P-type low-resistance Si substrate 31, a thin insulating film 32 is formed on the side wall of the groove by thermal oxidation, and then a low impurity-doped layer is filled in to fill the groove. Polycrystalline Si film 3 for resistance
3 was deposited on the entire surface. After that, mechanical polishing is performed so that the main surface becomes flat and the polycrystalline Si film 33 region is made into Si.
It was separated from the substrate 31 (FIG. 14).

Here, an inter-element isolation insulating film, gate electrodes 46 and 47, an N-type low resistance diffusion layer, an electrode protective insulating film and the like having a desired circuit configuration are formed on a separately prepared P conductivity type single crystal Si substrate 1. Then, according to the first embodiment, the ultrathin single crystal semiconductor integrated circuit device layer 1 having the film thickness defined on the bottom surface of the element isolation insulating film was formed. The Si substrate 31 in which the above ultra thin film is manufactured up to FIG. 14 based on the first embodiment
And glued to the base for precise alignment. Adhesion was performed by using a fluorocarbon resin coating film as the adhesive 34. Then, after removing the transparent quartz substrate used for alignment, a hole is formed in the ultrathin film Si layer in the desired diffusion layer region and the adhesive layer 34 immediately below,
An electrode 49 for electrically connecting the separated polycrystalline Si film 33 and the desired diffusion layer region was formed. Next, an electrode protection insulating film is deposited on the entire surface, and then an opening for connecting to the desired diffusion layer region 48 and a wiring electrode 14 forming a bit line are formed, and one capacitance element and one transistor are used as a basic unit. A semiconductor memory device is formed (FIG. 15).

In the semiconductor integrated circuit device manufactured according to the above manufacturing method, the semiconductor substrate including the capacitive element and the semiconductor substrate including the control transistor are separately manufactured and then integrated by bonding. Therefore, restrictions on the manufacturing process and the layout in manufacturing the capacitive element are significantly eased. Therefore, since the depth of the groove formed in the Si substrate 31 and the groove area that can be extended to the bottom surface of the transistor can be set to desired values, a sufficiently large capacitance value can be realized in the storage capacitor element portion. As a result, the malfunction caused by the α-ray irradiation can be remarkably eliminated.

(Embodiment 8) FIG. 16 is a sectional view showing a semiconductor integrated circuit device according to an eighth embodiment of the present invention. In the present embodiment, the thermal oxide film 36 and the thermal oxide film 3 are used instead of the Si substrate 31 which constitutes the capacitive element in the seventh embodiment.
6, a semiconductor substrate 35 having a main surface formed with a refractory metal silicide film 37 patterned according to the desired circuit configuration and a low resistance polycrystalline Si film 38 entirely deposited on the refractory metal silicide film. Was used. If desired, the refractory metal silicide film 37 may be entirely formed without patterning. Here, the groove for the capacitive element was formed in the region of the polycrystalline Si film 38, and after forming the thin insulating film on the processed surface thereof, the low resistance polycrystalline Si film 33 was embedded in the region of the groove. After that, the polycrystalline Si films 33, 36, etc. on the main surface of the semiconductor substrate 35 are planarized by mechanical polishing, and then the planarized surface and the ultrathin Si layer are adhered to each other according to the seventh embodiment, and the subsequent fabrication. The process was continued to manufacture a semiconductor integrated circuit device (FIG. 16).

In the semiconductor integrated circuit device manufactured by the above manufacturing method, the polycrystalline Si film 38 forming one electrode of the capacitive element is electrically connected to the refractory metal silicide film 37 having a lower resistance. , For the application of plate potential,
I was able to follow faster. As a result, the memory read / write speed can be further increased as compared with the semiconductor integrated circuit device of the seventh embodiment.

(Embodiment 9) FIG. 17 is a sectional view showing a semiconductor integrated circuit device according to a ninth embodiment of the present invention. In this embodiment, a semiconductor integrated circuit device having a multi-layer structure is manufactured by repeating stacking of the semiconductor integrated circuit device based on the second embodiment. In FIG. 17, 11 is a semiconductor support substrate, and 50 is a first ultra-thin film Si layer, which constitutes a main memory device. 51, 52 and 53 are second, third and fourth ultrathin films S
Each of the i layers has an extended storage device.

In the semiconductor integrated circuit device according to this embodiment, the increase in the operation processing time due to the wiring delay in the conventional semiconductor integrated circuit device can be greatly reduced due to the vertical high integration effect of the precision alignment multilayer structure. It was

(Embodiment 10) In this embodiment, cache memory devices are used as 51, 52 and 53 of the ninth embodiment. Structure of cache memory device The semiconductor device was an ultra-high speed bipolar transistor. Main memory 50 is M
It is composed of an OS type transistor.

In the semiconductor integrated circuit device according to the present embodiment, since the highly integrated vertical alignment effect of the precision alignment multilayer structure enables instant exchange of stored data between the cache memory device and the main memory device, it has a large capacity. I was able to provide the cash memory of. As a result, the operating speed of the storage device as a whole can be greatly improved and a large amount of information can be stored.

(Embodiment 11) FIG. 18 is a sectional view showing a semiconductor integrated circuit device according to an eleventh embodiment of the present invention. In this embodiment, based on the tenth embodiment, the semiconductor integrated circuit device is repeatedly laminated to manufacture a semiconductor integrated circuit device having a multilayer structure. In FIG. 18, reference numeral 54 is a central processing unit, 50 is a main storage device, 51 to 53 are instruction processors, system control devices, input / output processors, expansion storage devices, etc., which are laminated in a plurality of layers based on the second embodiment. , A semiconductor integrated circuit device that constitutes an ultra-high speed computer.

In the semiconductor integrated circuit device according to the present embodiment, the inter-device connection length is extremely shortened due to the vertical highly integrated effect of the precision alignment multilayer structure. As a result, compared to a conventional large-scale computer that assembles semiconductor devices, etc.
The number of instruction processings per second could be greatly increased.

(Embodiment 12) FIGS. 19 and 20 are sectional views showing a semiconductor integrated circuit device according to a twelfth embodiment of the present invention. FIG. 19 shows the first method of this embodiment, and FIG. 20 shows the second method. FIG. 19 shows a semiconductor integrated circuit device of the present embodiment manufactured by the same manufacturing method as that of the second embodiment, but the semiconductor integrated circuit device layers having the same function are vertically aligned and laminated. Further, a transistor for controlling the current path is arranged in series for each desired unit circuit in each semiconductor integrated circuit device layer. 55 and 56 are gate electrodes of the transistors in the adjacent semiconductor integrated circuit device layers.

In the semiconductor integrated circuit device according to this embodiment, the yield of non-defective products, which is reduced as the area and size of the semiconductor integrated circuit device are increased, can be improved. That is, when a defect occurs in a desired unit circuit in any one of the stacked semiconductor integrated circuit device layers, the path is blocked by a transistor (for example, a transistor controlled by the gate electrode 55) serially connected to the defect circuit. Then, the transistor (for example, the transistor controlled by the gate electrode 56) is made conductive through the connection wiring electrode 17 so that only the path on the desired unit circuit side of a good product is selected. As a result, it is possible to significantly improve the situation in which the yield of non-defective products has been greatly reduced because the semiconductor integrated circuit device was made defective due to the presence of a defective circuit at one location in the past, and a larger area of the semiconductor integrated circuit device can be obtained.・ We were able to open the way to larger scale. It should be noted that the defective portion of each semiconductor integrated circuit device layer is stacked after being confirmed by measurement in advance at the stage of forming each semiconductor integrated circuit device layer.

Another method of this embodiment is the semiconductor integrated circuit device shown in FIG. 20, and the semiconductor integrated circuit device layers having the same function are vertically aligned and laminated according to the fourth embodiment. The difference from the fourth embodiment is that after manufacturing each semiconductor integrated circuit device layer, the defective portion of the desired unit circuit is identified by electrical measurement, and the defective unit circuit (for example, the upper semiconductor integrated circuit device layer in FIG. The current path of the region (1) is broken by melting with a laser beam that is finely squeezed to form an electrically open region 39. As a result, in the semiconductor integrated circuit device of FIG. 20, the current path selects a path on the desired unit circuit side of a non-defective product (for example, the area shown in the lower semiconductor integrated circuit device layer in FIG. 20) via the connection wiring electrode 17. Was realized. That is,
The defective unit circuit portion can be relieved in the same manner as in the case of the other method of the present embodiment whose cross section is shown in FIG. Compared to the semiconductor integrated circuit device shown in FIG. 19, this method does not require an extra transistor required for repairing a defective unit circuit, and therefore, it is possible to prevent the occupied area from increasing, and to increase the area and size of the semiconductor integrated circuit device. It has become possible to further promote the conversion.

(Embodiment 13) FIGS. 21 and 22 are conceptual views showing a semiconductor integrated circuit device manufacturing apparatus according to the present invention. The semiconductor integrated circuit device of each of the above-described embodiments was manufactured using the manufacturing apparatus of this embodiment. In order to accurately align and bond two semiconductor substrates or semiconductor thin films 75 and 76 on which patterns are formed to each other and to bond them to each other, the expansion and contraction and distortion of each semiconductor substrate or semiconductor thin film based on the film formation can be accurately performed. It needs to be corrected to get a good match. In FIG. 21, a second stage 72 and a third stage 73 are arranged on the first stage 71. The substrate 75 was vacuum-adsorbed on the stage 72, and the substrate 76 was vacuum-adsorbed on the stage 73. Each substrate is transported onto the stage while being pre-aligned relative to the stage. The substrate was transferred by using a normal type automatic transfer mechanism. The stage 72 and the stage 73 each have a rotation mechanism, and can be aligned so that the chip arrangement on the substrate is parallel to the movement axis of the stage. Target marks for position recognition are formed on the substrate, and the position detection optical systems 77 and 78 detect the positions of the target marks. In this device, the substrate 76 is aligned with the substrate 75. The relative position error between the substrate 75 and the substrate 76 is measured by the detection optical systems 77 and 78, and if there is a position error, the substrate deforming mechanism on the stage 73 deforms the substrate 76, and the relative position error with the substrate 75 is detected. Control it so that it disappears.
Subdivided substrate suction blocks are arranged on the stage 73, and each block 74 is configured to be independently movable by a piezo element. The position of the substrate is recognized relative to the stage marks 80 and 81. The substrate 75 and the substrate 76 have a mirror-reversed positional relationship, and the positional relationship between the two is processed by the computer control system 83 based on the information from the position recognition section 79. The substrate deformation control mechanism 82 processes the data, moves the subdivided substrate suction block 74, and moves the substrate 76.
Transform. By this operation, the substrate 7
The same shape can be obtained in a state where 6 is mirror-inverted.

In the next step, as shown in FIG. 22, the substrate 75 is fixed to the stage 72, mirror-inverted, and moved so that the main surface of the substrate 76 and the main surface of the substrate 75 face each other. Although the moving mechanism is not shown, a normal arm type moving mechanism is used. In this state, the stage marks 80 and 81
Is detected using the position detection optical system 84. This data is processed by the computer control system 83. This data is processed by the stage position control system 85, and the stage 7
3 is moved by the moving mechanism 86 and positioned relatively to the stage 72. After that, the substrate 72 is lowered by the vertical movement mechanism of the stage 72 and brought into close contact with the substrate 73, whereby the bonding is completed. The stage 72 can be set to have a slight inclination in order to perform good bonding. The substrate 7 having different deformations by the above series of operations
5 and the substrate 76 can be corrected to the same shape and bonded. In the above-described embodiment, the mechanism for deforming the substrate 76 uses the mechanism for moving the subdivided substrate suction block 74 by the piezo element, but it may be based on another method. For example, various methods such as a method of moving the adsorption block 74 by a thermal deformation plate and a method of changing the position by utilizing the pressure of liquid or gas are possible. That is, the feature of this apparatus is that it has a mechanism capable of freely deforming the shape of the substrate. Note that the device is subdivided and described in order to explain the function of the present device, but the features of the manufacturing device according to the present embodiment are the same whether FIGS. 21 and 22 are configured in the same device or in different devices. Although the description of the mechanism that is not directly related to the features of the manufacturing apparatus according to the present embodiment is omitted, the mechanism necessary for the ordinary position alignment apparatus is added. For example, the temperature control mechanism of the entire device,
Examples include a stage position measuring mechanism and a substrate cassette / toe / cassette transport mechanism. As a modification of this device, it is also possible to measure the modification of the chip arrangement from the back surface of the substrate 75 as shown in FIG. When measuring the deformation of the substrate 76, it is necessary to retract the stage 72 to a position that does not interfere with the detection. In this case, the stage 71 of FIG. 21 is unnecessary, and the device can be downsized. The substrate 75 or 76 using the manufacturing apparatus of this embodiment need not be limited to a normal single crystal semiconductor substrate on which a semiconductor integrated circuit device is manufactured, but a semiconductor as a supporting substrate as described in the first embodiment and the like. It may be a semiconductor integrated circuit device layer manufactured on a single crystal ultra-thin film Si film that is bonded onto a substrate with an adhesive. The single crystal ultra-thin Si film may be formed by direct bonding without using an adhesive. In this case, after strict alignment, adhesion and adhesion based on the present embodiment are performed between the semiconductor integrated circuit device layers, the substrates 75 and 76 are removed from the manufacturing apparatus of the present embodiment and then placed in the solvent of the adhesive. The supporting substrate may be removed by immersing the substrate. In the case of direct bonding without using an adhesive, the supporting substrate is removed by grinding or polishing.

(Embodiment 14) In Embodiment 13, as shown in FIG. 21, the position detection using the position recognition targets on the substrates 75 and 76 is performed with the main surfaces of the substrates 75 and 76 facing up. It was In this embodiment, the substrate 75 and the second stage 72 are configured to transmit visible light and further ultraviolet light so that the substrate 75 is mirror-inverted, that is, the substrate 75 and 76 can be left as they are as shown in FIG. I gave it in. Omit the second stage 72,
You may distinguish between the position-recognition target marks on the board | substrate 75 and the board | substrate 76. Here, the target mark for position recognition on the substrate 76 is detected by the detection optical system 77.
To be identified. According to this embodiment, the first embodiment
The alignment mechanism between the substrates by the stage marks 80 and 81 used in No. 3 can be omitted, more direct alignment between the substrates 75 and 76 is possible, and the device can be simplified. Further, in the thirteenth embodiment, when there is a large positional misalignment between the substrate 75 and the second stage 72, there is a drawback that the position cannot be recognized, but in the present embodiment, between the substrates 75 and 76. The existence of a large misalignment of is obvious and can be easily corrected.

In this embodiment, the substrate 75 and the second stage 72 are configured to transmit ultraviolet light, so that the detection optics having a shorter wavelength can be detected as compared with the case where only infrared light can be transmitted like a normal Si substrate. System 77 is ready for use.
Therefore, more precise position detection becomes possible. Considering the transmission characteristics for ultraviolet light and easy availability,
The stage 72 of is preferably a transparent quartz substrate,
The substrate 75 is a single crystal S bonded to the transparent quartz substrate with a thin adhesive (especially a CFC resin that can also transmit ultraviolet light).
i It is desirable that the semiconductor integrated circuit device layer is an ultra-thin film. Here, the film thickness of the Si ultra-thin film is preferably 100 nm or less from the condition of transmitting ultraviolet light. Substrates 75 and 76 which have been subjected to steps such as precise position detection, subsequent adhesion, and ultra-thinning according to the present embodiment have the ultra-thin film formed by removing the transparent quartz substrate according to the first or second embodiment. To be done.

In Embodiments 13 and 14, the factor obstructing the precise alignment between the substrates 75 and 76 is due to the film formation on the substrate which is indispensable for the manufacture of the integrated circuit device formed on each of the substrates 75 and 76. . That is, the semiconductor integrated circuit device or the semiconductor integrated circuit device due to the thermal stress based on the difference in the thermal expansion coefficient from the substrate due to the internal stress of various insulating films formed on the substrate or the metal film itself or the various heat treatments performed in the state of film formation on the substrate. The substrate on which the semiconductor integrated circuit device layer is formed is warped as it is convex or concave, and the pattern on the substrate surface is distorted and expanded. The above-mentioned pattern distortion and expansion / contraction are particularly remarkable in the peripheral area of the substrate. An integrated circuit device was manufactured to significantly mitigate the effects of the pattern distortion and expansion and contraction in the step of performing precise alignment between two substrates.
The problem can be solved by controlling the warpage of the substrates to be the same. As one of the methods, the two substrates are configured so as to be flat. Specifically, in Examples 13 and 14, the substrate 75 was placed on the stage 72 and the substrate 7 was placed on the stage 73.
6 was vacuum-sucked, but the vacuum suction can be realized by strongly sucking the substrate with a stage having an extremely flat surface and having a large number of suction holes. The larger the number of suction holes, the more the suction substrate can conform to the shape of the stage, and the stage having a porous structure is desirable. This makes it possible to keep the main surfaces of the two substrates for precise alignment flat and minimize pattern distortion and expansion and contraction. Two
From the viewpoint of controlling the pattern distortion and expansion / contraction on the main surfaces of the substrates to be the same, the main surface is not necessarily a flat surface, and may be controlled to a desired curved surface so that the pattern distortion and expansion / contraction are the same.

(Embodiment 15) FIG. 23 is a sectional view showing a method of manufacturing a semiconductor integrated circuit device according to a fifteenth embodiment of the present invention. In the present embodiment, a technique for more precise alignment between the two substrates was pursued. As mentioned above,
The expansion and contraction and distortion of the pattern formed on the surface of the substrate largely depend on the film thickness of various insulating films and metal films formed on the substrate in the manufacturing process of the integrated circuit device and the heat treatment history after the various films are formed. Therefore, it is unavoidable that expansion / contraction and distortion peculiar to the integrated circuit device occur in the pattern of the integrated circuit device formed on the semiconductor substrate. In this embodiment, based on the above situation, the two substrates are bonded together while guaranteeing accurate alignment. That is, the two substrates to be bonded were made to have the same history of film forming conditions. In FIG. 23, 57 and 58 are semiconductor integrated circuit device layers each of which is a single crystal Si ultrathin film, and the ultrathin film and its bonding were performed based on the second or third embodiment. Reference numeral 30 denotes a transparent quartz substrate, which is adhered to the ultrathin film 57 with the water-soluble adhesive 26 and the fluorocarbon adhesive 34. The manufacturing processes of 57 and 58 are different from each other, and therefore, the warp amount of the semiconductor substrate is different at the stage before the ultra thin film formation, that is, at the stage where the semiconductor integrated circuit device is formed on the main surface of the semiconductor substrate. With respect to such a semiconductor substrate, in this embodiment, an insulating film having a coefficient of linear expansion different from that of the semiconductor substrate is deposited and controlled so that the two semiconductor substrates have the same warp direction and amount. The insulating film may be deposited on any surface of the semiconductor substrate. Then, using the apparatus described in Example 13, the two semiconductor substrates were precisely aligned and adhered to each other. Between two substrates having the same warp direction and amount, the amount of expansion and contraction of the pattern and the amount of distortion are almost equal, the relative pattern displacement is eliminated, and good alignment can be performed.

Two sets of ultra-thin films 57 and 58 manufactured by exactly the same manufacturing process are adhered to the transparent quartz substrate 30, respectively, and they are directly bonded again without using an adhesive by using the apparatus described in the thirteenth embodiment. The lamination was performed to form an ultrathin film having a four-layer structure.
Thereafter, the water-soluble adhesive 26 is melted to remove one transparent quartz substrate 30 and then adhered to a separately prepared support substrate, and the other transparent quartz substrate 30 is also removed by melting the adhesive 34 to thereby integrate the semiconductors. Completed the circuit device. In the production of the ultra-thin film having the four-layer structure, the two sets of superposed ultra-thin films 57 and 58 are produced by exactly the same production process and have the same sectional structure. As a result, the pattern positional deviations generated in the superposed ultra-thin films 57 and 58 are relatively equal, and accurate positioning can be easily realized without any special measures. (Embodiment 16) FIG. 24 is a plan view showing a method for manufacturing a semiconductor integrated circuit device according to a sixteenth embodiment of the present invention.
In each of the above-described embodiments, the semiconductor integrated circuit device of the present invention has been described including its manufacturing method. However, in any of the embodiments, a semiconductor substrate or a quartz substrate in which a semiconductor integrated circuit device or a semiconductor integrated circuit device layer is separately prepared A method of adhering the ultrathin film to another substrate by some method after adhering it once to a desired manufacturing process such as forming an ultrathin film is used. In the above method, the first bonded semiconductor substrate, quartz substrate, or the like is peeled from the semiconductor integrated circuit device or the semiconductor integrated circuit device layer, but depending on the adhesive, peeling with the solvent may not be easy. This is because the thickness of the adhesive is small and the solvent does not quickly penetrate into the adhesive surface. The solvent is quickly permeated into the adhesive surface, and the quartz substrate 72
In order to quickly peel off the semiconductor substrate from the semiconductor integrated circuit device or the semiconductor integrated circuit device layer 75, in this embodiment, as shown in FIG. Through hole 59
The thing which formed multiple pieces was used. There may be one through hole 59 depending on the type of adhesive.

In the method for manufacturing a semiconductor integrated circuit device according to the first and second embodiments, a semiconductor substrate having a semiconductor integrated circuit device or a semiconductor integrated circuit device layer formed thereon is adhered to a quartz substrate to obtain an ultra thin film. After performing the manufacturing process of
The semiconductor integrated circuit device or the semiconductor integrated circuit device layer separately prepared is precisely aligned and bonded. Thereafter, the quartz substrate is peeled off, but the time required for the peeling is compared between the quartz substrate 72 according to the present embodiment and the quartz substrate 30 having no through hole 59 in this peeling step. As the adhesive to be melted, a water-soluble adhesive such as polyvinyl alcohol, a fluorocarbon adhesive, and the diameter of the through hole 59 provided in the quartz substrate 72 is 10 μm to 200 μm.
The number of through holes 59 was also variously examined from 1 to 50. In any case, the quartz substrate 7 according to the present embodiment having the through hole 59
When 2 was used, the time required for peeling could be significantly shortened to less than 1/10. The quartz substrate 72 having the through holes 58 satisfying the above described conditions can operate in exactly the same way as the quartz substrate having no through holes 59 through the steps of pre-bonding and subsequent desired manufacturing steps such as ultra-thinning. Did not occur.

In each of the above-mentioned embodiments, the material of the adhesive is specified for the sake of simplification of description, but the spirit of the present invention is the melting of the first adhesive and the second adhesive. However, the material of the adhesive is not limited as long as it is within the range. Also,
Melting of the adhesive is a process to transfer the manufactured ultra-thin film to another supporting substrate, and if the increase in manufacturing cost due to consumption of the substrate to be adhered is not taken into consideration, the ultra-thin film is transferred to another supporting substrate. After that, the adherend substrate may be removed by mechanical polishing / grinding.

(Embodiment 17) FIGS. 25 to 26 are sectional views showing a semiconductor integrated circuit device according to a sixteenth embodiment of the present invention in the order of manufacturing steps. In the second embodiment, an opening is formed in the protective insulating film 12 from the state of FIG. 6, and metal films 65 and 66 containing Al as a main material are buried in the opening to form the protective insulating film 1.
The surface was flattened and cleaned so that it was flush with the two surfaces. Further, a thick polycrystalline Si film 24 is formed on a semiconductor integrated circuit device formed on another single crystal Si substrate 11 by the same manufacturing method as in FIG.
Are deposited and the surface thereof is flattened and polished, an adhesive layer 23 made of a fluororesin is formed on the surface thereof, and an opening reaching the semiconductor integrated circuit device is formed in the adhesive layer 23. Metal film 67 whose main part is Al
And 68 were embedded and flattened and cleaned so as to be flush with the surface of the adhesive layer 23. After that, accurate alignment was performed using the alignment device described above to bond the two together (FIG. 25).

Then, the second Si substrate 11 is heated to 100 ° C.
Then, the wax 20 was melted and peeled from the quartz substrate 30, and the remaining wax was removed by washing with acetone and the polycrystalline Si film 22 was selectively etched. The wax removing step has no influence on the adhesive layer 23 made of a fluororesin. Next, wiring 18 was formed on the single crystal ultra-thin film Si layer 1 based on a desired circuit configuration to complete a semiconductor integrated circuit device (FIG. 26).

Although the memory cell array was laminated and integrated as the semiconductor integrated circuit device according to the present embodiment, the memory cell array of each layer was formed by the same manufacturing process and the same heat treatment process, and therefore had the same function. The function did not change even by stacking and integrating. The maximum wiring length in the conventional planar structure integrated structure was shortened by the stacking according to this embodiment, and the access speed could be improved.
Further, since the present embodiment has a configuration in which the connection wiring is exposed on the adhesive surface and the connection wiring can be formed on the exposed surface, there is an advantage that the method of this embodiment can be easily applied to stacking three or more layers. It is clear.

[0060]

According to the present invention, since the semiconductor integrated circuit device can be aligned in the vertical direction with extremely high accuracy, the semiconductor integrated circuit device can be further integrated without increasing the area. In the above-mentioned lamination, the semiconductor integrated circuit devices of the respective layers can be laminated while maintaining the same characteristics and functions including the heat treatment step. According to the present invention, it is possible to manufacture an ultra-high performance, large-capacity semiconductor integrated circuit device required by the existing semiconductor manufacturing apparatus for the next generation and the next generation without requiring new capital investment such as increasing the diameter of the semiconductor substrate. Further, according to the present invention, a plurality of semiconductor integrated circuit devices constituting the system are preliminarily manufactured in advance,
It is possible to quickly manufacture and ship the system requested by the customer according to the demand situation. Therefore, the manufacturing process can be shortened and the cost can be reduced.

According to the present invention, the basic circuit constituting the semiconductor integrated circuit device is further manufactured on the same semiconductor substrate for each desired component group, and the integrated circuits are integrated into one basic circuit by stacking them. You can Therefore, as compared with the conventional structure in which regions of different conductivity type are formed by dividing the regions in the same substrate, the manufacturing process and the occupied area required for the region separation can be omitted. In addition, mutual interference between adjacent elements and restrictions on the degree of freedom of the element structure based on the adjacent element manufacturing process can be eliminated.
As a result, the manufacturing process is shortened and the cost is reduced.

As the capacity and area of a semiconductor integrated circuit device increase, the probability that an element or a constituent circuit will fall into manufacturing defects increases. Further, according to the present invention, a defective area is selected for each element or desired unit. However, the current path can be switched to a normal element or a region on the side of the constituent circuit. As a result, the yield of non-defective semiconductor integrated circuit devices with large capacity and large area can be significantly improved.

According to the present invention, in the process of manufacturing the ultrathin film, when the ultrathin film is transferred from the first supporting substrate to which the ultrathin film is adhered to another supporting substrate, the first supporting substrate is peeled without being consumed. Therefore, a large-scale semiconductor integrated circuit device can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a conventional semiconductor integrated circuit device.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a completed sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 8 is a completed sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 11 is a completed sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 12 is a completed sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 13 is a completed sectional view of a semiconductor integrated circuit device according to fifth and sixth embodiments of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 15 is a completed sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 16 is a completed sectional view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 17 is a completed cross-sectional view of the semiconductor integrated circuit device according to the ninth and tenth embodiments of the present invention.

FIG. 18 is a completed sectional view of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to embodiment 12 of the present invention.

FIG. 20 is a completed sectional view of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 21 is a conceptual diagram showing a semiconductor integrated circuit device manufacturing apparatus according to a thirteenth embodiment of the present invention.

FIG. 22 is a conceptual diagram showing an apparatus for manufacturing a semiconductor integrated circuit device according to Example 13 of the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to example 15 of the present invention.

FIG. 24 is a plan view showing a semiconductor integrated circuit device of Embodiment 16 of the present invention.

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device according to example 17 of the present invention.

FIG. 26 is a plan view showing a semiconductor integrated circuit device according to a seventeenth embodiment of the present invention.

FIG. 27 is a sectional view showing an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4, 5 ... Gate electrode, 6, 7, 8 ... Diffusion layer, 9,
15 ... Terminal electrode, 10 ... Electrode protective insulating film, 11 ... Semiconductor substrate, 14 ... Wiring, 16 ... Protective insulating film, 17 ... Connection wiring, 18 ... Wiring, 19 ... Gate electrode, 20, 25 ... Wax, 21, 23 ... Adhesive layers, 22, 24, 27, 28 ...
Polycrystalline Si film, 26, 29 ... Adhesive layer, 30 ... Transparent quartz substrate, 31, 35, 40 ... Si substrate, 32 ... Thin insulating film,
33 ... Low resistance polycrystalline Si film, 36 ... Thermal oxide film, 37 ... Low resistance conductive wiring, 38 ... Polycrystalline Si film, 39 ... Electrical open area, 41, 44 ... Electrode protective insulating film, 42, 43 ... Low Resistive conductive film, 45 ... Adhesive layer, 46, 47 ... Gate electrode, 4
9 ... Electrode, 50 ... Ultra-thin film Si configured main memory
Layers, 51, 52, 53 ... Ultra thin film Si layer with extended storage device, 54 ... Ultra thin film Si with central processing unit
Layers, 55, 56 ... Gate electrodes of current path control transistors, 57, 58 ... Ultra thin film semiconductor integrated circuit devices, 59 ...
Through holes, 61, 62, 63 ... Diffusion layers, 71, 72, 73
... Stage, 74 ... Block, 75, 76 ... Substrate, 7
7, 78, 84 ... Position detection optical system, 79 ... Position recognition unit,
80, 81 ... Stage mark, 82 ... Substrate deformation control mechanism, 83 ... Computer control control system, 85 ... Stage position control system, 86 ... Moving mechanism, 201 ... First semiconductor integrated circuit layer, 202 ... Second semiconductor integrated Circuit layer, 203 ... Insulating film, 205 ... Inter-layer wiring, 211 ... First wiring layer, 22
1 ... 2nd wiring layer, 212 ... 1st active region, 222 ...
Second active region, 213 ... First layer gate electrode.

Claims (22)

[Claims] 1. A semiconductor integrated circuit device layer in which at least one semiconductor device is provided in each of a plurality of single crystal semiconductor thin film regions separated from each other by an insulating film, and the semiconductor device is connected to each other by a wiring layer. In a stacked semiconductor integrated circuit device, some of the semiconductor devices formed in the semiconductor integrated circuit device layer have substantially the same transmission delay time characteristics and are adjacent to each other. 2. A semiconductor integrated circuit device comprising: a semiconductor device electrode terminal aligned between circuit device layers; and a connecting conductor that penetrates the terminal and reaches the lower terminal. 2. A semiconductor integrated circuit device layer in which at least one semiconductor device is provided in each of a plurality of single crystal semiconductor thin film regions separated from each other by an insulating film, and the semiconductor device is connected to each other by a wiring layer. In the semiconductor integrated circuit device configured by stacking, a part of the semiconductor devices formed in each of the semiconductor integrated circuit device layers has substantially the same transmission delay time characteristic, and the single layer of the upper layer part has the same characteristics. A semiconductor integrated circuit device comprising a connecting conductor which penetrates a crystalline semiconductor thin film region and is connected to the single crystal semiconductor thin film region or a wiring region in a lower layer portion. 3. The semiconductor integrated circuit device according to claim 1, wherein the adjacent semiconductor integrated circuit device layers are laminated by direct bonding without an adhesive layer. Circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device layer has a wiring layer on both a top surface and a bottom surface thereof. 5. The semiconductor integrated circuit device according to claim 4, wherein at least one of the wiring layers is planar and has a terminal for applying a power supply potential or a ground potential. Circuit device. 6. The semiconductor integrated circuit device according to claim 1 or 2, wherein one of the adjacent semiconductor integrated circuit device layers is provided with a first conductivity type semiconductor device, and the other is provided with a second conductivity type semiconductor device. And a semiconductor integrated circuit device which is paired with each other. 7. The semiconductor integrated circuit device according to claim 1, wherein a transistor is provided in a desired region of one of the semiconductor integrated circuit device layers which are adjacent to each other, and a transistor is provided in a desired region of the other semiconductor integrated circuit device layer. A semiconductor integrated circuit device, wherein a capacitive element is provided in alignment with the transistor to form a pair. 8. The semiconductor integrated circuit device according to claim 7, wherein one electrode of the capacitance element is connected to a refractory metal film or a refractory metal silicide film, and the metal film or the metal silicide film is provided under the transistor. And a semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 1 or 2, wherein one of the adjacent semiconductor integrated circuit device layers which is laminated adjacently is composed of only a memory cell array. . 10. The semiconductor integrated circuit device according to claim 1, wherein the plurality of stacked semiconductor integrated circuit device layers have a main memory device and an extended memory device. . 11. The semiconductor integrated circuit device according to claim 1, wherein the plurality of stacked semiconductor integrated circuit device layers have a main memory device and a cache memory device. 12. The semiconductor integrated circuit device according to claim 10 or 11, wherein the other semiconductor integrated circuit device layer to be stacked has a central processing unit. 13. The semiconductor integrated circuit device according to claim 1 or 2, wherein a unit circuit group and a switch for selecting one of them are provided in a pair relationship at the contact positions of the semiconductor integrated circuit device layers which contact each other. A semiconductor integrated circuit device comprising: 14. A control means for deforming and correcting a positional irregularity in a desired region of a first substrate having a position detection pattern by applying a mechanical or thermal external force, and a second substrate having the position detection pattern and the first substrate. An apparatus for manufacturing a semiconductor integrated circuit device, comprising: control means for aligning a substrate using the position detection pattern; and control means for bringing the first substrate and the second substrate into close contact with each other. 15. A semiconductor integrated circuit device manufacturing apparatus according to claim 14, wherein a semiconductor integrated circuit device or a semiconductor integrated circuit device layer is formed on the first and second substrates. Manufacturing equipment for integrated circuit devices. 16. The manufacturing apparatus of a semiconductor integrated circuit device according to claim 14, wherein the first substrate is transparent to visible light. 17. The manufacturing apparatus for a semiconductor integrated circuit device according to claim 14, 15, or 16, wherein
Alternatively, there is provided a semiconductor integrated circuit device manufacturing apparatus having a control means for holding the main surface of the second substrate to a flat surface or a desired curved surface. 18. A step of flattening a main surface of a first substrate on which a first semiconductor integrated circuit device is formed, a flat second substrate on the flattened surface with a first adhesive layer interposed therebetween. And a step of thinning the first substrate from the back surface side to a desired thickness to flatten the surface, and the thinned and flattened surface is transparent to visible light through a second adhesive layer. The step of adhering to the third substrate, the step of removing the first adhesive layer to expose the main surface of the first substrate, the step of providing the second semiconductor integrated circuit device, and the step of planarizing the main surface. No. 4 substrate and the main surface of the first substrate are aligned and bonded, the second adhesive layer is removed, and the thinned and flattened surface is exposed, the first semiconductor integrated circuit An opening is formed through the desired area of the circuit device to reach the desired area of the second semiconductor integrated circuit device, and The method of manufacturing a semiconductor integrated circuit device characterized by a step of. 19. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the bonding is performed between layers of the semiconductor integrated circuit device having a uniform sectional structure. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein a solvent injection hole for the second adhesive layer is provided at a desired portion of the third substrate. Manufacturing method of integrated circuit device. 21. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the first semiconductor integrated circuit device layer and the second semiconductor integrated circuit device layer are bonded to each other in place of the connecting step through the opening. A method of manufacturing a semiconductor integrated circuit device, comprising connecting and interconnecting metal surfaces exposed to each other. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of aligning the main surfaces of the fourth substrate and the first substrate and adhering them directly without using an adhesive, Further, after the second adhesive layer is removed, a heat treatment for increasing the adhesive strength is performed, which is a method for manufacturing a semiconductor integrated circuit device.