JPH07147532A - Negative surge clamping circuit - Google Patents

Abstract

PURPOSE:To allow the circuit to withstand a high negative surge noise without increasing power consumption by feeding back a current with a predetermined ratio to a supplied current to a reference potential generating element to reduce load fluctuation when a negative surge noise penetrated to a terminal of an integrated circuit is absorbed through the supply of a current to the terminal. CONSTITUTION:When a potential of a small signal terminal 20 is lower than a forward bias of a diode Q17 through which a current flows from a constant current source 11, transistors(TRs) Q13-Q15 are active. Let a current flowing from the terminal 20 be IN, a collector current Ic14 of the TRQ14 is expressed as Ic14=IN/(n+1). Since the current Ic14 also flows to a collector of the TRQ13, a collector current of the TRQ12 is also the current Ic14 by the mirror circuit configuration. Then a forward bias VBE17 of a TRQ17 is expressed as VBE17= VT.ln(Ic14+I11)/Is), where I11 is a current of a power supply 11. The current I11 is set sufficiently smaller than the current I14. On the other hand, a base- emitter voltage of the TRQ14 is expressed as VBE14=VT.ln((Ic/Is). When a potential V20 of the terminal 20 is less than and equal to zero, the TRs Q13-Q15 are active independently of the IN.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a negative surge clamp circuit. More specifically, the present invention relates to a negative surge clamp circuit required for preventing negative surge noise from entering the terminals of the integrated circuit and causing the integrated circuit to malfunction.

The invention is particularly applicable to, but not limited to, in-vehicle integrated circuits.

[0003]

2. Description of the Related Art In an integrated circuit, if negative surge noise enters from its terminal, it may induce an undesirable operation of a parasitic transistor, and the operation of such a parasitic transistor causes a malfunction of the integrated circuit. Is known to be.

Therefore, conventionally, in an on-vehicle integrated circuit or the like which is required to have a severe EMI characteristic, a negative surge clamp circuit as shown in FIG. 5 is formed inside the integrated circuit to prevent negative surge noise from entering from each terminal. Absorption has been done.

The negative surge clamp circuit as shown in FIG. 1A is mainly applied to the small signal input terminal such as the input terminal 107 of the comparator 105. In the diode Q ₁₀₂ , a reference potential is generated by the current supplied from the constant current source 101.

In such a configuration, the terminal 107
When a negative surge noise enters the base of the reference potential, the transistor Q ₁₀₃ is formed by connecting the terminal 107 to the emitter becomes active state, the transistor Q
_A current is supplied to the terminal 107 from a power supply connected to the collector of ₁₀₃ .

Further, the negative surge clamp circuit as shown in FIG. 2B is mainly set to a potential higher than the power supply voltage when the open collector output terminal 119 of the transistor Q ₁₁₇ is pulled up by the on-vehicle battery voltage. Applies to terminals that need to be.

In such a configuration, the reference potential is the current from the constant current source 111 to the diodes Q ₁₁₅ and Q _116.
Is generated by being supplied to the series circuit of.

When negative surge noise enters the terminal 119, a forward bias is applied to the diode Q ₁₁₄ , which is formed so that a current flows toward the terminal 119, and a forward bias is applied to the diode Q ₁₁₄ based on the reference potential. Transistor Q formed by connecting the current inflow side to the emitter
₁₁₂ becomes active, and current is supplied to the terminal 119 from the power supply connected to the collector of the transistor Q ₁₁₂ .

The negative surge clamp circuit as shown in FIG. 3C is mainly used at a potential within the power supply voltage, such as when pulling up the open collector output terminal 141 of the transistor Q ₁₃₈ at the power supply voltage. Applied to the terminal.

In such a configuration, the reference potential is such that the current from the constant current source 132 is based on the diode Q ₁₃₆ and the current outflow side of the diode Q _136.
It is generated by flowing 132 to the collector and to the collector of a transistor Q ₁₃₇ formed by connecting the ground to the emitter.

[0012] When the negative surge noise enters the terminal 141, joined by a forward biased diode Q ₁₃₃ which is formed by connecting the reference potential to the current input side, based on the current output side of the diode Q ₁₃₃ , The terminal 141
Transistor Q ₁₃₄ is formed by connecting the emitter to become active state, current to the terminal 141 from the power supply connected to the collector of the transistor Q ₁₃₄ is supplied.

The black-painted diode symbol in the figure means that the diode is formed by a PNP transistor. Further, (n) means that the transistor is formed to be n times larger than the size of the transistor without ().

[0014]

In order to suppress malfunction of the integrated circuit due to the operation of the parasitic transistor, the negative clamp level of the negative surge clamp circuit is set to the operation starting voltage of the parasitic transistor (generally about -0.2 to -0.3). ) Must be higher than.

The negative clamp level in the negative surge clamp circuit described above is as follows: V _BE (Q ₁₀₂ ) -V _BE (Q ₁₀₃ ) -V _BE (Q ₁₁₅ ) + V _BE (Q ₁₁₆ ) -V _BE (Q ₁₁₂₎ a _{-V bE (Q 114) · V} bE (Q 136) + V bE (Q 137) -V bE (Q 133) -V bE (Q 134). Here, V _BE () means forward voltage if the inside of () is a diode, and base-emitter voltage if the inside of () is a transistor.

The above V_BE(Q₁₀₂), V_BE(Q₁₁₅), V
_BE(Q₁₁₆), V_BE(Q₁₃₆), V _BE(Q₁₃₇)smell
The negative surge noise enters the terminal and current is
When supplied, each of the transistors Q₁₀₃, To
Langista Q₁₁₂, Transistor Q₁₃₄Flowing to the base
The current decreases by the current and the reference potential also decreases.

Further, V _BE (Q ₁₀₃ ), V
_BE (Q ₁₁₂ ), V _BE (Q ₁₁₄ ), V _BE (Q ₁₃₃ ), V _BE
( _Q134 ) increases as the supply current increases.

Therefore, the clamp level in the above configuration changes when negative surge noise enters the terminal and current is supplied to the terminal. This is called load fluctuation of the clamp level, and as described above, it is preferable that the clamp level is always maintained above the operation starting voltage of the parasitic transistor.

Since the negative surge clamp circuit as described above has the characteristic that the clamp level decreases as the supply current increases, the effective range of the negative surge clamp circuit is the clamp level decrease represented by the above equation. Negative surge noise is absorbed to the extent that it can be absorbed by a supply current that stays above the starting voltage, and it is necessary to reduce load fluctuations to expand the effective range.

Further, the transistors Q ₁₀₃ , Q ₁₁₂ ,
In Q ₁₃₄ , if the maximum supply current is set to I _NMAX , a base current of I _NMAX / β (β is an amplification factor) is required.
_{In the} current sources 101, 111 and 132 which supply the base currents to ₁₀₃ , Q ₁₁₂ and Q ₁₃₄ , it is necessary to constantly pass a current higher than the current. This is called dark current and increases the power consumption of the integrated circuit. Therefore, a smaller value is preferable.

Since the negative surge clamp circuit as described above has a characteristic that the dark current also increases when the maximum supply current _INMAX is increased so as to cope with a large negative surge noise, the effective range is expanded. Requires increased power consumption.

The technical problem of the present invention is to pay attention to such a problem, and in the negative surge clamp circuit, the load fluctuation can be made small, and the corresponding negative surge noise can be set large without increasing the power consumption. Is to raise.

[0023]

A negative surge clamp circuit according to claim 1, wherein a first semiconductor element which generates a reference potential by flowing a current, and the terminal according to a potential difference between the reference potential and an integrated circuit terminal. A second semiconductor element that controls a current supplied to the second semiconductor element.

Further, a third semiconductor element having a size that is a predetermined multiple of the second semiconductor element and controlling a current supplied to the terminal according to a potential difference between the reference potential and the terminal, and the third semiconductor element. 2 A current supplied from the semiconductor element to the terminal is detected, and a current having a predetermined rate of the detected current is detected by the first
And means for supplying the semiconductor element.

In the negative surge clamp circuit of the second aspect, in such a configuration, the predetermined rate is 1.

According to a third aspect of the present invention, in the negative surge clamp circuit having the above-mentioned structure, the negative surge clamp circuit has a rectifying characteristic in which a current flows from the second and third semiconductor elements to the terminal in a current path for supplying the current to the terminal. A semiconductor element having the same is inserted, and the predetermined ratio is set to less than 1.

According to a fourth aspect of the present invention, in the negative surge clamp circuit as described above, the second and third semiconductor elements are connected to a path for transmitting the reference potential from the first semiconductor element to the second and third semiconductor elements. A semiconductor element having a rectifying characteristic that allows a current to flow is inserted.

[0028]

In the negative surge clamp circuit according to the first aspect of the present invention, the supply current supplied to absorb the negative surge noise is divided according to the size of the semiconductor element, and a current equal to the predetermined rate of the smaller divided current is supplied to the reference potential. It is possible to suppress the load fluctuation at the clamp level by causing the current to flow to the semiconductor element that generates the voltage and displacing the reference potential.

More specifically, the reference potential generated by passing a current through the semiconductor element is V _BE (1), and in the semiconductor element where a current equal to a predetermined ratio of the smaller divided current flows, the reference potential and the terminal are connected. If the voltage drop that occurs, specifically, the base-emitter potential is V _BE (2), then V _BE (1) = V _T · ln (I _C1 / (S ₁ · I _S )) V _BE (2) _{= V T · ln (I C2} / (S 2 · I S)) and can be.

Here, V _T and I _S are constants determined by the physical properties of the semiconductor, and S ₁ and S ₂ are constants determined by the size of the semiconductor element. Also, I _C1 is
I _C2 is a current for generating a reference potential, and I _C2 is a current equal to a predetermined rate of the divided current. The current I _C1 is
Also it includes the dark current I _O to be passed in order to generate a reference potential when said supply current is zero.

In the negative surge clamp circuit of claim 1, since the predetermined rate is m and I _C1 = mI _C2 + I _O , the clamp level is from V _BE (1) to V _BE (2). S ₁ and S ₂ are made equal,
By setting I _O to be sufficiently small, it is possible to set V _BE (1) −V _BE (2) = V _T · ln (m) and to set the clamp level to a constant value that does not depend on the supply current. . That is, it is possible to eliminate the load fluctuation at the clamp level.

By the way, the structure in which the reference potential is displaced by the small current obtained by dividing the supply current is such that the allowable current of the semiconductor element for generating the reference potential is made small so that the semiconductor element can be made small. This is to obtain the advantage of doing.

According to the structure of claim 1, the dark current I _O is (compared to the m · I _C2 )
The condition is that it is sufficiently small, and there is no need to increase it depending on the magnitude of the supply current.

Further, in the negative surge clamp circuit according to the second aspect of the present invention, the m is set to 1 and the clamp level is set to 0 V so as to be particularly suitable for a small signal terminal required to absorb even a small amount of negative surge noise. Hold (0 for small signal
Even if the negative surge clamp circuit operates at V, only a slight current flows through the negative surge clamp circuit and no problem occurs. ).

Further, the negative surge clamp circuit according to claim 3 is provided with a semiconductor element having a rectifying characteristic in which a current is made to flow toward the terminal so as to be particularly suitable for the terminal having 0V or a relatively high potential. Prevents current from flowing from this terminal to the negative surge clamp circuit,
By setting m to be less than 1 and setting the clamp level to a negative potential, the negative surge clamp circuit is prevented from operating when the potential of the terminal is near 0V.

Further, the negative surge clamp circuit according to claim 4 is provided with a semiconductor element having a rectifying characteristic in which a current does not flow toward the reference potential so as to be particularly suitable for the same terminal, so that a semiconductor generating the reference potential is obtained. The current is prevented from flowing into the element from the terminal.

[0037]

EXAMPLES Next, examples of how the negative surge clamp circuit according to the present invention is actually embodied will be described.

[Structure of First Embodiment] FIG.
A first embodiment of the present invention which is particularly suitable for the small signal terminal 20 will be described with reference to the block diagram shown in FIG. 18 is a small signal comparator.

The terminal 20 is connected to the negative input of the comparator 18. A comparison voltage is applied to the positive input of the comparator 18. A resistor R ₁₀ having a relatively large resistance value is generally externally attached to the terminal 20 for inputting such a small signal.

Reference numeral 19 is a power supply terminal. A power supply Vcc is externally supplied to the terminal 19. A series circuit of a constant current source 11 and a diode Q ₁₇ is connected between the terminal 19 and the ground, with the current outflow side of the diode Q ₁₇ being connected to the ground. A current flows from the constant current source 11 toward the diode Q ₁₇ .

A current mirror circuit composed of PNP type transistors Q ₁₂ and Q ₁₃ is connected to the terminal 19. In the current mirror circuit, a current equal to the collector current flowing through the transistor Q ₁₃ is also supplied to the collector of the transistor Q ₁₂ .

The collector of the transistor Q ₁₂ is connected to the connection point between the constant current source 11 and the diode Q ₁₇ . The collector of the transistor Q ₁₃ is an NPN.
Connected to the collector of the type transistor Q ₁₄ . The emitter of the transistor Q ₁₄ is connected to the terminal 20.

The collector of the NPN transistor Q ₁₅ is
It is connected to the terminal 19. The emitter of the transistor Q ₁₅ is connected to the terminal 20. The base of the transistor Q ₁₅ is connected to the connection point of the constant current source 11 and the diode Q ₁₇ together with the base of the transistor Q ₁₄ .

The diode Q ₁₆ connects the current input side to the emitter of the transistor Q _14, Q _15, the emitter of the transistor Q _14, Q ₁₅ transistors Q _14,
Connected to the base of Q ₁₅ .

The diodes Q ₁₆ and Q ₁₇ are constructed by using NPN type transistors as described later.

The transistor Q ₁₅ is formed such that its emitter area is n times as large as the emitter area of the transistor Q ₁₄ . The transistor Q ₁₄ and the diode Q ₁₇ , and the transistor Q ₁₂ and the transistor Q ₁₃ are formed so that their emitter areas are the same.

[Operation of the First Embodiment] When the potential of the terminal 20 becomes lower than the forward bias of the diode Q ₁₇ , the transistors Q ₁₃ , Q ₁₄ and Q ₁₅ are activated. Here, when the current flowing out from the terminal 20 is I _N , the collector current I of the transistor Q ₁₄ is
_C14 is represented by I _C14 = I _N / (n + 1).

Since I _C14 also flows into the collector of the transistor Q ₁₃ , the collector current of the transistor Q ₁₂ also becomes I _C14 due to the mirror circuit configuration. Therefore, the forward bias V of the diode Q ₁₇ is
_BE17, the current constant current source 11 flow as I _11, represented by _{V BE17 = V T · ln (} (I C14 + I 11) / I S). However, I ₁₁ is set to be sufficiently smaller than I _C14 .

On the other hand, the base-emitter voltage V _BE14 of the transistor Q ₁₄ is represented by V _BE14 = V _T · ln (I _C14 / I _S ).

From the above, the potential V of the terminal 20 is
_20, when the V ₂₀ ≦ 0, not dependent on the I _N, the transistor Q
₁₃ , Q ₁₄ and Q ₁₅ are activated.

[Supplement to First Embodiment] In addition,
Although the figure (a) is shown as a bipolar transistor, it may be replaced with an FET as shown in the figure (b). Those with a dash in FIG. 2 (b) correspond to those with the same reference numeral without a dash in FIG.

[Structure of Second Embodiment] Next,
A second embodiment of the present invention which is particularly suitable for the open collector terminal 52 will be described with reference to the block diagram shown in FIG. Transistor Q ₄₉ has an open collector output.

The terminal 52 is connected to the collector of the transistor Q ₄₉ . The terminal 52 is a diode Q _45.
It is also connected to the current outflow side. A pull-up resistor R ₄₀ is generally connected to such an open collector output terminal 52. Further, in this example, the pull-up power supply voltage V _B may be higher than the power supply voltage Vcc.

Reference numeral 51 is a power supply terminal. The power supply Vcc is externally supplied to the terminal 51. A constant current source 50, a diode Q ₄₇ and a diode Q ₄₈ are provided between the terminal 51 and the ground.
A series circuit of a is to connect the current output side of the diode Q ₄₇ to the current input side of the diode Q _48, and connect the current output side of the diode Q ₄₈ to ground, is connected. A current flows from the constant current source 50 toward the diodes Q ₄₇ and Q ₄₈ .

The terminal 51 is connected to a current mirror circuit composed of PNP type transistors Q ₄₁ and Q ₄₂ . The transistor Q ₄₂ is formed such that the emitter area thereof is m times the emitter area of the transistor Q ₄₁ .

In the current mirror circuit, a current equal to 1 / m of the collector current flowing through the transistor Q ₄₂ is also supplied to the collector of the transistor Q ₄₁ .

The collector of the transistor Q ₄₁ is connected to the connection point between the constant current source 50 and the diode Q ₄₇ . The collector of the transistor Q ₄₂ is an NPN.
Connected to the collector of the type transistor Q ₄₃ . The emitter of the transistor Q ₄₃ is connected to the current inflow side of the diode Q ₄₅ .

The collector of the NPN transistor Q ₄₄ is
It is connected to the terminal 51. The emitter of the transistor Q ₄₄ is connected to the current inflow side of the diode Q ₄₅ .
Also, it based the transistor Q _44, the base together with the transistor Q _43, is connected the connection node between the constant current source 50 and the diode Q _47.

[0059] Diode Q ₄₆ connects the current input side to the emitter of the transistor Q _43, Q _44, the transistor Q _43, the emitters of Q ₄₄ and the transistor Q _43, Q
Connected between ₄₄ bases.

The diodes Q ₄₆ and Q ₄₇ are constructed by using NPN type transistors as described later. The diodes Q ₄₅ and Q ₄₈ are constructed by using PNP type transistors as described later.

[0061] The transistor Q ₄₄ is, (n emitter area of the emitter area of the transistor Q ₄₃
-1) Doubled. The diode Q ₄₅
Is formed such that its emitter area is n times the emitter area of the transistor Q ₄₈ .

The transistor Q ₄₃ and the diode Q
_{At 47} , their emitter areas are formed to be the same.

[0063] [The operation of the second embodiment] The diode Q _47, a forward bias of Q ₄₈ V _BE47, V _BE48
, The forward bias of the diode Q ₄₅ is V _BE45
When, the potential of the terminal 52 becomes lower than V _BE47 + V _BE48 -V _BE45, the transistors Q _42, Q _43, Q ₄₄
Becomes active.

Here, the current flowing out from the terminal 52 is I
_{Assuming N} , the collector current I of the transistor Q _43
C43 is represented by I _C43 = I _N / n.

Since the I _C43 also flows into the collector of the transistor Q ₄₂ , the collector current of the transistor Q ₄₁ becomes I _C43 / m due to the mirror circuit configuration. Therefore, forward bias V _BE47, V _BE48 of the diode Q _47, Q ₄₈ is a current that the constant current source 50 is flowed I
As _50, represented by _{V BE47 = V BE48 = V T} · ln ((I C43 / m + I 50) / I S). However, the I ₅₀ is set to be sufficiently smaller than the I _C43 / m.

The forward bias V _BE45 of the diode Q ₄₅ is represented by V _BE45 = V _T · ln (I _N / (n · I _S )).

On the other hand, the base-emitter voltage V _BE43 of the transistor Q ₄₃ is represented by V _BE43 = V _T · ln (I _C43 / I _S ).

From the above, the potential V of the terminal 52 is
_52, when the _{V 52 ≦ -2V T · ln (} m), independent of the I _N, the transistor Q
₄₂ , Q ₄₃ and Q ₄₄ are activated.

[Supplement to Second Embodiment] In addition,
Although the figure (a) is shown as a bipolar transistor, it may be replaced with an FET as shown in the figure (b). Those with a dash in FIG. 2 (b) correspond to those with the same reference numeral without a dash in FIG.

[Regarding Configuration of Third Embodiment] Next,
A third embodiment of the present invention, which is particularly suitable for the open collector terminal 74, will be described based on the block diagram shown in FIG. Transistor Q ₇₀ is an open collector output.

The terminal 74 is connected to the collector of the transistor Q ₇₀ . A pull-up resistor R ₆₀ is generally connected to such an open collector output terminal 74, and a resistor R ₆₁ is generally connected to the output destination. In this example, the pull-up power supply voltage is the power supply voltage V
It is assumed that it is cc or less.

Reference numeral 73 is a power supply terminal. The power supply Vcc is externally supplied to the terminal 73. Between the terminal 73 and the ground, a series circuit of a constant current source 72 and a PNP transistor Q ₆₉ connects the collector of the transistor Q ₆₉ to the constant current source.
Connected by connecting to 72, connecting the emitter to ground.

Transistor Q₆₉The base of the die
Aether Q₆₈The current outflow side of is connected. The diode Q
₆₈The current inflow side of the transistor Q₆₉To the collector of
Connected. Current from the constant current source 72 is the diode.
De Q₆₈, The transistor Q ₆₉To the collector of
Will be issued.

A current mirror circuit composed of PNP type transistors Q ₆₂ and Q ₆₃ is connected to the terminal 73. In the current mirror circuit, a current equal to the collector current flowing in the transistor Q ₆₃ is also supplied to the collector of the transistor Q ₆₂ .

The collector of the transistor Q ₆₂ is connected to the connection point between the constant current source 72 and the transistor Q ₆₉ . The collector of the transistor Q ₆₃ is NP
It is connected to the collector of an N-type transistor Q ₆₄ . The emitter of the transistor Q ₆₄ is connected to the terminal 74.

The collector of the NPN transistor Q ₆₅ is
It is connected to the terminal 73. The emitter of the transistor Q ₆₅ is connected to the terminal 74. Further, the base of the transistor Q ₆₅ is connected to the current outflow side of the diode Q ₆₇ together with the base of the transistor Q ₆₄ . The current inflow side of the diode Q ₆₇ is connected to the connection point between the current source 72 and the transistor Q ₆₉ .

[0077] Diode Q ₆₆ connects the current input side to the emitter of the transistor Q _64, Q _65, the emitter of the transistor Q _64, Q ₆₅ transistors Q _64, Q
Connected with the base of ₆₅ .

The emitter of the PNP transistor Q ₇₁ is
It is connected to the terminal 74. The base of the transistor Q ₇₁ is connected to the terminal 73. The collector of the transistor Q ₇₁ is connected to ground.

The diode Q ₆₆ is constructed by using an NPN type transistor as described later. Further, the diodes Q ₆₇ and Q ₆₈ have P
It is configured by using an NP type transistor.

The emitter area of the transistor Q ₆₅ is (n) of the emitter area of the transistor Q _64.
-1) Doubled.

The diode Q ₆₇ and the diode Q ₆₈ , the transistor Q ₆₄ and the transistor Q ₆₉ , the transistor Q ₆₂ and the transistor Q _63.
, They are formed so that their emitter areas are the same.

[Regarding Operation of Third Embodiment] The forward bias of the diodes Q ₆₇ and Q ₆₈ is set to V _BE67 and V _{BE68.
Assuming} that the base-emitter voltage of the transistor Q ₆₉ is V _BE69, and the potential of the terminal 74 becomes lower than V _BE68 + V _BE69 −V _BE67 , the transistors Q ₆₃ , Q ₆₄ , and Q ₆₅
Becomes active.

Here, the current flowing out from the terminal 74 is
_N , the collector current I of the transistor Q _64
C64 is represented by I _C64 = I _N / n.

Since I _C64 also flows to the collector of the transistor Q ₆₃ , the collector current of the transistor Q ₆₂ becomes I _C64 due to the mirror circuit configuration.
Therefore, the forward bias V _BE68 of the diode Q ₆₈ and the base-emitter voltage V _BE69 of the transistor Q ₆₉ are as _follows : the current flowing from the constant current source 72 is I ₇₂ , and the amplification factor of the transistor Q ₆₉ is β. V _BE68 = V _T · ln (((I _C64 + I ₇₂ ) / β) / I _S ) V _BE69 = V _T · In ((I _C64 + I ₇₂ ) / I _S ). However, the I ₇₂ is set to be sufficiently smaller than the I _C64 .

The forward bias V _BE67 of the diode Q ₆₇ is represented by V _BE67 = V _T · ln ((I _N / β) / I _S ).

On the other hand, the base-emitter voltage V _BE64 of the transistor Q ₆₄ is represented by V _BE64 = V _T · ln (I _C64 / I _S ).

From the above, the potential V of the terminal 74 is
_74, at the _{V 74 ≦ -V T · ln (} n), does not depend on the I _N, the transistor Q
₆₃ , Q ₆₄ and Q ₆₅ become active.

The potential of the terminal 74 is higher than the power source Vcc.
When it gets higher, the transistor Q ₇₁Becomes active
It

[Supplement to Third Embodiment] In addition,
Although the figure (a) is shown as a bipolar transistor, it may be replaced with an FET as shown in the figure (b). Those with a dash in FIG. 2 (b) correspond to those with the same reference numeral without a dash in FIG.

[Fourth Embodiment] The diode is formed as shown in FIG. Figure (a)
Is a configuration using an NPN type transistor. Same figure
(b) is a configuration using a PNP type transistor.

[0091]

As described above, in the negative surge clamp circuit according to the first aspect of the present invention, when the negative surge noise invading the terminal of the integrated circuit is supplied to the terminal and absorbed, a predetermined ratio of the supplied current is absorbed. Is fed back to a device that generates a clamp level reference potential.

Therefore, unlike the prior art, when the supply current increases, the reference potential does not decrease, but the reference potential is increased, and the amount of increase is a voltage drop that occurs in an element that causes the supply current to flow. The clamp level can now be kept constant by equalizing the amount. In other words, it was possible to eliminate the load fluctuation at the clamp level.

In the negative surge clamp circuit according to the first aspect of the invention, as described above, the dark current flowing to generate the reference potential when the supply current is 0 is set to be sufficiently small. So unlike the past,
It is no longer necessary to increase power consumption to set a large negative surge noise that can be handled.

Since the negative surge clamp circuit of claim 2 has the clamp level of 0 V as described above, it can be particularly applied to a small signal terminal which is required to absorb even a slight negative surge noise. It was

According to the negative surge clamp circuit of the third aspect, since the clamp level is set to the negative potential as described above,
It has become particularly applicable to terminals that reach 0V.

According to the negative surge clamp circuit of the third and fourth aspects,
As described above, since the current is prevented from flowing backward from the terminal to the clamp circuit, the present invention can be applied particularly to a terminal having a relatively high potential.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a conventional negative surge clamp circuit.

[Explanation of symbols]

Q ₁₂ and Q ₁₃ Transistors that form a current mirror circuit Q ₁₇ Diodes that generate a reference potential Q ₁₄ and Q ₁₅ Transistors Q ₄₁ and Q ₄₂ Transistors that form a current mirror circuit Q ₄₇ and Q ₄₈ Diodes that generate a reference potential Q ₄₃ , Q ₄₄ Transistor Q ₄₅ Diode for preventing reverse current Q ₆₂ , Q ₆₃ Transistor forming current mirror circuit Q ₆₈ Diode for generating reference potential Q ₆₉ Transistor for generating reference potential Q ₆₄ , Q ₆₅ Transistor Q _{67 For} preventing reverse current diode

Claims (4)

[Claims] 1. A negative surge clamp circuit for preventing a negative surge noise from entering a terminal of an integrated circuit to malfunction the integrated circuit, wherein the first semiconductor element generates a reference potential by flowing a current. A second semiconductor element that controls a current supplied to the terminal according to a potential difference between the reference potential and the terminal potential; a size that is a predetermined multiple of the second semiconductor element, the reference potential and the terminal A third semiconductor element that controls a current supplied to the terminal according to a potential difference between the potentials, a current supplied from the second semiconductor element to the terminal is detected, and a current having a predetermined rate of the detected current is detected as the first current. 1. A negative surge clamp circuit comprising: a means for supplying to one semiconductor element. 2. The negative surge clamp circuit according to claim 1, wherein the predetermined rate for controlling the current supplied to the first semiconductor element is 1. 3. The negative surge clamp circuit according to claim 1, wherein a semiconductor element having a rectifying characteristic that causes a current to flow toward the terminal is inserted in a current path for supplying a current from the second and third semiconductor elements to the terminal. The negative surge clamp circuit is characterized in that the predetermined rate for controlling the current supplied to the first semiconductor element is less than 1. 4. The negative surge clamp circuit according to claim 1, wherein a current is made to flow toward the second and third semiconductor elements in a path for transmitting the reference potential from the first semiconductor element to the second and third semiconductor elements. A negative surge clamp circuit in which a semiconductor element having a rectifying characteristic is inserted.