JPH07141892A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve a disturbance resistance with electrical circuit means by restoring a threshold voltage in a case that the change of the threshold voltage of the memory cell of a non-selection is detected after writings or erasings of selected memory cells. CONSTITUTION:After a writing verification is completed, a write state control circuit WCNT starts a disturbance verifying mode. The circuit, in conjunction with the starting of the mode, loads the content of a counter AUPCT on a buffer ADB and enters into the verification of a disturbance address. At first, a disturbance detecting voltage value is impressed on the control gate of the memory cell of a first address. At this time, a detection in a case that the reduction of a threshold value due to the disturbance is larger than a constant value and the knowing of an original value are possible by observing the output data of a sense amplifier SAMP at the time of a disturbance verifying signals DVF=H volt and DVF2=L volt and at the time of DVF=DVF2=H volt. When the output signal DTC is H, the circuit WCNT enters into the re-erasing mode of an address degraded by the disturbance and then restores the threshold voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable and non-volatile semiconductor memory device, or an electrically writable and erasable and non-volatile semiconductor memory device.

[0002]

[Prior art]

Reference 1; SINGLE TRANSISTOR ELECTRICALLY PROGRAMM
ABLE MEMORY DEVICE AND METHOD United States Patent 4,698,787 Oct.6,19
87 Reference 2: FLASH EEPROM ARRAY WITH NEGATIVE GATE
VOLTAGE ERASEOPERATION United States Patent 5,077,691 Dec.31,1
991 Document 3; Present and Future Prospects of Flash Memory ICD91-134 Document 4; Nonvolatile Semiconductor Memory Device Published Patent Publication No.

As a nonvolatile semiconductor memory device, an ultraviolet erasable EPROM (Erasable and Programmable Read) is used.
Only Memory) and an EEPROM (Electrifier) that is electrically writable and erasable (hereinafter referred to as "electrically rewritable")
(ically Erasable and Programmable Read Only Memory)
There is. Furthermore, in recent years, EEPRO that electrically erases all at once
M is being developed. The EPROM is capable of erasing the stored data in the memory cell only with ultraviolet rays and cannot be electrically erased. Therefore, a package with a window having transparency is required as a package, and further, rewriting is performed after mounting the system on a substrate. Had the inconvenience of having to remove it once. The EEPROM is electrically rewritable in the system, but generally requires a transistor or a channel region for selective isolation in the memory cell, and therefore the memory cell area is EPRO.
It is about twice as large as M. In order to solve this problem, a batch erase type EEPROM has been developed which is electrically erasable and has a memory cell area equivalent to that of an EPROM.

Documents initially disclosed as a batch erasing type EEPROM are described in, for example, Document 1. According to document 1, a method and a device structure for electrically writing and erasing by a single memory transistor having a floating gate are provided. In erasing,
By applying a high voltage of 10 to 20 V (V) to the source terminal of the memory cell and a ground potential to the control gate terminal, a high electric field is generated between the thin insulating film between the floating gate and the source terminal, Electrons are emitted from the floating gate by the Farrer-Nordheim tunnel (hereinafter referred to as "FN injection"), which lowers the threshold voltage of the memory cell seen from the control gate.
In writing, 5 to the drain terminal of the memory cell
By applying a voltage of 10 V, applying a high voltage of 10 to 15 V to the control gate, and grounding the source, the drain-
A strong inversion region is generated on the substrate surface between the sources, and hot electrons (hereinafter referred to as “HE injection”) are generated to inject electrons into the floating gate, thereby increasing the threshold voltage of the memory cell. To do.

Further, in pages 2 and 5 of Documents 2 and 3, as another erasing method, a negative voltage (for example, -7V to -15V) is applied to the control gate of the memory cell, and a power supply voltage ( A method has been proposed in which electrons are emitted from the floating gate by FN injection by applying, for example, 5 V) or a ground potential. With this method,
As disclosed in Document 1, it is not necessary to apply a high voltage (for example, 10 to 20 V) to the source terminal, so that there is an advantage that the voltage can be lowered at the time of rewriting. Further, in the case of this method, since the control gate of the memory cell is generally connected to the column decoder as a word line, by applying a voltage of, for example, 0V to 5V to the control gate of the non-selected memory cell, It becomes possible not to induce FN injection, and it becomes possible to erase in word line units (in other words, sector units).

However, when erasing in sector units is realized, the write disturb resistance and the erase disturb resistance must be sufficiently stronger than the batch erase.
It is shown on page 5 of Reference 3. For example, the write disturb time in the batch erasing method should be about 10 milliseconds, but if the sector erasure guarantees the rewriting of 1,000,000 times, the write disturb time is required to be about 10,000 seconds. Here, the disturb refers to the charge holding amount of the floating gate of the non-selected memory cell, that is, the control by the voltage applied to the non-selected memory cell during writing, erasing or reading of the selected memory cell. Meaning that the threshold voltage of the memory cell changes from the gate, it is write disturb if it is in the write mode, erase disturb if it is in the erase mode, and read disturb if it is in the read mode. Is written. Disturb is a change in the threshold voltage of an undesired memory cell (usually, when the threshold voltage is high at the beginning, the threshold voltage is lowered by the disturb, and when the threshold voltage is low, the threshold voltage is raised by the disturb). Failure to take measures will result in the loss of stored information.

[0007]

In order to improve the disturb resistance, Document 3 proposes a solution such as reducing the dose amount of the implantation of the drain into the drain. However, the dose amount of the drain is reduced. In this case, it is necessary to increase the drain voltage at the time of writing, which has a drawback that it hinders rewriting with a low power supply voltage, for example, a single 5 V power supply.

Therefore, an object of the present invention is to substantially improve the resistance to the disturbance by the electric circuit means without the need for optimizing the structure of the memory cell and devising the manufacturing method as in the prior art. A non-volatile semiconductor memory device is provided.

[0009]

In order to solve the above-mentioned problems, according to the present invention, a plurality of electrically writable elements arranged in rows and columns are possible in an electrically writable nonvolatile semiconductor memory device. A non-volatile semiconductor memory cell,
A decoder circuit for setting at least one of the memory cells in a selected state and another memory cell in a non-selected state, a writing unit for writing to the selected memory cell via the decoder circuit, and the decoder circuit. Read means for reading from the memory cell in the selected state via the memory cell, and the memory cell in the non-selected state generated by the voltage applied to the memory cell in the non-selected state at the time of writing to the memory cell in the selected state. Detecting means for detecting a change in the threshold voltage, and the result of detecting the change in the threshold voltage of the non-selected memory cells, the threshold voltage of the non-selected memory cells before the change or Restoration means for restoring the value to the neighborhood.

In a preferred aspect of the present invention, the detection means provides a detection level of the threshold voltage of the memory cell in the selected state more than the minimum number required for reading the stored information of the memory cell, and the detection level is set. And the threshold voltage of the memory cell are compared with each other to extract information for detecting a change in the threshold voltage in addition to the stored information of the memory cell.

In a further preferred aspect of the present invention, the nonvolatile semiconductor memory device operates the detection means after writing the memory cell in the selected state when a writing mode is designated by an external signal or an external command. And a control circuit for operating the restoring means according to a result of detecting a change in the threshold voltage of the non-selected memory cell.

In the electrically writable and erasable non-volatile semiconductor memory device, a plurality of electrically writable and erasable non-volatile semiconductor memory cells arranged in a matrix and at least one of the memory cells A decoder circuit that puts one in a selected state and another memory cell in a non-selected state, a writing unit that writes to the selected memory cell via the decoder circuit, and a memory in the selected state via the decoder circuit. Erasing means for erasing cells, reading means for reading from the memory cells in the selected state via the decoder circuit, and voltage applied to the memory cells in the non-selected state when erasing the memory cells in the selected state Detecting means for detecting a change in the threshold voltage of the memory cell in the non-selected state, which is caused by And a restoring means for restoring the threshold voltage of the memory cell in the non-selected state to a value before the change or a value in the vicinity thereof according to the result of detecting the change in the threshold voltage of the recell. The means provides a detection level of the threshold voltage of the memory cell in the selected state more than the minimum number required for reading the stored information of the memory cell, and compares the detection level with the threshold voltage of the memory cell. By doing so, information for detecting a change in the threshold voltage is taken out in addition to the information stored in the memory cell.

In a preferred aspect of the present invention, the nonvolatile semiconductor memory device operates the detection means after erasing the memory cell in the selected state when an erase mode is designated by an external signal or an external command. A control circuit for operating the restoring means according to a result of detecting a change in the threshold voltage of the non-selected memory cell.

Furthermore, in an electrically writable and erasable non-volatile semiconductor memory device according to another aspect of the present invention, a plurality of electrically writable non-volatile semiconductor memory cells arranged in rows and columns, A decoder circuit that sets at least one of the memory cells to a selected state and another memory cell to a non-selected state; a writing unit that writes to the selected memory cell via the decoder circuit; and a decoder circuit Erase means for erasing the selected memory cell, read means for reading from the selected memory cell via the decoder circuit, and non-selected memory cell when writing to the selected memory cell First detecting means for detecting a change in the threshold voltage of the non-selected memory cell caused by the voltage applied to the memory cell And second detecting means for detecting a change in the threshold voltage of the memory cell in the non-selected state by the voltage applied to the memory cell in the non-selected state during the erasing of the memory cell in the selected state. The threshold voltage of the memory cell in the non-selected state is the value before the change or its The detection means restores the threshold voltage of the memory cell in the selected state to a value larger than the minimum number required for reading the stored information of the memory cell. By providing the detection level and comparing the threshold voltage of the memory cell, information for detecting a change in the threshold voltage is extracted in addition to the stored information of the memory cell.

In a preferred aspect of the present invention, the detecting means obtains information on whether or not the threshold voltage value of the memory cell in the non-selected state is changed as compared with that at the time of writing or erasing. A threshold voltage detection level that is at least twice as many as the minimum number required to read the stored information in the cell is provided, and the threshold voltage value of the non-selected memory cell is increased as compared with that during writing or erasing. In order to obtain information on whether or not the threshold voltage has dropped, a threshold voltage detection level that is at least three times the minimum number required to read the stored information in the memory cell is provided, and the detection level and the threshold voltage of the memory cell are set. By comparing with the stored information of the memory cell and extracting information for detecting a change in the threshold voltage, the presence or absence of the change in the threshold voltage of the memory cell and the threshold value are detected. So as to obtain the information about the value before the change in pressure.

[0016]

With the above-described structure, the change in the threshold voltage of the non-selected memory cell is detected after the write or erase of the selected memory cell at the time of writing or erasing, and the change amount is predetermined. When it becomes larger than the value of, the threshold voltage is restored by writing or erasing in the non-selected memory cell. By including these detecting means and restoring means, it becomes possible to prevent the destruction of the stored information due to the disturb in advance.

[0017]

1 shows a circuit block diagram of a first embodiment of the present invention. In FIG. 1, FROM is an electrically rewritable nonvolatile semiconductor memory device, and has a storage capacity of (1048576 words × 16 bits = 16777216 bits), for example. Address inputs A0, A1, ..., A19, chip enable signal CEB, output enable signal OE
B, the write enable signal WEB, the power supply voltage VCC and the ground voltage VSS are input signals from the outside of the FROM, and the data input / output D0, D1, ..., D15 are external data during writing, that is, during writing and erasing. It is an input, and when reading, it is a data output to the outside.
In addition to writing and erasing, the circuit of the embodiment of FIG.
A verify circuit for write and erase verify and disturb is shown.

In FIG. 1, DVCNT is a device control command identification circuit, and includes a write enable signal WEB and a chip enable signal CE in the operation mode of FROM.
B, the output enable signal OEB, and the plurality of internal data inputs DATIN are input, and the control signal CNT1 and the plurality of control signals CNT2 are output. For example, CNT2 includes a control signal indicating a write mode or an erase mode.

RCNT is a chip / output selection state control circuit, which receives a chip enable signal CEB, an output enable signal OEB and a control signal CNT1 as control inputs, and uses a power down signal PDQ and an output buffer activation signal DOE.
Output N.

The write state control circuit WCNT is CNT
2, the timer end signal S2, the disturb verify data output signal DTC, and the write / erase verify data output signal PENG as control inputs, and the write signal PR.
G, erase signal ERS, write verify signal PVF,
The erase verify signal EVF, the disturb data verify signals DVF and DVF2, the address counter up signal AUP, the timer start signal S1, the address latch signal LTA, and the data latch signal LTD are output.

The timer circuit is a write state control circuit WC.
The timer start signal S1 is received from NT, and after a lapse of a predetermined time, the address up clock signal S3 is output to the address up counter AUP, and the write state control circuit WC
The timer end signal S2 is output to NT.

The address buffer / latch circuit ADB is
, A19 are input, the power-down signal PDQ is a control input, the address latch signal LTA is a latch input, and a plurality of internal address signals A are input.
Let X be the output.

The column decoder RDEC receives the internal address signal AX as a decode input, receives a write signal PRG, an erase signal ERS, a plurality of high voltage signals VP and a plurality of negative voltage signals VN, and a write / erase verify voltage signal VVF. A plurality of (for example, 4096) word line signals WL are output.

The row decoder CDEC receives an internal address signal AX, a write signal PRG, an erase signal ERS, a plurality of high voltage signals VP and a plurality of negative voltage signals VN, and receives a plurality (for example, 256) of multiplexer selection signals CX. Output.

The memory block MBLK is, for example, 167
77216 memory cells are formed, and a word line, a bit line, and a memory cell source line are connected to one memory cell.

The multiplexer MPX receives the multiplexer selection signal CX as an input and inputs and outputs a plurality (for example, 4096) of bit lines BL and a plurality (for example, 16) of internal data lines IO. A part of the negative voltage signal VN is input to the substrate terminals of the transistors of MBLK and MPX.

Write / erase verify voltage generation circuit V
The FGEN receives the write verify signal PVF and the erase verify signal EVF and outputs the write / erase verify voltage signal VVF.

The positive high voltage charge pump circuit PCP receives the write signal PRG and the erase signal ERS and outputs the positive charge pump voltage signal POUT1.

The negative high voltage charge pump circuit NCP receives the write signal PRG and the erase signal ERS and outputs the negative charge pump voltage signal POUT2.

The positive high voltage control circuit HVCNT receives the positive charge pump voltage signal POUT1 and outputs a plurality of positive high voltage signals VP.

The negative high voltage control circuit NVCNT receives the negative charge pump voltage signal POUT2 and outputs a plurality of negative high voltage signals VN.

Memory cell array source line control circuit ASC
The NT receives the write signal PRG, the erase signal ERS, and a plurality of positive high voltage signals VP as inputs, and inputs and outputs the memory cell source line signal AS.

The bit line voltage control circuit BLCNT receives a plurality of positive high voltage signals VP, a plurality of negative high voltage signals VN and an erase signal ERS as input, and receives the bit line load voltage signal BD.
Output IS.

The bit line load circuit BLLD receives the bit line load voltage signal BDIS and the erase signal ERS and outputs a plurality of bit lines BL.

The sense amplifier circuit SAMP receives the internal data line IO as a data input, the power down signal PDQ and the disturb verify data output signals DVF and DVF2 as control inputs, and outputs the sense amplifier output signal SOUT.

Disturb verify data detection circuit D
The VFC receives the sense amplifier output signal SOUT as a data input, the disturb verify voltage signal DVF as a control input, and outputs the disturb verify data output signal DTC.

The write / erase verify data coincidence detection circuit VEOR has a sense amplifier output signal SOUT and an internal data input DATIN as data inputs, a write verify signal PVF and an erase verify signal EVF as control inputs, and a write / erase verify data output signal. PENG is output.

The data input / output buffer DIB has the output buffer activation signal DOEN and the power down signal PDQ as control inputs, the data latch signal LTD as latch inputs, and the sense amplifier output signal SOUT as data inputs.
The internal data input DATIN is used as a data output, and the data input / output signals D0, D1, ..., D15 are used as input / output.

The data program circuit DPRG uses the internal data input DATIN as a data input and receives the write signal P.
The RG and erase signal ERS are used as control inputs, and the internal data line IO is used as data output.

2 to 5 are schematic diagrams showing the circuit diagram of this embodiment. FIG. 2 is the upper left portion of the circuit, FIG. 3 is the lower left portion of the circuit, FIG. 4 is the upper right portion of the circuit, and FIG. 5 is the lower right portion of the circuit. Are shown respectively.

In the examples of FIGS. 2 to 5, the number of memory cells, the number of addresses, and the number of data inputs / outputs are reduced from those of the example of FIG. is there. However, in the example of FIG. 1 and the examples of FIGS. 2 to 5, the circuit name and the signal name have almost the same meaning.
2 to 5 are different from the example of FIG. 1 in that the device control command identification circuit DVCNT, the chip / output selection state control circuit RCNT, and the write state control circuit WCN of the example of FIG.
T, write / erase verify voltage generation circuit VFGE
N, disturb verify data detection circuit DVFC,
Program / erase verify data match detection circuit VEO
R, timer TIM and address up counter AUP
CT is omitted. Further, in the example of FIG. 1, there is only one type of erasing signal, but in the examples of FIGS. 2 to 5, two types of erasing signals and erasing methods are described. Further, in the data input / output buffer DIB in the example of FIG. 1, the data input buffer is omitted, and the data output buffer corresponds to the output buffer DBF of FIG. The input DIN of the data program circuit DPRG of FIG. 5 is one of DATIN of FIG.
Corresponds to a book.

2 to 5, the BEROM is an electrically rewritable nonvolatile semiconductor memory device, and addresses are externally input to address input terminals A0, A1, A2 and A.
3, the internal input data is input from the data input terminal DIN of the data program circuit, and the output data is output from the output terminal DO. BEROM is ADB
1, column buffers RDEC, DEC6, DEC7, which are composed of address buffers ADB2, ADB3 and ADB4, and DEC1, DEC2, DEC3 and DEC4.
Row decoding circuit CDE including DEC8 and DEC9
.., MC16, memory block MBLK, multiplexer MPX, data program circuit DPRG, sense amplifier circuit SAM.
P, output buffer circuit DBF, positive high voltage charge pump circuit PCP, negative voltage charge pump circuit NCP, positive high voltage control circuit HVCNT, negative voltage control circuit NVCNT, memory cell source line voltage control circuit ASCNT, bit line voltage control circuit BLCNT, bit It comprises a line load circuit BLLD, oscillators OSC1, OSC2 and OSC3, and other logic circuits. As a whole power source, a positive power source (for example, 5 V) from the outside is supplied from the terminal VDD, and a ground voltage is supplied from the terminal VS.
Supplied by S.

The connection relation of the BEROM is the address terminal A.
0 is connected to the input of the address buffer ADB1, the address terminal A1 is connected to the input of the address buffer ADB2, the address terminal A2 is connected to the input of the address buffer ADB3, and the address terminal A3 is connected to the input of the address buffer ADB4. Outputs AX0 and A of address buffer ADB1
X0B is an input of a logical product inverting gate of the column decoder RDEC (hereinafter referred to as "non-logical product gate"), and outputs AX1 and AX1B of the address buffer ADB2 are column decoders R.
The outputs AY0 and AY0B of the address buffer ADB3 are input to the inverting gate of the logical product of the DEC and the row decoder CD.
Address buffer AD is input to the non-logical product gate of EC
The outputs AY1 and AY1B of B4 are connected to the inputs of the non-AND gates of the row decoder CDEC.

The column decoder RDEC is DEC1, DEC
2, DEC3 and DEC4 are composed of four circuits, and each circuit is the same.

The DEC1 is a 2-input non-logical product gate ND1 which receives the outputs AX0B and ABX of the address buffer ADB1 and AX1B of the address buffer ADB2, and an inverting gate of two 2-input logical sums (hereinafter referred to as "non-logical sum gate") NR1. , N
R2, inverter IV1, positive high voltage switch circuit HVS
ND consisting of W1 and negative voltage switch circuit NVSW1
The output N1 of 1 becomes 1 input of NR1 and NR2, and NR
ERSB1 is input as the other input of 1, and CLK1 is input as the other input of NR2. The output N2 of NR1 is input to IV1 and the output N3 of IV1 is input to HVSW1.
Two outputs N4 are connected to one input of NVSW1.

HVSW1 is N3, the high voltage signal VPP
1, WEL1 and ISO1 are input, and the output is connected to the column line (word line) WL0 of the memory block MBLK.

NVSW1 receives N4, WEL2 and negative voltage signal VPN1 as inputs, and its output is connected to the same column line WL0 as the output of HVSW1.

DEC2, DEC3 and DEC4 are DEC
Although the circuit is the same as that of 1, the combination of the inputs from the address buffers ADB1 and ADB2 to the non-logical product gate and the output column line are different, and the output of DEC2 is WL1 and the output of DEC3 is WL2. , DEC4 outputs are connected to WL3, respectively.

The row decoder CDEC is DEC5, DEC
It is composed of four circuits of 6, DEC7 and DEC8, and each circuit is the same.

DEC5 receives the output AY0B of the address buffer ADB3 and the output AY1B of ADB4 as input 2
Input non-logical product gate ND2, two 2-input non-logical sum gates NR6 and NR17, inverter IV6, positive high voltage switch circuit HVSW2 and negative voltage switch circuit NVSW3
And the output N5 of ND2 is 1 of NR6 and NR17.
It becomes an input, and N18 is NR17 as another input of NR6.
CLK3 is input as the other input. Output N of NR6
15 is input to IV6, output N16 of IV6 is HVSW
The output N17 of NR17 is 1 of NVSW3.
Connected to input.

HVSW2 is N16, a high voltage signal VPP
1, WEL5 and ISO3 are input, and the output is connected to the row line selection signal C1 of MPX.

The NVSW3 receives N17, WEL6 and the negative voltage signal VPN1 as its inputs, and its output is connected to the same row line selection signal C1 as the output of the HVSW2.

DEC6, DEC7 and DEC8 are DEC
5 has the same circuit as that of FIG. 5, but the combination of inputs from the address buffers ADB3 and ADB4 to the non-logical product gate and the row line selection signal to be output are different from each other.
The output of C6 is the row line selection signal C2, the output of DEC7 is the row line selection signal C3, and the output of DEC8 is the row line selection signal C4.
Connected to each.

The memory block MBLK is MC1, MC
.., MC16, each of which has a drain terminal, a source terminal, a control gate terminal and a floating gate, and further has a substrate terminal common to each memory cell. Each memory cell has, for example, a drain region and a source region on a semiconductor substrate surface, a thin oxide film on the semiconductor substrate surface between the drain region and the source region, and an upper portion of the thin oxide film. And a floating gate made of, for example, polycrystalline silicon, and a control gate made of, for example, polycrystalline silicon on the floating gate via an interlayer insulating film. The drain region is electrically connected to the drain terminal, the source region is electrically connected to the source terminal, the control gate is electrically connected to the control gate terminal, and the substrate is electrically connected to the substrate terminal. M
The control gate terminals of C1, MC2, MC3, and MC4 are on the column line WL0, and the control gate terminals of MC5, MC6, MC7, and MC8 are on the column line WL1, MC9, MC10, MC1.
1 and the control gate terminals of MC12 are connected to the column line WL2, MC
The control gate terminals of 13, MC2, MC3, and MC4 are on the column line WL4, and the drain terminals of MC1, MC5, MC9, and MC13 are on the column line BL0, and MC2, MC6, and MC10.
And the drain terminals of MC14 are connected to the column line BL1, MC3,
The drain terminal of MC7, MC11 and MC15 is the column line B.
The drain terminals of MC4, MC8, MC12, and MC16 of L2 are connected to the column line BL3. That is, the memory cells are arranged in 4 columns × 4 rows. MC1, MC
The source terminals of the memory cells MC2, ..., MC16 are commonly connected to the memory source line AS, and MC1, MC2 ,.
The substrate terminal of the MC16 memory cell is the substrate voltage signal VSU.
Connected to B.

The multiplexer MPX is, for example, an N-channel enhancement type MOS transistor M1,
It consists of M2, M3 and M4, and the drain of M1 is the row line B
L0, gate to row selection signal C1, drain of M2 to row line BL1, gate to row selection signal C2, drain of M3 to row line BL2, gate to row selection signal C3, M4
Is connected to the row line BL3 and the gate is connected to the row selection signal C4. The substrates of M1, M2, M3 and M4 are connected to the substrate voltage signal VSUB, and M1, M2, M3
The sources of M4 and M4 are connected to the internal data line DIO.

The data program circuit DPRG includes a 2-input non-OR gate NR4, inverters IV2, IV3 and IV4, N-channel enhancement type MOS transistors M15, M16, M10 and M11 and a P-channel enhancement type MOS transistor M1.
7, M18 and M9. Input 1 of NR4
The end is connected to the data input terminal DIN, the other end is connected to WRB, the output N6 of NR4 is connected to the input of IV2, and IV
The second output N7 is connected to the input of IV3 and the gate terminal of M15. The output N8 of IV3 is connected to the gate terminal of M16, the drain terminal of M16 is connected to N10, and N10 is further connected to the gate terminal of M17, the drain terminal of M18, the gate terminal of M9, and the gate terminal of M10.
The drain terminal of M15 is connected to N9, and N9 is further connected to the drain terminal of M17 and the gate terminal of M18.
The source terminals of M17, M18 and M9 are high voltage signals VP.
On P3, the board terminals of M17, M18 and M9 are also VP
The sources of M15, M16 and M11 are connected to P3 and are connected to the ground terminal VSS by M15, M16, M10 and M11.
The substrate terminal of is also connected to the ground terminal VSS. IV4
Is connected to WRB, the output WR of IV4 is connected to the gate terminal of M11, the drain terminal of M11 is connected to N19, N
Reference numeral 19 is connected to the source terminal of M10, and the drain terminal of M10 and the drain terminal of M9 are connected to the internal data line DIO.

Memory source line voltage control circuit ASCNT
Is composed of inverter circuits IV5 and IV6, 2-input non-logical sum gate NR5, 2-input non-logical product gate ND3, N-channel enhancement MOS type transistor M13, P-channel enhancement MOS type transistor M12 and positive high voltage switch HVSW4. The input of IV6 is to PRGB, the output N11 of IV6 is to one end of the input of NR5, the other end of the input of NR5 is to ERSB2, ND3
One end of the input is connected to PRGB and the other end is connected to ERSB2. The output N12 of NR5 is a positive high voltage switch HV.
One input of SW4, the output N14 of ND3 is connected to the input of IV5, and the output N15 of IV5 is connected to the gate terminal of M13. HVSW4 is a high voltage signal VPP2 and N12
Is an input, N13 is an output, and N13 is connected to the gate terminal of M12. The source terminal of M12 is VPP
2, the drain terminal of M12 and the drain terminal of M13 are connected to the memory source line AS. The substrate terminal of M12 is connected to VPP2, and the source terminal and substrate terminal of M13 are connected to the negative voltage signal VPN2.

The bit line load circuit BLLD includes N-channel enhancement MOS type transistors M5, M6 and M.
7 and M8, the drain terminal of M5 is the column line (bit line) BL0, the drain terminal of M6 is the column line BL1,
The drain terminal of M7 is connected to the column line BL2, the drain terminal of M8 is connected to the column line BL3, and the gate terminals of M5, M6, M7 and M8 are all connected to the bit erase signal ER2.
The source terminals of 6, M7 and M8 are both connected to BDIS, and the substrate terminals of M5, M6, M7 and M8 are connected to the substrate voltage signal VSUB.

The bit line voltage control circuit BLCNT is composed of a positive high voltage switch HVSW3 and a negative voltage switch NVSW2, and the input of HVSW3 is the outputs ER2B, WEL3, ISO2 of the inverter IV8 and the high voltage signal VP.
Input P3, output BDIS, NVSW
2 receives the outputs CLK2 and WEL4 of the oscillator OSC2 and the negative voltage signal VPN3, and outputs BDIS.

The write signal PRG has one input of the positive high voltage charge pump circuit PCP, one input of the negative voltage charge pump circuit NCP, one input of the negative voltage control circuit NVCNT,
Positive high voltage control circuit HVCNT 1 input, oscillator OS
C1 input, 3 input Non-OR gate NR3 1 input, 2
It is connected to one input of the input disjunction gate NR9 and the input of the inverter circuit IV7.

The block erase signal ER1 is supplied with 1 input of the address buffer ADB3, 1 input of ADB4, 1 input of the positive high voltage charge pump circuit PCP, and the positive high voltage control circuit H.
VCNT 1 input, negative voltage control circuit NVCNT 1 input, negative voltage charge pump circuit NCP 1 input, 3 input non-logical sum gate NR3 1 input, 2 input non-logical sum gate NR8 1 input, NR7 1 input And oscillator OSC
2 and the inputs of OSC3.

The bit erase signal ER2 is a 1-input of the positive high voltage charge pump circuit PCP, the positive high voltage control circuit HVC.
1 input of NT, 1 input of negative voltage control circuit NVCNT, input to gate terminals of M5, M6, M7 and M8 of bit line load circuit BLLD, 1 of 3 input non-OR gate NR3
It is connected to one input of an input, two-input non-logical sum gate NR9, one input of NR8, one input of NR7 and input of an inverter IV8.

The output WRB of NR3 is 1 input of NR4, I
The output E of NR8 is connected to the input of V4, the one input of the sense amplifier circuit SAMP and the one input of the output buffer DBF.
RSB1 is connected to one input of NR1 and output N of NR9
18 is connected to one input of NR6 and output ERS of NR7
B2 is connected to one input of NR5 and ND3, OSC1
Output CLK1 is connected to 1 input of NR2, and OSC2
Output CLK2 is connected to 1 input of NVSW2
The output CLK3 of C3 is connected to one input of NR17.

The positive high voltage charge pump circuit PCP is P
RG, ER1 and ER2 are input, POUT1 is output, and the negative voltage charge pump circuit NCP is PRG and E.
R1 is an input, POUT2 is an output, and the positive high voltage control circuit HVCNT is POUT1, PRG, ER1 and ER.
2 as input, VPP1, VPP2, VPP3, WEL
1, WEL2, WEL3, WEL4, WEL5, WEL
6, ISO1, ISO2 and ISO3 are output, the negative voltage control circuit NVCNT receives POUT2, PRG, ER1 and ER2 as inputs, and outputs VPN1, VPN2, VPN3 and VSUB.

The sense amplifier circuit SAMP receives the internal data line DIO as input, WRB as control input, and SOUT.
Is output, the output buffer DBF receives SOUT as input, WRB as control input, and output terminal DO as output.

Next, writing to the BEROM of this embodiment,
The operation of erasing and reading will be described with reference to FIGS. The BEROM of this embodiment has 16 bits (4 columns x 4 rows).
Writing to the memory cell of with a data width of 1 bit,
The nonvolatile semiconductor memory device performs first erasing, second erasing and reading. There are A0 and A1 as column line selection addresses, and A2 and A3 as row line selection addresses.
There is.

Table 1 below shows an example of voltage application to the memory cell of the system of this embodiment. The operation of each mode will be described with reference to Table 1 and FIGS. Writing is started by changing the write signal PRG from a low (“L”) level to a high (“H”) level (ER1 = ER2 = “L” remains), and the negative voltage charge pump circuit NCP is set to “PRG”. The operation starts at the H "level. NCP is, for example, from the power supply voltage (for example, 5V) and ground voltage (for example, 0V) −
This is a circuit for generating a negative voltage of 8V, and an example of the circuit is shown in FIG.

[0068]

[Table 1]

The negative voltage control circuit NVCNT is a circuit for controlling a negative voltage, and its output is 0V or a negative voltage (for example, -8V). PRG = “H”, ER1 = ER2
== "L", the output of NVCNT is, for example, VPN1 =-
8V, VPN2 = VPN3 = VSUB = 0V.

The positive high-voltage charge pump circuit PCP is a circuit for generating a positive high voltage of, for example, 12 V based on the power supply voltage VDD and the ground voltage. An example of the circuit is shown in FIG. PRG = “H”, ER1
= ER2 = “L”, positive high voltage charge pump circuit P
CP operates and the output POUT is 12V, for example.

The positive high voltage control circuit HVCNT is a circuit for controlling the positive high voltage, and its output is between 0V and the positive high voltage (for example, 12V). PRG = “H”,
When ER1 = ER2 = “L”, the output of HVCNT is, for example, VPP1 = WEL5 = WEL6 = 12V, VPP2
= VPP3 = WEL3 = WEL4 = ISO1 = 5V, I
SO2 = ISO3 = WEL1 = WEL2 = 0V.

For example, when the memory cell MC1 is selected,
For the address, input A0 = A1 = A2 = A3 = “L”,
As a result, the output of the 2-input non-logical product gate ND1 of the column decoder DEC1 becomes "L". The oscillator OSC1 starts oscillating when the input PRG = “H”, and is output to CLK1 (for example, an amplitude of 5 V in a cycle of 30 MHz). The output of the 2-input non-OR gate NR8 becomes "H", the output N3 of the inverter IV1 becomes "H", and the positive high voltage switch HVSW1 is turned off. The output N4 of the 2-input NOR gate NR2 is the outputs N1 and O of ND1.
Oscillation is performed according to the level of the output CLK1 of SC1. As a result, the negative voltage switch NVSW1 is turned on, and the voltage of VPN1, that is, −8 V is applied to the column line (word line) WL0. For the column lines WL1, WL2 and WL3, for example, WL1 = WL2 = WL3 = 0V because both the positive voltage switch and the negative voltage switch of the row decoders DEC2, DEC3 and DEC4 are turned off. With the same operation, in the row decoder DEC5, the positive high voltage switch HVSW2 is turned on and the negative voltage switch NVSW is turned on.
3 is turned off, the row line selection signal C1 is set to VPP.
The voltage becomes 1, that is, 12V, and C2 = C3 = C4 = 0V.

As write data, for example, when "L" is input to the data input terminal DIN, write is performed,
When writing is not performed when “H” is input, and when erasing is performed during erasing, PRG = “H”, ER
When 1 = ER2 = “L”, WRB becomes “L”, and in the data input buffer DIB, DIN = “L”, so N7 = “H”, N8 = “L”, and the internal data line DIO Outputs the same voltage as VPP3, that is, 5V.
When DIN = “H”, the internal data line DIO becomes 0V, for example. In the multiplexer MPX, since only the transistor M1 is in the ON state, the column line BL0
When DIN = “L”, for example, 5V is applied and DIN =
When it is "H", for example, 0V is applied. BL1, BL2
And BL3 become 0V, for example.

At the time of writing, the memory cell source line voltage control circuit ASCNT outputs the output PR of the inverter IV7.
Since GB = “L” and ERSB2 = “H”, the positive high voltage switch HVSW4 is turned on and its output N
13 has the same voltage as VPP2, that is, 5V. Further, the output N15 of the inverter IV5 becomes "L", both the transistors M12 and M13 are turned off, and the memory source line AS is electrically opened. Further, in the bit line load circuit BLLD, since the gate voltages of the transistors M5, M6, M7 and M8 are "L", M5, M6, M7 and M8 are turned off.

Therefore, at the time of writing, the control gate terminal of the selected memory cell MC1 is, for example, -8V, the drain terminal is 5V or 0V, the source terminal is in an open state, the substrate terminal is 0V, and 5V is applied to the drain terminal. In this case, the voltage difference between the drain terminal and the control gate terminal induces a high electric field in the thin oxide film between the floating gate and the drain region of the memory cell, and the FN injection causes electrons to flow from the floating gate to the drain region. Is released. As a result, the threshold value of the memory cell is lowered (for example, from 7V to 2V), and the memory cell is in the written state. Unselected memory cell M
Since a sufficient potential difference for causing FN injection is not applied to C2, ..., MC16, no data is written (in order to cause FN injection, a potential difference between the drain and the control gate of 11 V or more is required).

In the first erase, the block erase signal ER1 = "H", PRG = ER2 = "L", the positive high voltage charge pump circuit PCP and the negative voltage charge pump circuit NCP start operating, and for example, POUT1 =. 12
V and POUT2 = -8V. The output of the positive high voltage control circuit is, for example, VPP1 = WEL1 = WEL2 = 10V, V
PP2 = VPP3 = ISO2 = ISO3 = 5V, ISO
1 = WEL3 = WEL4 = WEL5 = WEL6 = 0V, and the output of the negative voltage control circuit NVCNT is VPN, for example.
1 = VPN2 = VPN3 = VSUB = −8V.

A0 = A1 is added to the address as in writing
= A2 = A3 = “L” is input, the column decoder DE
The positive high voltage switch HVSW1 of C1 is turned on,
The negative voltage switch NVSW1 is turned off, and the same voltage as VPP1, that is, 10 V is applied to the column line (word line) WL0. The unselected column lines WL1, WL2, WL3 are set to 0V, for example. Since the block erase signal ER1 becomes "H", the outputs of the address buffers ADB3 and ADB4 are AY0 = regardless of the address values of A2 and A3.
AY0B = AY1 = AY1B = “H”, the positive high voltage switches HVSW2 of the row decoders DEC5, DEC6, DEC7 and DEC8 are turned off, the negative voltage switch NVSW3 is turned on, and the row line selection signals C1 and C.
2, C3 and C4 have the same voltage as VPN1, that is, -8V.

At the time of the first erase, the bit line voltage control circuit B
In the LCNT, the positive high voltage switch HVSW3 is in the off state, the negative voltage switch NVSW2 is in the on state, and the output BDIS has the same voltage as the VPN3, that is, −8V.
Is applied. The gates of the transistors M5, M6, M7, and M8 of the bit line load circuit BLLD are "L", but the substrate is VSUB = -8V, so that it is turned on and the row lines (bit lines) BL0, BL1, BL2, and BL
The same voltage of −8 V as the substrate voltage is applied to 3. Further, a negative voltage is applied to the drains of the transistors M1, M2, M3, and M4 of the multiplexer MPX, but the negative voltage is also applied to the gates, so that M1, M2, M3, and M4 are turned off. The internal data line DIO becomes 0V or 5V, for example, depending on the input data DIN.

In the first erasing, the erasing cannot be performed in units of one memory cell, and the memory cells MC1, MC2, MC3 and MC4 connected to the selected column line WL0 are erased. For example, 10V is applied to the control gate terminals of the memory cells MC1 to MC4, and −8V is applied to the drain terminal, the source terminal, and the substrate terminal, and FN injection occurs due to the potential difference between the substrate and the control gate, and electrons are emitted. It is injected from the substrate into the floating gate. As a result, the threshold values of the memory cells MC1, MC2, MC3, and MC4 rise (for example, from 2V to 7V) and the erased state is set. The first erase method is also referred to as word line erase, block erase, or sector erase.

At the time of the second erase, the bit erase signal ER2 = "H", PRG = ER1 = "L", the positive high voltage charge pump circuit PCP starts the operation, and the output PO
UT1 becomes 12V, for example. The negative voltage charge pump circuit NCP does not operate, and the output POUT2 becomes 0V, for example. The output of the positive high voltage control circuit HVCNT is, for example, VP.
P1 = WEL1 = WEL2 = 12V, VPP2 = VPP
3 = WEL3 = WEL4 = WEL5 = WEL6 = 5V,
ISO1 = ISO2 = ISO3 = 0V, and the output of the negative voltage control circuit NVCNT is, for example, VPN1 = VPN2 =
VPN3 = VSUB = 0V. Address A0 = A1
= A2 = A3 = “L” is input, the column decoder D
The positive high voltage switch HVSW1 of EC1 is turned on, the negative voltage switch NVSW1 is turned off, and the same voltage as VPP1, that is, 12 V is applied to the column line WL0. The column lines WL1, WL2, WL3 are not selected and are, for example, 0
It becomes V. Further, the positive high voltage switch HVSW4 of the row decoder DEC5 is turned on, the negative voltage switch NVSW3 is turned off, and the same voltage 12V as VPP1 is applied to the row line selection signal C1. The unselected row line selection signals C2, C3 and C4 are, for example, 0V.

At the time of the second erase, the memory source line voltage control circuit ASCNT sets the ERSB at PRGB = “H”.
Since 2 = “L”, the positive high voltage switch HVSW4 is turned off, the node N13 becomes “L”, and the output N15 of the inverter IV5 also becomes “L”. Therefore, the transistor M13 is off, M12 is on, and the memory source line AS has the same voltage as VPP2, for example, 5V. When "H" is input to the data input terminal DIN, the internal data line DIO becomes 0V, and when "L" is input to DIN, DIO becomes the same voltage as VPP3, for example, 5V. At this time, in the bit line voltage control circuit BLCNT, the positive high voltage switch HVSW3 is in the on state and the negative voltage switch N
VSW2 is turned off, and output BDIS is VPP3
The same voltage as, for example, 5 V is applied. Further, the transistors M5, M6, M7 and M of the bit line load circuit BLLD are
Since the gate input of 8 is "H", these transistors are turned on. Since the transistor M1 is turned on in the multiplexer MPX, when "H" voltage is input to DIN, VPP3 changes to BDIS,
A current flows to the ground terminal via BL0 and DIO. By setting the resistance value of the transistor M5 at this time to be sufficiently larger than the resistance value of the transistor M1, the row line BL0 can be set to almost 0V. Row lines BL1, B
Since L2 and BL3 have no current flow path, BDI
The voltage is set to be almost the same as S, for example, 5V.

Therefore, 12 V is applied to the control gate terminal of the selected memory cell MC1 and 5 V is applied to the source electrode.
V is applied, 0 V is applied to the drain electrode, and 0 V is applied to the substrate electrode.
Electrons are injected from the channel of the memory cell to the floating gate. As a result, the threshold value of the memory cell MC1 becomes high (for example, from 2V to 7V). 12V is also applied to the control gate terminals of the unselected memory cells MC2, MC3, and MC4, but the voltage of the drain electrode and the source electrode is as high as 5V, and there is no potential difference between the drain and the source, so that FN injection is also performed. HE injection does not occur either. Other unselected memory cells MC5, MC9 and MC
13, the control gate voltage is 0V, the source electrode is 5V,
Since the drain electrode has 0 V, the potential difference between these memory cells is small in the off state, so that neither FN injection nor HE injection is performed. Therefore, only the selected memory cell can be erased,
Moreover, the presence or absence of erasure can be controlled according to the input data.

At the time of reading, PRG = ER1 =
ER2 = "L", positive high voltage charge pump circuit P
CP and the negative voltage charge pump circuit NCP do not operate,
For example, POUT1 = POUT2 = 0V. The output of the positive high voltage control circuit HVCNT is, for example, VPP1 = V
PP2 = VPP3 = WEL1 = WEL2 = WEL3 = W
EL4 = WEL5 = WEL6 = 5V and ISO1 = ISO
2 = ISO3 = 0V. Negative voltage control circuit NVCN
The output of T is, for example, VPN1 = VPN2 = VPN3 = V
SUB = 0V. At this time, 3-input non-OR gate NR
The output WRB of 3 becomes "H", the data program circuit DPRG becomes inactive, and the sense amplifier circuit SA
MP and the output buffer DBF are activated. When the address input is, for example, A0 = A1 = A2 = A3 = “L”, the column line WL0 is, for example, 5V, and when the memory cell MC1 is in a written state (for example, the threshold voltage is 2V), MC1 is input.
Is on, for example from SAMP to DIO and BL
A current flows through 0 (in this case, the voltage of BL0 is supplied from SAMP). Also, the memory cell MC
When 1 is erased (for example, the threshold voltage is 7V), MC1 is in the off state, and the current does not flow. The presence or absence of this current is detected and amplified by the sense amplifier circuit SAMP and output to the output terminal DO via the output buffer DBF.

FIG. 6 shows a configuration example of the circuit of the positive high voltage switch shown in the embodiments of FIGS.

HVSW-1 in FIG. 6 is, for example, N-channel enhancement MOS type transistors M20 and M2.
1. P-channel enhancement MOS type transistors M22 and M23, P-channel depletion MOS
The transistor M24, a switch input terminal IN, a positive high voltage input terminal VPP, a negative voltage blocking signal input terminal ISO, a substrate input terminal WEL, an output terminal OUT, a power supply terminal and a ground terminal. N-channel enhancement MOS
The threshold value of the p-type transistor is, for example, 0.8 V, and P
The threshold value of the channel enhancement MOS type transistor is, for example, -0.8V, and the threshold value of the P channel depletion MOS type transistor is, for example, 2V.

The wiring relationship of HVSW-1 is as follows: the drain terminal of M20 is IN, the gate terminal of M20 is power supply voltage,
The source terminal of M20 is connected to the node N101, and M2
The gate terminal of 1 is connected to the node N101, the drain terminal of M21 is connected to the node N102, the source terminal of M21 is connected to the ground terminal, and the gate terminal of M22 is connected to the node N102.
The drain terminal of M22 is connected to node N101,
Is connected to VPP, the source terminal of M24 is connected to the node N102, the gate terminal of M24 is connected to ISO, and the drain terminal of M24 is connected to OUT. M20 and M
The substrate terminal of 21 is connected to the ground terminal, the substrate terminals of M22 and M23 are connected to VPP, and the substrate terminal of M24 is connected to WEL.

The operation of HVSW-1 includes a switch operation at a normal power supply voltage, a switch operation at a positive high voltage, and a switch operation at the time of blocking a negative voltage. When the power supply voltage is, for example, 5 V, the switch operation at the normal power supply voltage is VPP.
Is also 5V, and ISO = 0V and WEL = 5V. At this time, if IN = 5V, N101 = 5V, N102
= 0V and OUT = 0V. If IN = 0V, then OUT = 5V. The switch operation at a positive high voltage is ISO = 0V and WEL = 12V when the power supply voltage is 5V and the VPP is 12V, for example. IN this time
= 5V, N1 = 12V, N2 = 0V, and O
UT = 0V. If IN = 0V, OUT = 12
It becomes V. The switch operation at the time of blocking the negative voltage is such that when a negative voltage is applied to OUT, OUT and node N1
This is an operation for electrically insulating 02. Power supply voltage is 5V, VPP is 5V or 12V
Then, when IN = 5V, ISO = 5V, WEL = 0V, the node N101 is 5V or 12V, and the node N102 = 0.
V, and M24 is turned off even when a negative voltage is applied to OUT.

The HVSW-2 of FIG. 7 is the HVSW-1 of FIG.
On the other hand, the transistor, the input terminal, and the wiring necessary for the switch operation when blocking the negative voltage are omitted, and the other transistors, the wiring, and the operation are exactly the same as those of HVSW-1 in FIG.

FIG. 8 shows a configuration example of the negative voltage switch shown in the embodiments of FIGS.

NVSW of FIG. 8 is, for example, P-channel enhancement MOS type transistors M29, M30 and M.
31, capacitance C1, clock input terminal CLK,
It has a negative voltage input terminal VPN, a substrate voltage terminal WEL, and an input / output terminal IOUT. The threshold value of the P-channel enhancement MOS type transistor is, for example, -0.8V.
Is.

The connection relationship of NVSW is C at one end of C1.
LK, the node N201 at the other end of C1, the node N201 at the gate and drain terminals of M30, and M3.
The source terminal of 0 is IOUT, the source terminal of M29 is VPN, the gate terminal of M29 is IOUT, M2
The node N201 is connected to the drain terminal of 9, the node VPN is connected to the source terminal of M31, and the IOUT is connected to the gate terminal and drain terminal of M31. M29, M30
WEL is connected to the substrate terminals of M31 and M31.

The operation of NVSW in FIG. 8 may be in the switch-off state, that is, when a positive voltage is applied to IOUT, or in the switch-on state, that is, when a negative voltage is output to IOUT. In the former case, CLK is fixed to "L" or "H", VPN is 0V, and WEL is 5V or 12V, for example. Even if 5V or 12V is applied to IOUT at this time, M29, M30, and M31 are in the off state, and VP
N and IOUT are electrically isolated. In the latter case,
CLK oscillates (for example, a period of 30 MHz and an amplitude of 5 V)
And a negative voltage, for example -8V is applied to VPN,
EL is, for example, 0V. Since the node N201 is capacitively coupled through CLK and C1, the value of C1 and CL
A charge corresponding to the amplitude of K is induced in N201,
Voltage fluctuates greatly in the negative direction (positively, the WEL voltage is 0 V
Therefore, since a forward diode is formed from the drains of M29 and M30, almost no oscillation occurs. IOUT is in an open state close to 0V at the start of the switch operation, but the voltage of N201 becomes negative, M30 is turned on, and the voltage of IOUT also becomes negative. Therefore, M2
9 is also turned on, the positive charge of N201 flows to VPN according to the cycle of CLK, and the voltage of N201 becomes lower and lower. When the voltage of IOUT becomes equal to VPN, M29 does not turn on and IOUT becomes, for example, -8V.

HVSW-1 of FIG. 6 is the HVSW of FIGS.
1, HVSW2 and HVSW3 can be used.
SW-2 can be used for HVSW4 in FIGS.
VSW is NVSW1, NVSW2, NVSW of FIGS.
Can be used for 3.

Next, the disturb verify circuit and means in this embodiment will be described.

FIG. 9 shows an operation flowchart at the time of writing in this embodiment. In the write flow in FIG. 9, first, the control terminal is externally set to the write mode, and the write command is input to the data input (S1). Next, when a write address and data are input (S2), actual writing is started inside the storage device (S3). After a lapse of a predetermined time by a timer inside the storage device, writing is completed and write verification is performed (S4). When the write verify result is bad (that is, when the write data does not match the verify data)
(S5) Writing is performed again. If the result of the write verify is good (that is, if the write data and the verify data match) (S5), then the memory cell that is disturbed by the write is verified (S6). This is the disturb address verify. If the verification results of all the addresses that are disturbed are good (S8, S9), the writing is finished (S13). When the result of the disturb verify at a certain address is bad, the erase mode is switched to and the bad memory cell is erased (S10) (in this case,
Considering the case where the threshold value of a memory cell that was in a sufficiently erased state drops due to disturb). afterwards,
If the erase address is verified (S11), the verify result is bad (S12), the address is erased again (S10), and if the erase verify result is good (S11), the disturb address verify is continued. (S6). When the verification of all disturb addresses is successful (S8, S9), the writing is finally ended (S13).

FIG. 10 shows a timing chart when the write operation flow shown in FIG. 9 is embodied in the embodiment of FIG. Signal names in FIG. 10 have the same meaning as in FIG.

First, CEB = "H", OEB = "L",
When WEB = “H”, the FROM in FIG. 1 is in the power-down (or standby) mode, and does not accept address or data input. The data outputs D0 to D15 are in a high impedance state. CEB = "L", OE
The write mode is entered by changing B = “H” and WEB = “L”, and a write command (that is, a write command and an erase command) from the data input / output terminals D0 to D15.
Accept. A write command (for example, 000000000010 in binary) to the data input / output terminals D0 to D15.
000) is input, data is taken in when WEB changes from “L” to “H”, and data (for example, 0000000000100000) is output to the internal data signal DATIN via the data input / output buffer DIB. This data is decoded by the device control command identification circuit DVCNT when the control signal is in the above state,
A corresponding one of the plurality of control signals CNT2 changes from "L" to "H", for example. In response to this signal, the write state control circuit WCNT prepares to latch the write address and data, and when the WEB changes from "H" to "L" again, the address latch signal LTA is set to "L", for example.
From "L" to "H" latches the address, and when the WEB changes from "L" to "H", the data latch signal LTD changes from "L" to "H" to latch the data. At this time, the data of the internal data signal DATIN is sent to the data program circuit DPRG and the write / erase verify data coincidence detection circuit VEOR. Further, when the WEB changes from "L" to "H", the write state control circuit WCNT
Changes the write signal PRG from, for example, "L" to "H" to start the actual write operation. Details of the write operation are described in the embodiments of FIGS. The write state control circuit WCNT activates the timer TIM by changing the timer start signal S1 from, for example, “L” to “H” at the same time when the write operation is started. The timer TIM changes the timer end signal S2 from, for example, “L” to “H” after a predetermined time (eg, 1 millisecond) elapses, and thereby changes the write signal PRG from, for example, “H” to “L”. The actual write operation is finished.

The write state control circuit WCNT next changes the write verify signal PVF from, for example, "L" to "H" in response to the change of the write signal PRG from "H" to "L", thereby performing the write verify. Let it start. Further, the timer start signal S1 is set to "L", for example.
To "H". Write verify signal PV
When F becomes “H”, the voltage value for write verify, for example, 2V is output to the output VVF of the write / erase verify voltage generation circuit VFGEN. This voltage value is applied to the control gate of the written memory cell via the column decoder RDEC. When the threshold voltage of the memory cell becomes 2 V or less by the writing, the multiplexer MPX detects the sense amplifier circuit SA.
The same data as the write data is input to the write / erase verify match detection circuit VEOR via MP.
When the threshold voltage of the memory cell is equal to or higher than 2 V due to the writing, data different from the writing data is output to the output SOUT of the sense amplifier circuit SAMP. Program / erase verify match detection circuit VEOR
Is a write / erase verify data output signal PEN when the data of SOUT does not match the write data.
G is changed from "L" to "H", whereby the write state control circuit WCNT causes the write operation to be executed again. When the data of SOUT matches the write data, the write / erase verify data output signal PENG
Remains at "L", and at this time, the write verify signal PVF changes from "H" to "L" after a lapse of a predetermined time (for example, 1 microsecond) by the timer TIM, so that the write verify is completed. To do.

Immediately after the completion of the write verify, the write state control circuit WCNT changes the disturb verify signal DVF from "L" to "H".
The disturb verify mode, which is the gist of the present invention, is started. At this time, the address up counter AUP
At the same time as the write address is latched in CT, the head address of all the memory cells that are disturbed is latched. For example, the word line is 4096
Memory cell to be written in the memory cell array having 4096 bit lines, the third in the column direction (03h in hexadecimal).
), When it is at the 8th position in the row direction (008h in hexadecimal), the address up counter displays 030 in hexadecimal.
00h is set. When the disturb verify mode starts, the address up counter AUPC
The contents of T are loaded into the address buffer ADB, and the disturb address is verified. FIG. 11 shows an embodiment of the sense amplifier circuit including the write / erase disturb detecting means.

In FIGS. 1, 10 and 11, first, D
When VF becomes “H”, the disturb detection voltage value (for example, the same value as the applied voltage in the read mode) is applied to the control gate of the memory cell of the disturb address at the first address. At this time, a state in which the data of the address before the disturbance is erased, for example, D0 to D in binary
15 = (0000000000000000), and the threshold voltage of the memory cell at that time is, for example, 7.5.
In the case of V, the sense amplifier output data SOUT0 when the disturb detection voltage is applied and the DVF = “H” and DVF2 = “L” voltages in FIG. ~ 15 is (0
000000000000) and DVF = D
Sense amplifier output data S when VF2 = “H” voltage
The data for OUT0 to OUT15, that is, the disturb detection data is (0000000000000000). However, if there is a decrease in the threshold voltage due to disturb (for example, the threshold value of a 1-bit memory cell is 7.5 V).
To 6.5V), DVF =
The sense amplifier output data SOUT0 to SOUT0 to SOUT0 to SOUT15 at the time of “H” and DVF2 = “L” voltage are (0000000000)
However, the sense amplifier output data SOUT0 to SOUT0 when DVF = DVF2 = “H” voltage, that is, the disturb detection data is (0000000000).
0000010). Therefore, DVF = “H”, D
When VF2 = “L” voltage and DVF = DVF2 = “H”
Sense amplifier output data SOUT0 at voltage
By looking at 15, it is possible to know the detection and the original value when the decrease of the threshold value due to the disturbance is a certain value or more.

In FIG. 1, FIG. 10 and FIG. 11, when all the disturb detection data are 0, that is, when the change in the memory cell threshold voltage due to the disturb is less than a certain value, the disturb verify data output signal DTC is For example, it remains “L”, but for example DVF =
When the sense amplifier output data when the voltage is "H" and DVF2 = "L" is 0, and the sense amplifier output data when the voltage DVF = DVF2 = "H" is 1, the disturb verify data output signal DTC is For example, it changes from "L" to "H". If DTC is "L", the address S3 of the timer TIM causes the address up counter AUP to increase by one address. Timer TI
M, when the disturb verify mode was started,
Timer start signal S from write state control circuit WCNT
The operation is started by 1. When DTC is "H", the write state control circuit WCNT enters the mode of re-erasing the address deteriorated by disturb. That is,
The erase signal ERS changes from "L" to "H", for example.
In the embodiment of FIGS. 1 and 10, the erasing uses the erasing operation on a bit-by-bit basis in FIGS. By this erase operation, the threshold voltage of the disturbed memory cell is restored from 6.5V to 7.5V, for example. After the erase operation is completed, the write state control circuit WCNT executes the erase verify, and if the verify result is good, the disturb verify mode is executed again. The above operation is performed by the final address of the address up counter, for example, 16
The disturb verify mode ends by performing up to (03FFFh) in decimal. When the disturb verify mode ends, the writing finally ends.

FIG. 11 shows the sense amplifier circuit of FIG. 1 in more detail. PDQ or DVF is a signal that activates the sense amplifier circuit, DVF2 is a read signal of information for detecting a change in the threshold voltage value of the memory cell, SOUT0 to 15 are data outputs, and IO to
Reference numeral 15 is a memory read / write input. IV01, IV
02, ..., IV05 are inverter circuits composed of MOS transistors, AND01, AND02, AND03
Is a two-input logical product circuit (AND circuit) composed of MOS transistors, and OR1 is a two-input logical sum circuit (OR circuit) composed of MOS transistors. MP0
1, MP02, ..., MP08 are P-channel enhancement type MOS transistors, and are MN01, MN0.
2, ..., MN08 is an N-channel enhancement type MO
S-transistors, RCEL1, RCEL2, RC
EL3 is a reference memory cell.

In FIG. 11, N20 is the drain of MP01 and M
It is connected to the drain of N01, the drain of MN02, and the gate of MN03, and N21 is the drain of MP02, the gate of MP02, the drain of MN03, and MN05.
Is connected to a portion corresponding to the gate of MN05 and the gate of DAMP2 and DAMP3, and N22 is a drain of MP05, a gate of MP05, a drain of MN07 and MN.
N23 is connected to the drain of MP03, the drain of MN05 and the input of IV05, N24 is connected to the drain of MP04, the drain of MN06, the gate of MP03 and the gate of MP04, and the source of N25 is the source of MN05. , MN06 source and MN04 drain, N26 connected to MP06 drain, MN09 drain, MN10 drain and MN07 gate, N27 connected to MN07 source, MN08 drain and MN09 gate. There is.

DAMP1 is MP03, MP04, MP
05, MP06, MN04, MN05, MN06, MN
07, MN08, MN09, MN10, IV02 and R
This is a circuit that includes the CEL1 part, DAMP2, DAM
P3 is a circuit having the same transistors and connections as DAMP1.

In FIG. 11, PDQ and DVF are inputs of OR1. RD is the output of OR1, the input of IV01, A
Input of ND01, gate of MN04 and DAMP2 and D
It is connected to a location corresponding to the gate of MN04 in AMP3, and the output PDQB of IV01 is the gate of MP01,
It is connected to the gate of MN01, the gate of MP06, the gate of MN10, and the points corresponding to the gate of MP06 and the gate of MN10 in DAMP2 and DAMP3. IO0 is connected to the gate of MN02 and the source of MN03, and DVF2 is the input of AND01.
DV1 is the output of AND01, the input of IV03, M
It is connected to the gate of P08 and the gate of MN11. DV2 is an output of IV03, and is connected to the gate of MP07 and the gate of MN12. SOUT0 is connected to the drains of MP08, MP08, MN11, and MN12. SO1 is the output of IV02 of DAMP1, is the input of IV04, and SO2 is D
Corresponding to the part corresponding to the output of IV02 in AMP2, I
V05 input, SO3 is DAMP3 IV
It corresponds to the part corresponding to the output of 02, is the input of AND02, SO1B is the output of IV04, AN
It is an input of D02 and AND03. SO2B is IV05
Is the output of AND3 and is the input of AND03. D1 is AND
03 output, and is connected to each source of MN12 and MP08. P1 is the output of AND02, and MN
11 and MP07 sources. REF
1 is connected to the source of MN08 of DAMP1 and the drain of RCEL1. REF2 and REF3 are connected to a portion of DAMP2 and DAMP3 corresponding to the source of MN08 and a drain portion of RCEL2 and RCEL3, respectively. N30 is a ground node, each ground node of the inverter circuit and the AND circuit, MN01 and MN02.
, MN04, MN09, and MN10, and source portions of RCEL1, RCEL2, and RCEL3. N31 is a power supply node, each power supply node of the inverter circuit and the AND circuit, MP01 and MP0
2, MP03, MP04, MP05, and MP06 are connected to the respective source terminals and the gate of MN08.

SAMP1 is MP01, MP02, MP0
7, MP08, MN01, MN02, MN03, MN1
1, MN12, DAMP1, DAMP2, DAMP3,
IV01, IV03, IV04, IV05, AND0
1 and AND02 and AND03, SAMP2 to 16 are circuits having the same configuration as SAMP1, and outputs are SOUT1 to 15, respectively.

In FIG. 8, RD becomes "H" voltage when PDQ or DVF becomes "H" voltage, and IO0 becomes the same potential as the row line of the selected memory cell. PDQB
Becomes "L" voltage, MP01 is turned on,
MN01 is turned off, and the voltage of N20 rises from 0V. When the voltage of N20 rises, MN03 is turned on and IO0 becomes a voltage obtained by subtracting the threshold of MN03 from N20. However, when the voltage of IO0 becomes higher than the threshold value of MN02, MN02 is turned on and I
It suppresses the rise in the potential of O0. Therefore, when PDQ becomes "H", IO0 becomes, for example, 2V, which is near the intermediate value between 0V and the power supply voltage. At this time, if the memory cell to be read is in the ON state, a current flows from IO0 to the source of the memory cell, and the potential of IO0 drops slightly,
For example, it becomes 1.8V. The current supply for this is MP02
Therefore, by appropriately selecting the transistor size of MP02, the voltage of N21 is greatly reduced as compared with IO0, for example, from 4.2V to 3.5.
Since the voltage of N21 is also proportional to the amount of current flowing through the memory cell, MP01, MP02, MN02 and MN03 are amplifying the potential fluctuation of IO0. MP03, MP04, MN04, MN05 and MN
Reference numeral 06 is a differential amplifier, and N21 and N22 are differential inputs. MP05, MP06, MN07, MN09, and MN10 are circuits similar to MP01, MP02, MN01, MN02, and MN03, and IO0 for REF1.
Works the same as. MN08 changes the potential of REF1 to N2
It works to tell 7. IO1 to 15 are SAM
It is a node corresponding to IO0 in P2 to 16.

The threshold value of the memory cell to be read is, for example, 3 V, and the reference cells RCEL1 to RCE
When the threshold value of L3 is, for example, 7V, 4.5V, and 2V, the voltage of REF3 <the voltage of IO0 <the voltage of REF2 <RE
It becomes the voltage of F1, SO1 and SO2 become "L" voltage, and SO3 becomes "H" voltage. The threshold value of the reference memory cell is set in advance in the test mode or the like and will not be described in detail in this embodiment. D1 is "H" voltage, P1
Becomes an "H" voltage. DVF is "H" voltage and DVF2
Is at the "L" voltage, the sense amplifier circuit is in the read mode of the data written in the memory cell, and SOUT
The data of D1 is output to 0, and SOUT0 becomes the “H” voltage. When the DVF is the “H” voltage and the DVF2 is the “H” voltage, the sense amplifier circuit is in the mode for reading the information for detecting the change in the threshold value of the memory cell due to the disturb, and the data of P1 is output to SOUT0. SOUT0 becomes "H" voltage. The SAMPs 2 to 16 also operate in the same manner.

FIG. 13 shows the threshold voltage of the memory cell and FIG.
It is a figure which shows the correspondence with 2-bit data read from the nodes P1 and D1 of 1. The upper one corresponds to a higher threshold, and the lower one corresponds to a lower threshold. The threshold voltage value written in the memory cell at the time of programming and erasing is a value indicated by a circle. The reason why three detection levels of the threshold voltage by the reference cell are included between the threshold voltage values indicated by the circles is that the threshold voltage values stored in the memory cells are adjacent to each other. This is because the original threshold voltage can be restored when the threshold voltage level is changed. However, when the threshold voltage value stored in the memory cell rises above RCEL1 or falls below RCEL3, even if the threshold voltage value changes, the data written in the memory cell changes during reading. There is nothing to do, so R
It is not necessary to provide the threshold voltage detection level by the reference cell above CEL1 or below RCEL3.

The method of detecting the disturbance of the memory cell will be described below with reference to FIG.

For example, assume that the threshold voltage value of a certain memory cell immediately after erasing is higher than the threshold voltage value of the reference cell RCEL1. When the threshold voltage value of the memory cell remains higher than the threshold voltage value of RCEL1 during the disturb verify, the data D1 read at the time of reading the data written in the memory cell is the “L” voltage. The data P1 read as the information for detecting the disturbance of the memory cell is the "L" voltage. The threshold voltage value of the memory cell is lower than that at the time of erasing due to the loss of charges, and
As shown in, when the threshold voltage value of the reference cell RCEL1 and the threshold voltage value of the reference cell RCEL2 are reached, D1 is the “L” voltage and P1 is the “H” voltage. Although the threshold voltage value of the memory cell was initially lower than that of RCEL3, the threshold voltage value of the reference cell RCEL2 becomes higher than that at the time of programming due to charge injection, for example, as shown in FIG. When it is between the threshold voltage value of the reference cell RCEL3, D1 is the "H" voltage and P1 is the "H" voltage.

As described above, when 1-bit write data is read, the threshold voltage value of the memory cell is set to three adjacent threshold voltage values by providing three levels of the threshold voltage value of the reference cell. Even if the level changes, the data that is read when reading the data written to the memory cell does not change.By reading the information for disturb detection of the memory cell, the threshold due to the disturb before the value of the write data changes. It is possible to detect a change in value. In the present embodiment, there is no disturb when P1 is "L" voltage, and there is disturb when P1 is "H" voltage.

The operation of the device of this embodiment when a write command is input has been described above, but the same applies to an erase command.

FIG. 12 shows an operation flowchart of the apparatus of this embodiment at the time of erasing. In the erasing flow in FIG. 12, first, the control terminal is externally set to the erasing mode, and the erasing command is input to the data input (S20). Next, when an erase address is input (S21), actual erase is started inside the storage device (S22). After a lapse of a predetermined time by a timer inside the storage device, erasing is completed and erase verify is performed (S23). When the erase verify result is bad (that is, when the erase data and the verify data do not match) (S24), the erase is performed again (S2).
2). When the erase verify result is good (that is, when the erase data and the verify data match) (S2
4) Next, the memory cells that are disturbed by erasing are verified (S25). This is the disturb address verify. If the result of verifying all addresses that are disturbed is good (S27, S
28) and the erasing ends (S29). When the result of the disturb verify at a certain address is bad (S2
7) Then, the mode is switched to the erase mode again, and the bad memory cell is erased (S29) (in this case, the case where the threshold value of the memory cell in the sufficiently erased state is lowered due to the disturb) is considered. After that, the erase address is verified (S30), and if the verification result is bad (S31), the address is erased again (S30).
29), if the erase verify result is good (S3
1) Continue disturb address verification (S
25). When verification of all disturb addresses is successful (S27, S28), the erasing is finally ended (S29). Although a timing diagram for erasing is not described in detail, it can be easily realized by the above embodiment.

In the disturb detecting circuit and means of the present embodiment, the case where the lowering of the threshold value of the memory cell is corrected by the disturb is described, but even when the rising of the threshold value of the memory cell is corrected by the disturb. It will be easily understood that a similar circuit can be realized within the scope of the present invention.

Further, in the sense amplifier circuit of the present embodiment, only one of the stored information of the memory cell (D1 in FIG. 11) or the disturb detection data (P1 in FIG. 11) can be output, but in D1 in FIG. , P1 are both output from the sense amplifier circuit, so that the storage information of the memory cell and the disturb detection data are simultaneously output.
The disturb verify data detection circuit DVFC may be configured to be input.

FIG. 14 shows a circuit block diagram of the second embodiment of the present invention. The second embodiment differs from the first embodiment shown in FIG. 1 in that a write / erase disturb detection voltage generation circuit DSVF is provided. The write / erase disturb detection voltage generation circuit DSVF receives the disturb verify signal DVF from the write state control circuit WCNT, and outputs the disturb verify voltage signal VDVF to the column decoder RDEC. With the change in this configuration, the configuration of the sense amplifier circuit SAMP is changed as in the conventional one, and the disturb verify operation is changed as follows. The other points are the same as those of the first embodiment described above.

FIG. 15 shows a configuration example of the write / erase disturb detection voltage generation circuit DSVF. 16 shows a timing chart in this embodiment. As shown in FIG. 16, in this embodiment, the disturb verify signal DVF is divided into two signals DVF1 and DVF2 and output. This is because, in the write / erase disturb detection voltage generation circuit DSVF, when DVF1 is input, the first disturb verify voltage value (for example, 6V) is output to the disturb verify voltage signal VDVF, and D
This is because when VF2 is input, the second disturb verify voltage value (for example, 7V) is output to the disturb verify voltage signal VDVF.

In FIG. 15, DSDT is a disturb data detection circuit, which includes D-F / F0, D-F / F1,
.., D-F / F31 are data input flip-flops with a reset input in the synchronous system. The data input to the D terminal is output to Q at the transition edge of the clock CK from "H" to "L". ENOR1, ENOR2,
.., ENOR 15 is a 2-input exclusive OR inverting gate, and the output is "L" when the data of the two inputs match, and the output is "H" when the data of the two inputs do not match. OR1
Is a 16-input OR gate. In FIG. 11, the disturb verify signal DVF1 is DF / F0,
, D-F / F15 are connected to the CK terminals of D-F / F1, ..., D-F / F15, and DVF2 is D-F / F16, D-F / F17,
..., the sense amplifier output signal SOUT0 is connected to the CK terminal of the D-F / F31 and the D-F / F0 and D-F / F1
6 to the D terminal, SOUT1 is DF / F1 and DF / F
, SOUT15 are connected to the D terminals of D-F / F15 and D-F / F31, respectively. The reset signal CNTB2 is DF / F0, DF / F1, ...
It is connected to the reset terminal R of the D-F / F 31. C
NTB2 is a signal that becomes "L" when a write command is input and becomes "H" when the disturb verify is completed.

The operation flow of the disturb verify in the present embodiment is the same as that shown in FIG. 9, and in FIGS. 15 and 16, first, the DVF1 is set to "H" so that the first disturb detection voltage value (for example, 6V) is applied to the control gate of the memory cell of the disturb address of the first address, and DVF2 becomes "H", so that the second disturb detection voltage value (for example, 7V) causes the memory cell of the disturb address of the first address. Applied to the control gate of. At this time, a state in which the data of the address before the disturbance is erased, for example, D0 in binary
.About.D15 = (1111111111111111), and the threshold voltage of the memory cell at that time is, for example, 7.
In the case of 5 V, the sense amplifier output data SO when the first and second disturb detection voltages are applied when the threshold voltage does not drop due to disturb
The UT is (1111111111111111).
However, when there is a decrease in the threshold voltage due to the disturb (for example, when the threshold value of the 1-bit memory cell drops from 7.5V to 6.5V), the sense at the first disturb detection voltage is detected. Although the amplifier output data SOUT is (1111111111111111), it is, for example, (11111111111111101) at the second disturb detection voltage value. Therefore, when the sense amplifier output data at the first disturb detection voltage and the sense amplifier output data at the second disturb detection voltage value are coincident with each other, the threshold value drop due to the disturb is equal to or more than a certain value. It can be seen that can be detected.

In FIG. 14, FIG. 15 and FIG. 16, if there is a match between the sense amplifier output data at the first disturb detection voltage and the sense amplifier output data at the second disturb detection voltage value, the disturb The verify data output signal DTC remains "L", for example, but if they do not match, the disturb verify data output signal DTC changes from "L" to "H". When DTC is "L", output S of timer TIM
By 3, the address up counter AUP is incremented by one address. The timer TIM is a write state control circuit WCNT when the disturb verify mode is started.
The operation is started by the timer start signal S1 from When DTC is "H", the write state control circuit WC
The NT enters a mode of re-erasing an address deteriorated by disturb. That is, the erase signal ERS changes from "L" to "H", for example. In the case of the present embodiment, erasing is performed by referring to FIGS.
Use the bitwise erase operation in. By this erase operation, the threshold voltage of the disturbed memory cell is restored from 6.5V to 7.5V, for example. After the erase operation is completed, the write state control circuit WCNT executes the erase verify, and if the verify result is good, the disturb verify mode is executed again. The above operation is performed by the final address of the address up counter, for example, 1
The disturb verify mode ends by performing hexadecimal up to (03FFFh). When the disturb verify mode ends, the writing finally ends. The same applies to the erase command.

The present invention has been described above with reference to the embodiments.
According to the gist of the present invention, the arrangement and configuration of the memory cells do not necessarily have to be the same as those in the above-described embodiments. It may be arranged as shown.

Further, although one type of writing method and two types of erasing methods are presented in the above-mentioned embodiment, it is not necessary to specify the writing and erasing methods in the spirit of the present invention.

In this embodiment, the erasing means is used as a means for restoring the memory cell whose threshold voltage has changed due to the disturbance. It does not have to be the same as the time. In actual erasing, the threshold value of the memory cell is changed from 2V to 7.5V, for example, but to restore the threshold value of the disturbed memory cell from 6.5V to 7.5V, for example. The voltage may be changed, and the voltage may be lower than that in the actual erase. The shape of the memory cell is not specified.

Further, another function may be added to the embodiment of the present invention to add the function to the writing or erasing flow. Further, the voltage value used in the embodiments of the present invention is not particularly limited to that value, and any value may be selected within a range that does not impair the operation of the present invention.

[0126]

As described above, according to the present invention,
In an electrically writable or rewritable non-volatile semiconductor device, detection and restoration of a memory cell that has been disturbed before the data destruction due to disturb is realized by an electric means, so that the disturbance tolerance can be significantly improved. is there. That is, at least twice or three times the minimum number required to read the stored information in the memory cell.
By providing a double threshold voltage detection level and comparing and collating the detection level with the threshold voltage of the memory cell, it is possible to know the storage information of the memory cell and the disturb detection data at the same time. Disturb can be detected at the same time as the reading of the nonvolatile semiconductor device.

The final anti-disturbance time is (disturbance-proof time in the conventional circuit × recoverable number of times). Since the number of recoverable times is equal to or more than the number of rewritable times of the memory cell, for example, the disturbance resistance time in the conventional circuit is 1 second, and if the number of rewritable times of the memory cell is 100,000 times, the disturb resistance time is Is 100,000 seconds, and it can be seen that there is a sufficient margin even when sector erase is performed.

Further, it is possible to realize a great improvement in the disturbance resistance without the need for the optimization of the structure of the memory cell and the devising of the manufacturing method as in the prior art, and the data retention of the nonvolatile semiconductor memory device using the present invention can be realized. The reliability of can be greatly improved. Further, when the power supply voltage for writing or erasing the memory cell is reduced in the manufacturing process, the normal disturbance withstand time becomes short as shown in Document 3. However, if the present invention is used, the disturb resistance time can be lengthened,
Operation can be guaranteed at low power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an upper left portion of the circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a lower left portion of the circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing an upper right portion of the circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a lower right portion of the circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a positive high voltage switch according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing another positive high voltage switch according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a negative voltage switch according to the first embodiment of the present invention.

FIG. 9 is a flowchart at the time of writing in the first embodiment of the present invention.

FIG. 10 is a timing diagram at the time of writing in the first embodiment of the present invention.

FIG. 11 is a circuit diagram of a sense amplifier circuit according to the first embodiment of the present invention.

FIG. 12 is a flow chart at the time of erasing according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between read data and a memory cell threshold value in the sense amplifier circuit according to the first embodiment of the present invention.

FIG. 14 is a circuit block diagram showing a second embodiment of the present invention.

FIG. 15 is a circuit diagram of a disturb detection circuit according to a second embodiment of the present invention.

FIG. 16 is a timing diagram at the time of writing in the second embodiment of the present invention.

[Explanation of symbols]

FROM Non-volatile semiconductor memory device DVCNT device control command identification circuit WCNT write state control circuit RCNT chip / output selection state control circuit TIM timer VFGEN write / erase verify voltage generation circuit ADB1 address buffer RDEC column decoder CDEC row decoder MBLK memory block MPX multiplexer PCP Positive high voltage charge pump NCP Negative voltage charge pump HVCNT Positive high voltage control circuit NVCNT Negative high voltage control circuit DIB Data input / output buffer BLLD Bit line load circuit BLCNT Bit line voltage control circuit ASCNT Memory cell source line voltage control circuit SAMP Sense amplifier circuit DVFC disturb Verify data detection circuit VEROR Program / erase verification data match detection circuit PRG data program circuit DSVF write / erase disturb detection voltage generation circuit

Claims (7)

[Claims] 1. In an electrically writable nonvolatile semiconductor memory device, a plurality of electrically writable nonvolatile semiconductor memory cells arranged in a matrix and at least one of the memory cells are selected. Circuit for bringing the other memory cells into a non-selected state and writing means for writing to the memory cell in the selected state via the decoder circuit; and reading from the memory cell in the selected state via the decoder circuit. Read-out means for performing; and detecting means for detecting a change in threshold voltage of the memory cell in the non-selected state caused by a voltage applied to the memory cell in the non-selected state when writing to the memory cell in the selected state. And a threshold of the memory cell in the non-selected state according to a result of detecting a change in the threshold voltage of the memory cell in the non-selected state. A non-volatile semiconductor memory device, comprising: a restoring unit that restores a high-value voltage to a value before change or a value in the vicinity thereof. 2. The detection means provides the detection level of the threshold voltage of the memory cell in the selected state more than the minimum number required for reading the stored information of the memory cell, and the detection level and the memory cell 2. The non-volatile semiconductor memory device according to claim 1, wherein information for detecting a change in threshold voltage is taken out in addition to information stored in the memory cell by comparing with the threshold voltage. 3. When the writing mode is designated by an external signal or an external command of the nonvolatile semiconductor memory device, the detection means is operated after writing to the memory cell in the selected state, and the non-selected state 2. A control circuit for operating the restoring means according to a result of detecting a change in threshold voltage of a memory cell.
Alternatively, the nonvolatile semiconductor memory device described in 2. 4. An electrically writable and erasable non-volatile semiconductor memory device comprising: a plurality of electrically writable and erasable non-volatile semiconductor memory cells arranged in a matrix; and at least one of the memory cells. A decoder circuit that puts one in a selected state and other memory cells in a non-selected state, a writing unit that writes to the selected memory cell through the decoder circuit, and a memory in the selected state through the decoder circuit Erasing means for erasing cells, reading means for reading from the memory cells in the selected state via the decoder circuit, and voltage applied to the memory cells in the non-selected state when erasing the memory cells in the selected state Detecting means for detecting a change in the threshold voltage of the memory cell in the non-selected state, which is caused by And a restoring means for restoring the threshold voltage of the memory cell in the non-selected state to a value before the change or a value in the vicinity thereof according to the result of detecting the change in the threshold voltage of the recell. The means provides a threshold voltage detection level of the memory cell in the selected state more than the minimum number required for reading the stored information of the memory cell, and compares the detection level with the threshold voltage of the memory cell. A non-volatile semiconductor memory device is characterized in that, by performing the above step, information for detecting a change in threshold voltage is extracted in addition to the information stored in the memory cell. 5. When an erase mode is designated by an external signal or an external command of the nonvolatile semiconductor memory device,
After erasing the memory cell in the selected state, the control circuit operates the detection means, and operates the restoration means according to a result of detecting a change in the threshold voltage of the memory cell in the non-selected state. The nonvolatile semiconductor memory device according to claim 4. 6. An electrically writable and erasable non-volatile semiconductor memory device comprising: a plurality of electrically writable non-volatile semiconductor memory cells arranged in a matrix; and at least one of the memory cells. To a selected state and other memory cells to a non-selected state, a writing means for writing to the selected memory cell through the decoder circuit, and a write circuit for writing the selected memory cell through the decoder circuit. Erasing means for erasing, reading means for reading from the memory cell in the selected state via the decoder circuit, and generation by a voltage applied to the memory cell in the non-selected state when writing to the memory cell in the selected state First detecting means for detecting a change in threshold voltage of the memory cell in the non-selected state, and the memory in the selected state. Second detecting means for detecting a change in threshold voltage of the memory cell in the non-selected state by a voltage applied to the memory cell in the non-selected state during cell erasing; and the memory cell in the non-selected state In accordance with the result of detecting the change in the threshold voltage of, by the first or second detecting means,
And a restoring unit that restores the threshold voltage of the non-selected memory cell to a value before the change or a value close to the value before the change, wherein the detecting unit has a threshold voltage of the memory cell in the selected state. Detection levels of more than the minimum number required to read the stored information of the memory cell, and by comparing the detection level with the threshold voltage of the memory cell, the threshold value other than the stored information of the memory cell is determined. A non-volatile semiconductor memory device characterized by extracting information for detecting a change in value voltage. 7. The storage means stores the stored information of the memory cell when the threshold voltage value of the memory cell in the non-selected state obtains information as to whether or not the threshold voltage value has changed as compared with that at the time of writing or erasing. At least twice as many threshold voltage detection levels as necessary for reading are provided to determine whether the threshold voltage value of the non-selected memory cell is higher or lower than that at the time of writing or erasing. When obtaining information, a threshold voltage detection level that is at least three times the minimum number required to read the stored information of the memory cell is provided, and the detection level and the threshold voltage of the memory cell are compared. , Information regarding the presence or absence of a change in the threshold voltage of the memory cell and the value before the change of the threshold voltage by extracting the information for detecting the change in the threshold voltage in addition to the stored information of the memory cell. 3. The method according to claim 2, wherein
7. The nonvolatile semiconductor memory device according to any one of 4 and 6.