JPH07141300A - Period processing method using plural processors - Google Patents

Abstract

PURPOSE:To provide a decentralized period processing method using plural processors. CONSTITUTION:When an in-period-process flag IMF in a period process support circuit 2 is OFF and a flag for interruption generation is ON, processors P1 to Pn are interrupted and a period control program is started at the same time. A period control program places the processors in decentralized execution of the period process program by using a time-out signal holding flag 22 which holds the time-out signal of a timer 21, a period process execution inhibition display flag 27 which is fired by software at the end of the dispatching (actuation end) of all period process object programs to be processed in respective period and reset when a next period comes and the period processes in the last period are all completed, a period process end display flag 28 which indicates that the execution of all the period process object programs to be processed in the respective periods ends, and the period process program and a correspondence table 35 of its execution time in a main storage device 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cyclic processing method for distributing a plurality of cyclic processing programs having a predetermined start cycle by a plurality of processors, and more particularly, to the cyclic processing program evenly by a plurality of processors. The present invention relates to a periodic processing method using a multiprocessor which is distributed and executed.

[0002]

2. Description of the Related Art Generally, periodic processing guarantees real-time processing by executing a processing program determined for each predetermined cycle, and is particularly useful in exchange processing. Is the way. The conventional cyclic processing will be described below by taking a cyclic processing method using a cyclic processing table that defines the start timing of the cyclic processing program to be executed as an example. In the following description, what is activated by the periodic process schedule will be referred to as “periodic process”, and other processes will be referred to as “normal process”. FIG. 6 shows a conventional example in which a single processor is used to perform cyclic processing at a predetermined cycle. In FIG. 6, reference numeral 71 is a basic period signal generator TSG, and 72 is an interrupt controller IR.
C and 73 are register read / write units, 74 is an interrupt mask register, 75 is an interrupt factor register, 7
6 is an interrupt request determination unit, 77 is a processor, 78 is a processor bus, 79 is a main storage device (MM), and a main processing unit (MM) 79 has a periodic processing table (a periodic processing table that holds a processing program to be executed at each execution time). TBL) 80, time pointer 81, PROC pointer 82 for instructing a processing program
Is stored. In the periodic processing table (TBL: 80), as shown in the figure, processing program numbers are associated in the column direction and execution times are associated in the row direction. The processing program number is a column of PROC1 to PROCn (n: the maximum number of programs that can be registered), and the execution time is given from 0 to m rows of T / Ts (m: T / Ts, Ts is a basic cycle) (Ts : Basic period, T: maximum period).

Processing program currently being executed (PROC)
Is a time pointer TPTR (81) that specifies the execution time
And a processing program to be executed during the time (PRO
C) designated by the PROC pointer PPTR (82). Therefore, the designated TBL (8
When the content of 0) is "1", it means that the processing program (PROC) should be executed during the time. The above-mentioned time pointer TPTR (81) sequentially increments from 1 by 1 and has a value up to m, and after m, returns to 1 again. The PROC pointer PPTR (82) takes a value from 1 to n. The interrupt request of the processor is used to ensure the immediacy of the activation request notification to the processor of the periodic processing. The interrupt function of a general processor has an interrupt mask control for suppressing an interrupt. Since the periodic process is a process with a high degree of urgency, when executing the periodic process, interrupts from others are usually suppressed by using this interrupt mask. In the case of general interrupts, an interrupt priority order depending on the type of interrupt is also provided as needed.

The operation of FIG. 6 when the above-mentioned conventional single processor is used will be described in detail below with reference to the timing chart of FIG. 7 and the operation flowchart of the interrupt processing shown in FIG. (1) From the basic periodic signal generator TSG (71) to the above-mentioned T
The basic periodic signal S1 is generated at intervals of s (t1). (2) The interrupt control unit IRC (72) detects the active (high level) of the basic cycle signal S1 and sets the interrupt factor register IRR (75) to "1" (requested) (t2). . (3) The interrupt request determination unit IRJ (76) of the interrupt control unit IRC (72) uses the interrupt mask register IMR (7
Contents of 4) and the above-mentioned interrupt factor register IRR (75)
Content of IRR = "1" and IMR
If it is "0" (mask release), the interrupt request signal INT to the processor P is set to "1" (t3). (4) The processor P detects the active state (high level) of the above-mentioned interrupt request signal INT and shifts to interrupt processing.

(5) The interrupt processing in the processor P operates as follows. When the interrupt request signal INT is detected, the interrupt processing shown in FIG. 8 is performed. ． First, in step 91, the following processes a, b, and c are performed (t4). a. Processor P is a processor bus PBUS (78)
The register read / write unit RRW (73) in the interrupt control unit IRC (72) is activated via the, and "1" is set in the interrupt mask register IMR (74). b. Processor P is a processor bus PBUS (78)
The register read / write unit RRW (73) in the interrupt control unit IRC (72) is activated via the, and "0" is set in the interrupt factor register IRR (75). c. The processor P sets “0” in the PROC pointer PPTR (82) on the main memory MM. ． Next, in step 92, the processor P updates (+1) the time pointer TPTR (81) on the main memory MM (79) (t5). ． In the next step 93, the processor P searches the periodic processing table TBL (80) on the main memory MM (79) and updates the PPTR (82) (in the row indicated by TPTR, P
"1" is searched from the column of PTR + 1, and the contents of PPTR are updated to the column number of the search position). In step 94, the processor P executes the processing in step 95 and returns to step 93 if the corresponding PROC exists as a result of the search. While the corresponding processing PROC exists, the processing of step 93 to step 95 is repeated. ． In step 96, the processor P sends the interrupt control unit IRC via the processor bus PBUS (78).
Register read / write unit RRW (7 in (72)
3) is started, "0" is set in the interrupt mask register IMR (74) (t6), the interrupt process is terminated, and the normal process is resumed. By repeatedly executing the above processes (1) to (5), the periodic process is realized for each basic period. In the above (3), if IMR = "1" (t in FIG. 7).
7)), the subsequent process is extended until IMR = “0” (t8). When the cycle process cannot be completed within the cycle and enters the next cycle, the process of the next cycle is performed after the process of the previous cycle is completed.

[0006]

The above-mentioned prior art is premised on the processing by a single processor, and the periodic processing can be executed only by the single processor. Therefore,
Even when a multiprocessor is used, the conventional method cannot improve the performance because the periodic processing can be executed by only one dedicated processor. Therefore, load distribution cyclic processing in which cyclic processing is distributed and executed by a plurality of processors is conceivable, but in that case, there are the following problems (a) and (b). (A): When the time of the next cycle comes while a specific processor (for example, the processor 1) is executing the cyclic processing, the time until the execution of the cyclic processing (previous cycle) being executed by the processor 1 is completed Therefore, it is necessary to suppress the start of the periodic processing of another processor which has finished the periodic processing (of the previous cycle). (B): When a specific processor (for example, the processor 1) is executing a process different from the periodic process, when another processor completes the execution of the periodic process of the period, the processor 1 that has completed the different process It is necessary to suppress the periodic processing execution of. The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-described problems in the conventional technique, and even when a multiprocessor is used, a plurality of processors can perform the periodic processing equally. It is to provide a periodic processing method that can be executed in a distributed manner.

[0007]

In order to achieve the above-mentioned object, the above-mentioned object of the present invention uses a multiprocessor which disperses a plurality of periodic processing programs having a predetermined start-up period by a plurality of processors. In the cycle processing method, a cycle control program provided for each processor, a cycle processing display means provided for each processor to display that the cycle processing is being performed, and executed for each cycle From the time when the start of all the periodic processing programs to the start of the periodic processing of the next cycle, the periodic processing execution prohibition display means for displaying that the periodic processing execution is prohibited, and all the periodic processing execution prohibited Displays that all cyclic processing programs to be executed have been completed from the time when the cyclic processing program starts to the time when the next cycle starts. Cycle processing end display means, and when the cycle control program finishes starting all cycle processing programs to be processed in each cycle, the cycle processing end display means displays the start and end of all cycle processing programs. At the same time, the prohibition of the start of the periodic processing is displayed on the periodic processing execution prohibition display means, and the periodic processing execution prohibition display means is displayed at the start of the next cycle after the execution of all the periodic processing programs to be processed in each cycle is completed. I am trying to reset.

[0008]

In the periodic processing method according to the present invention, as described above, all the processors forming the multiprocessor system can realize the periodic processing by any processor on an equal basis. A periodic processing method in which the processing in the processor is the same can be realized, and the performance can be improved.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a system configuration to which an embodiment of the present invention is applied. In FIG. 1, 1
1 to 1n are processors (P1 to Pn), 2 is a periodic processing support circuit, and 3 is a main memory MM. In the cycle processing support circuit 2, 21 is a timer for counting cycle intervals (TICY: outputs a time-out signal for every fixed cycle), 2
Reference numeral 2 is a time-out signal holding flag (TIF) that holds a time-out signal of the timer 21, 231 to 23n are periodic processing in-progress flags (IMF) for each processor, and 241-
24n is a flag for generating an interrupt to the processor (IR
F), 251 to 25n are display flags 231 to 231 during periodic processing.
An interrupt suppression circuit for suppressing an interrupt to each processor while 23n is firing, and 26 is a display flag 231 for each periodic processing
A circuit that takes an OR of ~ 23n and displays whether or not the periodic processing has been completed in all the processors. 27 is fired by software when the dispatch of all the cyclically processed programs to be processed in each cycle is completed (startup is completed). Then, the next cycle arrives (timeout signal holding flag 22 ignition) and the cycle processing execution prohibition display flag (INCF), which is reset when the cycle processing of the previous cycle is completed, 28
Indicates that the periodic processing end display flag (EN
PF), 29 is a cycle for igniting the cycle processing end display flag when the cycle processing execution prohibition display flag is ignited, and for resetting the cycle processing end display flag upon arrival of the next cycle (timeout signal holding flag 22 ignition) It is a processing end display flag control circuit.

Further, 30 is a time counter (TCTR),
31 indicates that when the cycle processing of the previous cycle is completed within one cycle, the arrival of the next cycle (timeout signal holding flag ignition) triggers the cycle processing of the previous cycle to extend to the next cycle. When the cycle processing of the previous cycle is completed (circuit 2
When the output of 6 is "0"), the time counter increment control circuit that increments (+1) the time counter 30, 32 is the number of entries (TTE) registered in advance by software, 33 is the time counter 30 and 3 are the number of entries.
A comparator that resets the time counter when the contents of 2 match, 34 is a table reference flag (TAF) indicating whether or not the periodic processing table (TBL) on the main memory MM can be referred to,
Reference numeral 35 is a periodic processing table for managing the schedule of periodic processing,
Reference numeral 36 is a program pointer (PPTR) indicating the number of the program to be periodically processed which is currently being executed. In the periodic processing table 35, processing program numbers (1 to m) are associated in the column direction and execution times (t1 to tk) are associated in the row direction. In this embodiment, the counter for designating the time is also supported by hardware. As a result, it is not necessary to control the counter up of the time for each cycle by software.

Next, the operation of the system of FIG. 1 will be described with reference to the process flow chart of the cycle control program of FIG. 2 and FIGS.
It will be described in detail with reference to the time chart shown in FIG. In addition,
The activation pattern of the cycle control program can be broadly classified into those shown in FIGS. 3, 4, and 5. The pattern of FIG. 3 shows the case where the execution of all the cyclic processing target programs for each cycle ends within one cycle, and FIG. 4 shows the case where the execution of the cyclic processing target program spans two or more cycles. FIG. 5 shows a case where a processor that has been performing another process by masking an interrupt triggered by the periodic process ends the another process and starts the periodic process.

Below, the operation flow of the cycle control program activated upon the interruption of every fixed cycle will be described in detail with reference to FIG. First, when the cycle control program is started (step 50), the cycle control program firstly displays the cycle process execution prohibition display flag (INCF: 2).
7) is read (step 51). It is determined whether or not the read periodic process execution prohibition display flag (INCF: 27) is "0" (step 52). If it is "0" (ee1), it is not "0" (ee2). ).

(A-1): As a result of the judgment in step 52, when the periodic process execution prohibition display flag (INCF: 27) is in the periodic process execution permission state (that is, INCF = 0).
(For example, in the case of the processors P1, P2, ... Pn in FIG. 3). Periodic processing in progress display flag (IMF)
1 to IMFn: 231 to 23n), that is,
The cycle processing state ("1") is set, and the interrupt generation flags (IRF1 to IRFn: 241 to 24n) are reset (step 53). The reason for resetting the interrupt generation flag IRF is to newly store the interrupt when the interrupt occurs in the next cycle. ． Next, read the time counter (TCTR: 30),
It is confirmed what number cycle of the periodic processing target program should be executed (step 54).

.. Next, a test and set (T & S) is performed on the TAF flag 34 in order to acquire the periodic processing execution right. That is, the TAG flag 34 is read and "0" is read.
If it is "0" (accessible), it is set to "1" to prohibit access from others (step 5).
5: Acquisition of periodic processing execution right). The TAG flag 34 is "1"
If the acquisition of the periodic process execution right is not successful in (access prohibition), the process returns to step 55, and steps 55 and 56 are repeated until the acquisition of the periodic process execution right succeeds. If succeeded, the process proceeds to the next step 57. ． In step 57, the periodic process end display flag (ENPF: 28) is read in order to search whether or not the periodic process target program to be executed remains, and whether the periodic process end display flag (ENPF: 28) is 0 or not. (Step 58), if not 0, TAF flag 3
4. Display flag (IMF during processing) for own processor
1 to IMFn: 231 to 23n) are reset (step 62), and the periodic process is ended (step 63).

.. If the result of determination in step 58 is that the periodic processing end display flag (ENPF: 28) is 0, the periodic processing table (35) in the main memory (MM: 3) is searched and the program pointer (PPTR: 36) is set. Update (step 59). As a result of the search, if the cyclic processing target program to be executed is the last cyclic processing target program to be executed in the current cycle (step 60), the cyclic processing execution prohibition display flag (INCF: 27) is set and the program pointer (PPTR: 36) is reset (step 6)
1), release of the table reference flag (TAF: 34), display flag (IMF1 to IF1) corresponding to the own processor
MFn: 231 to 23n) is reset (step 62), and the cycle process is ended (step 63). ． As a result of searching the cyclic processing table, if the cyclic processing target program to be executed is not the last cyclic processing target program to be executed in the current cycle (step 60), after clearing the table reference flag (TAF: 34) (Step 64) and the procedure returns to (the processing of) step 55.

(A-2): As a result of the determination in step 52, when the periodic process execution prohibition display flag (INCF: 27) is in the periodic process execution prohibition state (that is, INCF = 1).
(For example, refer to the (m + 1) th cycle of the processors P1, P2, ... Pn in FIG. 4). The periodic processing end display flag (ENPF: 28) is read (step 65), and the periodic processing end display flag (E
It is determined whether NPF: 28) is 0 (step 66),
If it is not 0, the TAF flag 34 is released, the in-period processing display flags 231 to 23n corresponding to the self processor are reset (step 62), and the periodic processing is ended (step 63). ． If the result of determination in step 66 is that the cyclic process end display flag (ENPF: 28) is 0, the cyclic process execution prohibition display flag (INCF: 27) is read (step 67), and the cyclic process execution prohibition display flag (INCF). : 2
It is determined whether or not 7) is 0 (step 68). ． If the result of determination in step 68 is that the periodic process execution prohibition display flag (INCF: 27) is 0, the process returns to (a-1). If it is not 0, the process returns to step 67 again and repeats steps 67 and 68 until it becomes 0, and waits.

As described above, when the execution of all the cyclic processing target programs for each cycle is completed within one cycle, as shown in FIG. 3, the execution of the cyclic processing target program spans two or more cycles. When the processor that has been performing another process by masking the interruption caused by the periodic process as shown in FIG. 4 finishes the another process and starts the periodic process, it becomes as shown in FIG. 5 and constitutes a multiprocessor system. Since all the processors can equally implement the periodic processing by any processor, it is possible to realize the periodic processing method in which the processing by all the processors in the system is the same.

[0018]

As described above in detail, according to the present invention, even when a multiprocessor is used, a periodic processing method that allows any processor to execute the periodic processing, particularly all the processors in the system. It is possible to realize a periodic processing method in which the processing in step 1 is the same.

[Brief description of drawings]

FIG. 1 is a diagram showing a system configuration to which an embodiment of the present invention is applied.

FIG. 2 is a flowchart of a cycle control program of the present invention.

FIG. 3 is a time chart of each cyclic processing pattern.

FIG. 4 is a time chart of each cyclic processing pattern.

FIG. 5 is a time chart of each cyclic processing pattern.

FIG. 6 is a diagram showing a system configuration of periodic processing of a conventional example.

FIG. 7 is a diagram showing a time chart of a periodic processing pattern of a conventional example.

FIG. 8 is a flowchart of interrupt processing in a conventional example.

[Explanation of symbols]

11 to 1n Processor (P1 to Pn) 2 Cycle processing support circuit 3 Main memory (MM) 21 Timer (TICY) that outputs a timeout signal at regular intervals 22 Timeout signal holding flag 231 to 23n that holds the timeout signal of the timer 21 Display flag during I / O processing (IMF1-I
MFn) 241 to 24n Interrupt generation flag (IRF1 to IR
Fn) 251 to 25n Interrupt suppression circuit 26 Circuit for displaying whether or not the periodic processing is completed in all the processors 27 Cycle processing execution prohibition display flag (INCF) 28 Cycle processing end display flag (ENPF) 29 Cycle processing end display flag Control circuit 30 Time counter (TCTR) 31 Time counter increment control circuit 32 Number of entries (TTE) 33 Comparator 34 T indicating whether or not the periodic processing table on the main memory can be referred to
AF flag (TAF) 35 Periodic processing table for managing the periodic processing schedule 36 Pointer (PPTR) indicating the number of the periodic processing target program currently being executed

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Shuji Miki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Takanari Hoshiai 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo No. Japan Nippon Telegraph and Telephone Corp. (72) Inventor Nobuyuki Watanabe 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corp.

Claims (1)

[Claims] 1. A cycle processing method using a multi-processor for distributing a plurality of cycle processing programs of a predetermined start cycle by a plurality of processors, wherein a cycle control program provided for each processor, Cycle processing in-progress display means provided for each processor to indicate that the cycle processing is being performed for each processor, and the cycle processing for the next cycle from the time when all the cycle processing programs to be executed for each cycle are finished The periodic process execution prohibition display means for displaying that the periodic process execution is prohibited until the start time of, and the process should be executed from the time when the start of all the cyclic process programs to be executed in each cycle to the start time of the next cycle. A cycle processing end display means for displaying that the execution of all the cycle processing programs has been completed, When the start of all cyclic processing programs to be processed for each cycle is completed, the cyclic processing end display means displays the start and end of all cyclic processing programs, and the cyclic processing execution prohibition display means displays the start of cyclic processing. Cycle processing using a multiprocessor characterized by displaying prohibition and resetting the cycle processing execution prohibition display means at the start of the next cycle after the execution of all the cycle processing programs to be processed in each cycle is completed Method.