JPH0713963A - Method for processing scheduling of vector instruction - Google Patents

Abstract

PURPOSE:To generate an object program having satisfactory usage efficiency in the arithmetic equipment of a vector processing processor by evading a register collision at the time of shifting an instruction. CONSTITUTION:A vector instruction scheduling part 8 is operated before a vector processing processor register assigning part 9 and inputs an intermediate language in a vector forming loop from the intermediate language 3. Information obtained by analizing the reliance between the kind of the arithmetic equipment used by the instruction at each one vector instruction unit and vector data used by the instruction is held in an instruction table in an instruction table generating part 81 and the rearrangement of the intermediate language is executed so as to make instruction arrangement in accordance with the configuration ratio of the arithmetic equipment of the vector processing processor based on the instruction table in an instruction arranging part 82.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector instruction scheduling method, and more particularly, to a vector processor having a plurality of arithmetic units capable of operating in parallel in a compiler for generating an object program from a source program, The present invention relates to a vector instruction scheduling method suitable for improving the usage efficiency of arithmetic units of a vector processor to generate a target program with good execution performance.

[0002]

2. Description of the Related Art As a vector instruction scheduling processing method, for example, as shown in Japanese Patent Laid-Open No. 149570/1983, a partial instruction string having a dependency relationship is extracted from an instruction string to which a vector register of a vector processor is assigned. As one instruction group, a plurality of instruction groups that do not depend on each other are extracted, an execution simulation of one instruction group is performed to find a vacancy of an arithmetic unit, and an instruction that uses the arithmetic unit is applied from another instruction group. The method is known.

[0003]

The above conventional method has a sufficient effect in the range where register collision does not occur between instruction groups having no dependency. However, since the instruction sequence after allocating the vector register of the vector processor is the target of scheduling, even if there is no dependency relationship between instruction groups, register collision will occur when the instructions move. There is a problem that the instruction cannot be moved even if there is a vacancy in the computing unit, that is, the vacancy in the computing unit cannot be eliminated, which hinders the improvement of the usage efficiency of the computing unit.

Therefore, an object of the present invention is to provide a vector for avoiding register collision when moving instructions between non-dependent instruction groups to reduce the vacancy of the arithmetic unit and to improve the utilization efficiency of the arithmetic unit. It is to provide an instruction scheduling processing method.

[0005]

According to the present invention, in order to achieve the above object, a target program is generated from a source program for a vector processor having a plurality of arithmetic units that can operate in parallel. In the compiler, the vector instruction scheduling process is performed before the process of allocating the vector register of the vector processor.

In this vector instruction scheduling process, the information obtained by analyzing the dependency relation of the vector data used in the vector instruction and the type of the arithmetic unit used in the instruction is associated with the vector instruction for each vector instruction unit. The prepared instruction table is held, and instructions are arranged according to the composition ratio of the arithmetic units of the vector processing processor, that is, the ratio of the number of load / store arithmetic units to the number of arithmetic / logical arithmetic units based on the instruction table.

[0007]

Before the vector register allocation of the vector processor, the intermediate word for the vectorization loop in the source program is input, and the dependency of the vector data used in the vector instruction for each vector instruction unit, and The information obtained by analyzing the type of the arithmetic unit used in the instruction is held in an instruction table prepared for the vector instruction, and based on the instruction table, the composition ratio of the arithmetic units of the vector processor, that is, the number of load / store arithmetic units. A vector instruction that allocates instructions according to the ratio of the number of arithmetic and logical arithmetic units is scheduled, and after that, the vector register of the vector processor is allocated to generate a target program with efficient use of arithmetic units. be able to.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a compiler to which the present invention is applied. This compiler 1 generates an object program from a source program for a vector processor having a plurality of arithmetic units that can operate in parallel. As its constituent parts, a source program analysis section 5, a loop analysis section 6, and a vector. There is a generalization loop analysis unit 7, a vector instruction scheduling unit 8, a vector processing processor register allocation unit 9, a storage allocation unit 10, a scalar processing processor register allocation unit 11, and an object program output unit 12. The vector instruction scheduling unit 8
The instruction table creating unit 81 and the instruction arranging unit 82 are included.

The outline of the operation of the compiler 1 is as follows. The source program analysis unit 5 reads the source program 2 in the mass storage device and converts it into the intermediate language 3. The loop analysis unit 6 inputs the intermediate language 3 to analyze the control flow of the source program to detect the conditional structure and the loop structure, and at the same time, checks the definition / reference relationship of variables and array data to perform dependency analysis. To do. The vectorization loop analysis unit 7 detects a vector executable loop structure and converts it into a vectorization loop structure.

The vector instruction scheduling unit 8 rearranges the intermediate words so that the instruction arrangement improves the usage efficiency of the arithmetic units. Details of this processing will be described later.

The vector processing processor register allocating unit 9 allocates the vector register of the vector processing processor to the intermediate word in the vectorization loop. The storage allocation unit 10 allocates a data area necessary for executing the target program. The scalar processing processor register allocation unit 11 allocates the registers of the scalar processing processor used in the scalar instruction. The target program output unit 12 outputs the target program 4, which is a machine instruction word, to the mass storage device.

Next, the operation of the vector instruction scheduling unit 8 which is the main part of the present invention will be described in detail. As described above, the vector instruction scheduling unit 8 is composed of the instruction table creating unit 81 and the instruction arranging unit 82. Regarding the operation of the instruction table creating unit 81, FIG.
This will be described using the processing flow shown in.

First, an intermediate word of the vectorization loop is input from the intermediate word 3 shown in FIG. 1 (process 101), the intermediate word is scanned in the reverse order of the appearance order of the source program, and the unscanned intermediate word is scanned. It is determined whether there is a word (Process 10)
2). If there is an unscanned intermediate word, the instruction table creating process (process 103 to process 105) is performed.

The instruction table creating process (process 103 to process 105) is as follows. First, one instruction table of the format shown in FIG.
Is initialized (step 103), the type of the arithmetic unit used in the instruction is identified from the scanned intermediate language, that is, one type of the load / store arithmetic unit or the arithmetic / logical arithmetic unit is identified, and The information corresponding to the integer values 0 and 1 is set in the instruction table (process 104). Next, the vector data used in the instruction is detected from the intermediate word that is the scan target, and at the same time, the intermediate word having the dependency relationship is detected from the detected vector data, and the instruction corresponding to the intermediate word having the dependency relationship is detected. Sync bit n in the table (where n is
Is a value corresponding to the instruction operand number in which the vector data is used, and is one of the range of 1 to 4)
Set to N (1). At the same time, the content of the number of instruction chains in the instruction table secured in step 103 is incremented by 1 (step 105). Then, the control is returned to the process 102. The above is the description of the operation of the instruction table creation unit 81.

Next, the operation of the instruction placement unit 82 will be described using the processing flow shown in FIG. First, the instruction table created by the instruction table creating unit 81 is sequentially input, and the instruction table in which all the synchronization bits in the instruction table are OFF (0) can be arranged, Initial registration is performed for each arithmetic unit used in the command (process 201).

Next, the instruction allocation number counter is initialized to 1 (process 202), it is judged whether or not the command table to which the command is allocated is registered (process 203), and if registered, the process 204 is executed. Control is passed, and if not registered, the processing of the instruction placement unit 82 is ended. Process 2
In 04, the number of load / store arithmetic units of the vector processing processor (2 in this embodiment) is set in the arithmetic unit counter, and the process proceeds to load / store instruction allocation processing (processing 205 to processing 206).

Load / store instruction allocation processing (processing 20)
5 to process 206) are as follows. It is determined whether the instruction table in which the arithmetic unit counter is not 0 and the arithmetic unit type is 0 (load / store arithmetic unit) is registered (step 205). If the above condition is satisfied, the control is passed to the instruction rearrangement process 1 (process 206), and if not satisfied, the control is passed to the process 207.

In the instruction rearrangement process 1 (process 206), the arithmetic unit counter is decremented by one, and the one having the largest number of instruction chains in the instruction table is selected from the registered instruction table group, and the instruction table is stored in the instruction table. The corresponding intermediate word is placed at a predetermined position indicated by the instruction placement number counter, and the instruction placement number counter is incremented by one. Further, an intermediate word having a dependency relationship is detected for each of the vector data on the arranged intermediate word, and the vector data in the instruction table corresponding to each of the detected intermediate words is used. The synchronization wait corresponding to the instruction operand position is turned off (0) to cancel the synchronization wait. This time,
When all the synchronization bits in the corresponding instruction table are OFF with respect to the intermediate word for which the synchronization waiting is canceled, the instruction table is registered as the instruction can be arranged. Then, the instruction table corresponding to the arranged intermediate language is deleted, and the process 2
Return control to 05.

In step 207, the number of arithmetic / logical arithmetic units of the vector processing processor is set in the arithmetic unit counter (2 in this embodiment).
Set), and arithmetic / logical instruction allocation processing (processing 2)
08 to process 209). Arithmetic / logical instruction allocation processing is performed when the arithmetic unit counter is not 0 and the arithmetic unit type is 1
It is determined whether or not an instruction table, which is (arithmetic / logical operation unit), is registered (step 208). If the above condition is satisfied, control is passed to the instruction rearrangement process 2 (step 209). Returns control to process 203. The instruction rearrangement process 2 performs the same process as the instruction rearrangement process 1 and returns the control to the process 208.

The vector instruction scheduling unit 8 operates as described above, and schedules the intermediate words in the vectorization loop so that instructions are arranged according to the composition ratio of the arithmetic units of the vector processing processor.

An example of vector instruction scheduling to which the scheduling method of the present invention is applied is shown below.

FIG. 5 is obtained by inputting the source program 1 into the compiler 1 shown in FIG. 1 and subjecting the source program analyzing section 5, loop analyzing section 6 and vectorized loop analyzing section 7 to predetermined processing. An example of the intermediate word of the vectorization loop used is shown. A scheduling example using this intermediate language example will be described.

The instruction table creating unit 81 scans the intermediate words shown in FIG. 5 in reverse order, that is, in the order of, ..., And the type of arithmetic unit used in the instruction and the vector used in the instruction for each intermediate word. An instruction table shown in FIG. 6 is created by analyzing the data dependency.

The instruction arranging unit 82 inputs the instruction table shown in FIG. 6 in this order, ..., And the load / store arithmetic unit capable of arranging the instruction table in which all the synchronization bits are OFF. Is initially registered as an instruction using, and the instruction table is chained in the order of ,,,.

Next, since the instruction allocation number counter is set to 1 and the instruction table (,,,) to which the instruction is to be allocated is registered, the load / store operation unit number is set to 2 in the operation unit counter and the load is performed. • Performs store instruction allocation processing. By this placement processing of load / store instructions, the intermediate word corresponding to the instruction table is placed as the first instruction, and the synchronization bit 2 of the instruction table is turned off.
Delete the instruction table. Further, since the intermediate word corresponding to the instruction table is arranged as the second instruction and all the synchronization bits of the instruction table are turned off at the same time that the synchronization bit 3 of the instruction table is turned off, the instruction table can be placed in the instruction. Register as an instruction that uses an arithmetic / logical operation unit and delete the instruction table. Then, set the number of arithmetic / logical arithmetic units to the arithmetic unit counter,
Arrangement of arithmetic and logic instructions is performed. By the arithmetic / logical instruction arrangement process, the intermediate word corresponding to the instruction table is arranged as the third instruction, and the synchronous bit 2 of the instruction table is turned off, and at the same time, all the synchronous bits of the instruction table are turned off. The instruction table is registered as an instruction that uses a load / store arithmetic unit that can allocate instructions, and the instruction table is deleted.

As described above, while the instruction table to be arranged is registered, the arrangement process of the load / store instruction and the arrangement process of the arithmetic / logical instruction are repeated, so that FIG.
It becomes the arrangement of the intermediate language shown in.

In order to compare the use efficiency of the arithmetic unit of the intermediate word of the vectorization loop before scheduling (FIG. 5) and the intermediate word of the vectorization loop after scheduling (FIG. 7), each instruction Timing charts are shown in FIGS. 8A and 8B. As can be easily understood from this timing chart, the use efficiency of the arithmetic unit is improved by the scheduling process of the present invention.

[0028]

As described above, according to the vector instruction scheduling processing method of the present invention, it is possible to perform instruction scheduling while avoiding register collision between instructions having no dependency, thereby improving the usage efficiency of arithmetic units. The generated target program can be generated, and the execution time of the target program can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a compiler to which the present invention is applied.

FIG. 2 is a flowchart of an instruction table creating process in a vector instruction scheduling unit.

FIG. 3 is a flowchart of an instruction placement process in a vector instruction scheduling unit.

FIG. 4 shows an example of contents of an instruction table.

FIG. 5 shows an example of an intermediate word of a vectorization loop.

6 shows an example of creating an instruction table for the intermediate language of FIG.

FIG. 7 shows an arrangement of intermediate words after instruction scheduling processing of the intermediate words of FIG.

8 (a) is an instruction timing chart of the intermediate language of FIG. (B) It is an instruction timing chart of the intermediate language of FIG. 7.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 compiler 2 source program 3 intermediate language 4 object program 5 source program analysis unit 6 loop analysis unit 7 vectorized loop analysis unit 8 vector instruction scheduling unit 81 instruction table creation unit 82 instruction placement unit 9 vector processing processor register allocation unit 10 Storage allocation unit 11 Scalar processing processor Register allocation unit 12 Target program output unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiro Aida 5030 Totsuka-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Software Development Division, Hitachi, Ltd. (72) Hiroyuki Sone Inoue-cho, Naka-ku, Yokohama City, Kanagawa Prefecture 81 Hitachi Software Engineering Co., Ltd. In-house (72) Inventor Hisato Ushijima 6-81 Onoue-cho, Naka-ku, Yokohama-shi Kanagawa Hitachi Software Engineering Co., Ltd. In-house

Claims (1)

[Claims] 1. A vector processing processor having a plurality of arithmetic units capable of operating in parallel, in a compiler for generating an object program from a source program, sequentially inputting intermediate words in a vectorization loop to obtain one vector. Analyzing the dependency of vector data used in the instruction and the arithmetic unit used in the instruction for each instruction, creating an instruction table holding the analysis result, and calculating the vector processor based on the created instruction table A vector instruction scheduling method characterized by performing vector instruction scheduling immediately prior to vector register allocation so that instructions are arranged according to the composition ratio of the device.