JPH0713811B2 - Instruction prefetch method - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a buffer storage (L
The present invention relates to an instruction prefetch method when processing a branch instruction in a pipeline-controlled computer system having BS, GBS).

Conventionally, there is well known a method of improving the effective performance by adopting a pipeline control method in order to improve the processing speed of a computer system and overlapping processing of instructions. Increasing the overlap multiplicity poses a problem of performance degradation due to disturbance of the pipeline during execution of branch instructions.

Therefore, there is a demand for a control method for minimizing the disturbance of the pipeline even when the branch instruction is executed. In addition, in order to improve the processing speed of the computer system, in the computer system having a buffer storage (LBS, GBS) between the arithmetic unit and the main memory (MS), even in the arithmetic unit, Provide a multi-stage instruction buffer,
Instructions are prefetched with a focus on the locality of the distribution of program execution addresses. However, the branch destinations of branch instructions in programs are often at relatively close addresses, and memory elements in recent years are low. Buffer storage with a relatively large move-in unit due to price increase and large capacity
Since the introduction of (GBS) has become easier, the instruction prefetch immediately before the branch instruction often gives good results, and an effective instruction prefetch method is required.

[0004]

2. Description of the Related Art FIGS. 3 and 4 are diagrams for explaining a conventional instruction prefetch operation. FIG. 3 shows a configuration example of a conventional instruction prefetch operation. FIG. 4 is a time chart of the conventional instruction prefetch operation. It is the figure shown by.

In FIG. 3, as a computer system equipped with a buffer storage, there are two hierarchies of a high speed small capacity buffer storage (hereinafter referred to as LBS) 11 and a medium speed large capacity buffer storage (hereinafter referred to as GBS) 12. 1 schematically shows a configuration example of a computer system provided with a buffer storage.

First, when an instruction fetch request 2a is sent from the control unit 20 of the arithmetic unit (CPU) 2, the LBS control unit 1
1a is started, it is searched whether or not a block (for example, a unit of 32 bytes) including the instruction exists in the LBS 11, and when the block exists, the instruction is immediately read out and the arithmetic unit (CPU ) 2 is stored in the instruction buffer 21 and when the block does not exist, a move-in request is sent to the upper GBS control unit 12a, and the block is moved from the GBS 12 to the LBS 11 and the start address of the block is moved. The relevant instruction is read and the above instruction buffer 2
Operates as stored in 1.

When the block does not exist in GBS 12, it is moved in from main memory (MS) 1 in the same manner. The instructions stored in the instruction buffer 21 are sequentially read and decoded by the instruction decoder 21a to execute a specific operation.

In a pipeline-controlled computer system, each instruction generally has a decode cycle (D), an operand address calculation cycle (A), and an instruction execution cycle (E), as shown in the operation time chart of FIG. When,
It consists of a condition code check cycle (C) and a general register write cycle (W), and as shown in the figure, the operation pipeline (E) of any instruction is always executed in the operation pipeline. In addition, each instruction is controlled so that it is processed in an overlapping manner. However, the instruction execution cycle (E) may be multiple cycles depending on the type of instruction.

At a timing (eg, T2, T3 in FIG. 4) immediately before the execution cycle (E) of this instruction, an instruction prefetch request (PFRQ, RMSIP) 2b is sent to the LBS control section 11a and is being executed. Is pre-fetched for the next instruction, and a plurality of instructions are always stored in the instruction buffer 21, which functions to perform the efficient overlap control.

[0010]

However, when the instruction becomes a branch instruction, the timing of T3 is the branch destination address generation cycle (SA), and the timing of the next T4 is the read cycle of the branch destination instruction (SA). RMSI), in the first execution cycle (E1) of the timing of the T4, the branch condition of the branch instruction is determined, and when the branch is determined, in the same cycle (T4), as shown in the figure, The instruction buffer 21 is cleared, and in the next T5 cycle, the branch destination instruction is set in the instruction buffer 21 and decoded.

In the conventional method, the instruction prefetch request 2b is a branch instruction in the decode cycle (D) of the branch instruction because it has an adverse effect on the instruction fetch of the branch destination of the branch instruction. In the next recognized cycle (T3), for example, the instruction read cycle (RMS
The IP) is suppressed (indicated by "X" in FIG. 4), and the instruction prefetch request 2b is uniformly suppressed or canceled.

Therefore, as described above, in general, the branch destination of a branch instruction in a program is often a relatively close address, especially in a computer system having a medium-speed / large-capacity GBS 12. By the instruction prefetch request 2b immediately before the branch instruction, the move-in by the instruction prefetch request 2b to the GBS 12, LBS 11 is executed first for the instruction fetch of the branch destination of the subsequent branch instruction. As a result, even if there is a favorable effect, if the prefetch request 2b of the instruction is uniformly canceled as described above, there is a problem that the instruction prefetch request 2b cannot be effectively used.

In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a means for executing an instruction prefetch request immediately before a branch instruction without fail and canceling it as needed immediately after the branch condition of the branch instruction is judged. To do.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the present invention,
Between the main memory (MS) 1 and the arithmetic unit (CPU) 2, for example, has a high speed small capacity buffer storage (LBS) 11 and a medium speed large capacity buffer storage (GBS) 12, and further
In a pipeline-controlled computer system equipped with an instruction prefetch circuit that operates based on instruction prefetch request 2b, and an instruction buffer, the buffer storage (LBS 11, or GBS 11 12) is provided with a judgment circuit 23 for judging whether or not the instruction of the branch destination instruction address (target fetch address) of the branch instruction is included in the block transferred to
When it is determined that the instruction of the instruction address of the branch destination is included in the block moved in by the instruction prefetch request 2b, the instruction prefetch request 2b is validated and When it is determined that the instruction of the instruction address is not included in the block moved in by the instruction prefetch request 2b, the instruction prefetch request 2b is canceled.

[0015]

That is, according to the present invention, for example, a high speed small capacity buffer storage (LBS) and a medium speed large capacity buffer storage (GSS) are provided between the main memory (MS) and the arithmetic unit (CPU).
BS), a pipeline control computer system having an instruction prefetch circuit based on an instruction prefetch request and an instruction buffer, and the buffer storage (LBS, or , GBS) is provided with a judgment circuit for judging whether or not the instruction of the instruction address of the branch destination of the branch instruction (target fetch address) is included in the block transferred to the GBS). When it is determined that the instruction of the instruction address of the branch destination is included in the block moved in by the instruction prefetch request, the instruction prefetch request is validated, and the instruction of the instruction address of the branch destination is , It is determined that the block is not included in the block moved in by the instruction prefetch request. If the, since those that so as to cancel the instruction prefetch request,
Improve the hit rate in GBS or LBS of the branch destination instruction,
This has the effect of improving the performance of the computer system.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a block diagram of one embodiment of the present invention, and FIG. 2 is a diagram showing an instruction prefetch operation according to the present invention in a time chart. The instruction prefetch cancel request 2c in FIG. The decision circuit 23 for controlling the instruction prefetch cancel request 2c and the related mechanism are the functional blocks necessary for implementing the present invention. The same reference numerals indicate the same objects throughout the drawings.

Even if the present invention is carried out, the instruction fetch operation for the LBS 11, GBS 12, and the main memory (MS) 1 and the move-in operation associated with the instruction prefetch request are not particularly changed, and are omitted here. The instruction prefetch method according to the present invention will be described with reference to the time chart of FIG. 2 with reference to FIG. 1 focusing on the control operation for the instruction prefetch cancel request 2c.

First, in the present invention, the instruction prefetch request 2b immediately before the branch instruction is always executed, and the move-in operation according to the instruction prefetch request 2b is judged.
It is characterized in that it is controlled so as to be effective or canceled depending on.

In the embodiment of FIG. 2, for example, the instruction prefetch address immediately before the branch instruction (ie, the address of the block transferred to GBS 12 or the like by the move-in accompanying the instruction prefetch request 2b) and the branch destination A decision circuit 23 that compares the instruction address (target fetch address) is provided, and both are GBS 12, or LBS.
11 same block (64 bytes / 128 bytes / 256
Byte, or 32 bytes) is determined at the timing of T4, the instruction prefetch request 2b immediately before the branch instruction is validated by suppressing the bias to the instruction prefetch cancel request 2c. If it is determined that they are not the same block, GBS 12,
Alternatively, the instruction prefetch operation is controlled to be canceled immediately before the move-in to the LBS 11. {Specifically, an instruction prefetch cancel request (PF CANCEL) 2c is issued. : See FIG. 2} By controlling in this way, if the instruction prefetch address immediately before the branch instruction and the branch destination instruction address (target fetch address) belong to the same block on GBS 12, for example, the branch is executed. Instruction prefetch operation to GBS 12 (PFRQ) before the previous instruction fetch request (SA)
Can be started, resulting in the branch target instruction GBS 12
The hit rate above can be improved.

As described above, according to the present invention, the instruction prefetch request immediately before the execution of the branch instruction is always executed, and the move-in operation to the GBS or LBS accompanying the instruction prefetch request is suppressed if necessary. A control mechanism for canceling the prefetch request, for example, a circuit for determining whether the instruction at the branch destination address of the instruction is included in the block by the instruction prefetch request that has been moved into the buffer storage (LBS, or GBS) is provided. It is characterized in that the valid / invalid (cancel) of the instruction prefetch request can be controlled arbitrarily.

In the above embodiment, the main memory (M
S) and the arithmetic unit (CPU) between the high speed small capacity buffer storage (LBS) and the medium speed large capacity buffer storage (G
However, the present invention is not limited to a computer system having such a multi-stage buffer storage (LBS, GBS), and the LBS, GBS
It goes without saying that any one-stage computer system may be used.

[0022]

As described above in detail, the instruction prefetch method according to the present invention has a main memory (MS) and an arithmetic unit (C).
PU) has, for example, a high-speed small-capacity buffer storage (LBS) and a medium-speed large-capacity buffer storage (GBS), and further performs an instruction prefetch operation based on an instruction prefetch request. In a pipeline-controlled computer system that has a circuit to execute and an instruction buffer, check whether the instruction at the branch destination address of the branch instruction is included in the block transferred to LBS, GBS by move-in by the above instruction prefetch request. By providing a determination circuit for determination, based on the determination content of the determination circuit,
By providing a means for controlling the instruction pre-cancellation request, when the instruction pre-fetch request is determined to be valid, the pre-fetch request immediately before the branch instruction is validated. Or LBS
It has the effect of increasing the hit rate in and improving the performance of the computer system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a time chart of an instruction prefetch operation according to the present invention.

FIG. 3 is a diagram explaining a conventional instruction prefetch operation (No. 1).

FIG. 4 is a diagram explaining a conventional instruction prefetch operation (part 2).

[Explanation of symbols]

 1 Main memory (MS) 11 Buffer storage (LBS) 12 Buffer storage (GBS) 11a LBS control unit, 12a GBS control unit 2 Arithmetic unit (CPU) 20 Control unit 2a Instruction fetch request 2b Instruction prefetch request (PFRQ, RMSIP) 2c Instruction prefetch cancel request 21 Instruction buffer, 23 Judgment circuit,

Claims (1)

[Claims] 1. A main memory device (1) and a computing device (2),
In a pipeline-controlled computer system that includes a buffer storage (11, 12) and an instruction prefetch circuit that operates based on an instruction prefetch (prefetch) request (2b), and an instruction buffer, the above instruction prefetch A determination circuit (23) that determines whether or not the block transferred to the buffer storage by the move-in by the request (2b) includes the instruction of the instruction address (target fetch address) of the branch destination of the branch instruction. And the decision circuit (23) determines that the instruction at the instruction address of the branch destination is
When it is determined that the block is moved in by the instruction prefetch request (2b),
When it is determined that the instruction prefetch request (2b) is valid and the instruction at the branch destination instruction address is not included in the block moved in by the instruction prefetch request (2b), the instruction An instruction prefetch method characterized by canceling a prefetch request (2b).