JPH0713779B2 - Sequence controller - Google Patents

Description

The present invention relates to a sequence controller that performs sequence processing at high speed.

[Conventional technology]

As a conventional sequence controller, JP-A-60-1818
There is one described in No. 36. Here, a bit register for exchanging data with a process input / output device (hereinafter abbreviated as PIO), an arithmetic unit, and an accumulator for storing the arithmetic result are provided in the sequence controller. When an instruction or an OR instruction is executed, next, data is read from the PIO to the bit register, then the logical operation is performed by the arithmetic unit, and finally the arithmetic result is stored in the accumulator. In addition, here, according to the ladder diagram that constitutes the program of the sequence instruction,
It is shown that the above processing is performed for all instructions. In such a processing method, execution time is required for all sequence instructions, and each sequence instruction requires logical operation time.

[Problems to be solved by the invention]

An object of the present invention is to bypass unnecessary sequence instructions and to obtain the same result as executing a logical operation only by exchanging data between PIO and a bit register without executing the logical operation. To speed up sequence processing.

[Means for solving problems]

The principle for achieving the above object will be described with reference to the drawings.

The tenth item is a ladder diagram showing an example of the AND processing. I1
Is a read instruction (hereinafter abbreviated as LD instruction), I2 is an AND instruction, I
Reference numeral 3 is an output instruction, and the addresses of the PIOs targeted by these instructions are indicated by PIO1 to PIO3, respectively.

This AND processing is the 11th
The flow was as shown in the figure. Here, Dr indicates a bit register, Acc indicates an accumulator, and → indicates data transfer.
However, when PIO1 is "0", the operation result is "0" regardless of the value of PIO2. Therefore, it suffices to carry out the flow shown in FIG. 12 and, in FIG. 11, (c), (d), (e),
Each processing of (f) and (h) can be omitted, and the processing speed can be increased. On the other hand, when PIO1 is "1", the calculation result is the same as the value of PIO2. Therefore, it suffices to carry out the flow shown in FIG. 12, and the steps (c), (f) and (h) in FIG.
Each process can be omitted, and the process can be speeded up. In other words, if the content of the bit register is "0", the AND instruction should be bypassed, and if the content of the bit register is "1",
Executes the AND instruction, but does not require arithmetic processing, simply PIO
It is only necessary to read the data in the bit register.

FIG. 13 is a ladder diagram showing an example of the OR process. I4 is
LD instruction, I5 is an OR instruction, and I6 is an output instruction.

The conventional sequence controller performs this OR processing according to the flow shown in FIG. However, when PIO4 is "1", the operation result is "1" regardless of the value of PIO5. When PIO4 is "0", the operation result is the same as the value of PIO5. Therefore, the flow shown in FIG. 15 may be performed, and the processing speed can be increased. In other words, if the content of the bit register is “1”, the OR instruction should be bypassed. Conversely, if the content of the bit register is “0”, the OR instruction is executed, but no arithmetic processing is required. Simply read the PIO data into the bit register.

The technical means for realizing the above-described principle is a means for reading an instruction from the instruction memory and a bit register for storing the logical data read from the PIO, which is connected to the instruction memory storing the sequence instruction and the PIO. In a sequence controller equipped with a means for exchanging data between the PIO and the bit register,
The sequence controller is provided with a first instruction address part and a second instruction address part which indicate two different sequence instructions, and the sequence controller stores an instruction register for storing the sequence instruction and bit register contents of "1" and "0". This is achieved by a selector that selects the first instruction address portion and the second instruction address portion, respectively, corresponding to the case, and a control circuit that sequentially executes the sequence instruction pointed to by the instruction address selected by the selector.

[Action]

More specifically, in the ladder diagram, AND instructions are written so as to be lined up in a certain first direction, and OR instructions are written so as to be lined up in a second direction different from the first direction. The first instruction address part of each sequence instruction indicates the AND instruction connected in the first direction in the ladder diagram.
When there is no ND instruction, it indicates an output instruction, and the second instruction address part indicates an OR instruction connected in the second direction, but when there is no OR instruction, it indicates an output instruction. By defining the first instruction address portion and the second instruction address portion as described above, when the content of the bit register is "1", the execution of the OR instruction is bypassed to the AND instruction or the output instruction. Go to AND if the bit register contents are "0"
Bypass instruction and proceed to OR or output instruction. Further, in the execution of the OR instruction or the AND instruction after the bypass, the arithmetic processing is not necessary, and the PIO data is read and stored in the bit register.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which comprises an instruction memory 1, a PIO 2 and a sequence controller 3. The sequence controller 3 comprises an instruction register 4, a selector 5, a control circuit 6, and a bit register 7. , Gates 8-9, instruction data bus 11, instruction address bus 12, buses 13-15, signal line 16
It consists of ~ 20 and so on.

The control circuit 6 has a clock circuit 61, a quinary counter 62, and gate circuits 63 and 64 as main components, and outputs a command read signal 18, a read signal 19, and a write signal 20 which will be described later.

FIG. 2 shows an example of the format of the sequence instruction used in the present invention, which is composed of OP, PAD, AD1 and AD2. OP is an operation code indicating the type of instruction, which is 1 bit in the present embodiment, and when it is "0", read from PIO (hereinafter referred to as read) processing,
When it is "1", write processing to PIO (hereinafter referred to as write processing) is performed. PAD is the address of PIO. Although AD1 and AD2 are a first instruction address part and a second instruction address part which indicate two different sequence instructions, both are absolute addresses of the sequence instruction in this embodiment.

Next, the operation of this embodiment will be described.

To read an instruction, an instruction read signal is output from the control circuit 6 onto the signal line 18, and the instruction in the instruction memory 1 is set in the instruction register 4 via the bus 11. The instruction address at this time is from the selector 5 via the bus 12 to the instruction memory 1
Is output to. From the instruction register 4, the operation code OP is output to the control circuit 6 via the signal line 16,
D is output to PIO2 via bus 15 and the instruction address AD1
AD2 is output to the selector 5 via the buses 13 and 14, respectively. The control circuit 6 turns on the gate 64 at a predetermined timing when the operation code OP is “0” and performs a read operation, and turns on the gate 63 at a predetermined timing when the OP is “1”. , Write operation is performed. In the read operation, the PIO read signal is output from the control circuit 6 onto the signal line 19, and the data in the PIO2 is set to the bit register 7 via the signal line 17 and the gate 8. In the write operation, the PIO write signal is output from the control circuit 6 onto the signal line 20, and the data in the data register 7 is written into the PIO 2 via the gate 9 and the signal line 17. The selector 5 outputs the instruction address AD1 when the content of the bit register 7 is “1”,
When it is "0", the instruction address AD2 is output to the instruction memory 1 via the bus 12. When the read operation or the write operation is completed, the control circuit 6 starts reading the instruction. Since the address of the instruction read at this time is the address output from the selector 5, the content of the bit register 7 is "1".
When, the instruction designated by AD1 is proceeded to, and when the content of the bit register 7 is "0", the instruction designated by AD2 is proceeded to.

The time chart for the read operation is shown in FIG. In this figure, the read data from the PIO is indicated by x. The instruction address becomes AD1 when x is "1" and becomes AD2 when x is "0". The latch timing of the instruction register 4 is the fall of the instruction read signal, and the latch timing of the bit register 7 is the fall of the PIO read signal.

The time chart of the write operation is shown in FIG. In this figure, the contents of the bit register are indicated by y. The instruction address becomes AD1 when y is “1” and becomes AD2 when y is “0”.

Next, the coding of the sequence instruction will be described by taking the following arithmetic expression (S) as an example.

(PIO10 / PIO11 + (PIO12 + PIO13) / PIO14) / (PIO15
+ PIO16) = PIO17 ... Operational expression (S) Here, ·, +, and = are AND symbols, OR symbols, and output symbols, respectively, and the processes with these symbols are AND instructions, OR, respectively.
Execute with instructions and output instructions. In addition, the processing without the symbol is
Execute with LD instruction.

Although the arithmetic expression (S) is written in the ladder diagram, in the present embodiment, the AND instructions are written so as to be arranged in the right direction, and the OR instruction is written in the downward direction. Figure 5 shows
1 illustrates a concept of a notation method in an embodiment of the present invention. The AND instruction for the instruction of a is written at the position of b on the right side of the a, the AND instruction for the instruction of b is written at the position of c on the right side of the b, and the OR instruction for the instruction of a is written at the lower position of i. It is written in the position, and the OR command for this command is written in the position of e under the d.

FIG. 6 is a diagram in which the arithmetic expression (S) is represented in a ladder diagram according to the method of this table. I10 is an LD instruction, I11, I14, I15 are AND instructions, I12, I13, I16 are OR instructions, and I17 is an output instruction, and the PIO addresses that are the targets of these instructions are shown by PIO10 to PIO17.

AD1 in each instruction is determined so as to point to an AND instruction connected to the right in the ladder diagram, and is determined to point to an output instruction when there is no AND instruction. Therefore, the next instruction indicated by AD1 of each instruction is the instruction indicated by the arrow in FIG.

Also, AD2 in each instruction is decided to point to the OR instruction connected downward in the ladder diagram.
When there is no command, the output command is pointed to.
Therefore, the instruction indicated by AD2 of each instruction is the instruction indicated by the arrow in FIG.

The above analysis results in FIG. 9 when the ladder diagram shown in FIG. 6 is coded. Since the output instruction performs the write operation, OP becomes “1”, and the read operation other than the output instruction causes the OP to become “0”. Also, AD1, AD2 in each instruction
Are instructions indicated by arrows in FIGS. 7 and 8, respectively.

When the instruction of FIG. 9 is executed, the same result as the operation result of the operation expression (S) is obtained.
It shows that it is a figure.

In the ladder diagram notation method in the present embodiment, the AND instructions are written so as to be arranged in the right direction, and the OR instructions are shown so as to be arranged in the downward direction. There is no problem, the principle in that case is the same, and it is obvious that the same effect is obtained.

Although the first instruction address portion AD1 and the second instruction address portion AD2 in this embodiment are both absolute addresses of sequence instructions, they may be any addressing.

In addition, this embodiment shows an example of a sequence controller that executes a 1-bit sequence operation. However, even if it is executed by a sequence controller that has both a 1-bit sequence operation function and a numerical operation function, no problem occurs. Nonetheless, it is clear that the operating principle of the present invention is the same and the same effect.

〔The invention's effect〕

According to the present invention, an unnecessary sequence instruction is bypassed, and the same result as when a logical operation is executed only by exchanging data between the PIO and the bit register can be obtained without executing the logical operation. It has the effect of speeding up.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an instruction format diagram, FIGS. 3 and 4 are time charts, and FIG.
Figures are conceptual diagrams of ladder diagram notation method, Fig. 6, Fig. 7, Fig. 8
Fig. 9 is a ladder diagram, Fig. 9 is a coding diagram of Fig. 6, and 10
The figure is a ladder diagram, FIGS. 11 and 12 are the process flow diagrams of FIG. 10, FIG. 13 is the ladder diagram, and FIGS. 14 and 15 are the process flow diagrams of FIG. 1 ... Instruction memory, 2 ... PIO, 3 ... Sequence controller, 4 ... Instruction register, 5 ... Selector, 6 ... Control circuit,
7 ... Bit register.

Claims (1)

[Claims] 1. A command memory in which a sequence command is stored and a process input / output device, means for reading the command from the command memory, and a bit register for storing the logical data read from the process input / output device. A sequence controller having means for exchanging data between a process input / output device and a bit register, wherein the sequence command includes an AND command connected in a predetermined first direction in a ladder diagram and the first command. Including an OR instruction connected in a second direction different from the direction,
The sequence controller has a first instruction address part for designating an address of an AND command and a second instruction address part for designating an address of the OR command, and the sequence controller has an instruction register for storing the sequence command, When the first instruction address portion and the second instruction address portion stored in the instruction register are input to transfer the logical data from the process input / output device, the contents of the bit register are logical "1". 1 and an selector for selecting the second instruction address part when it is a logical "0", and when the content of the bit register is a logical "1", the selector By selecting the instruction address portion of 1, the execution of the OR instruction is bypassed and the operation shifts to the AND instruction, and in the case of logic "0",
By selecting the second instruction address part, the AND
Bypass execution of the instruction and move to the OR instruction,
A sequence controller characterized in that, when the AND instruction or OR instruction is executed, an operation result is obtained only by transferring logical data from the process input / output device to the bit register.