JPH07135462A - Semiconductor logic circuit and its output coupling circuit - Google Patents

Abstract

PURPOSE:To prevent the increase in power consumption and the destruction of elements at the coupling of plural circuits by connecting a Schottky barrier diode blocking a reverse current between a drain of a PMOS transistor(TR) and an output terminal. CONSTITUTION:A Schottky barrier diode 2 is connected between a drain D of a PMOS transistor(TR) and an output terminal 7 in the semiconductor conductor logic circuit in a direction of blocking a current flowing to the TR 1. Thus, even when a voltage higher than a voltage V at a power terminal 6 is applied to the output terminal 7 due to some cause, the high voltage is effectively blocked by the reverse direction transmission characteristic of the diode 2. Thus, no high voltage is sent to the TR 1 and an undesired TR current and diode current flows based on the high voltage. Thus, even when output terminals of the 1st and 2nd semiconductor logic circuits different from the voltage are connected in common to the coupling bus, the increase in the power consumption of the circuit in the stop state and operating state is suppressed and the destruction in the pause state circuit is prevented in advance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit and an output coupling circuit of the semiconductor logic circuit, and more particularly, to a good power consumption reduction characteristic for a combination of a plurality of semiconductor logic circuits having different power supply voltages. The present invention relates to a semiconductor logic circuit and an output coupling circuit of the semiconductor logic circuit.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor logic circuit, the output terminals and the like of two or more semiconductor logic circuits are sometimes connected to a common coupling bus, and the semiconductor logic circuit used at that time is , Not only those with the same power supply voltage value, but also those with different power supply voltage values.

FIG. 11 is a circuit diagram showing a first configuration example (hereinafter referred to as a known first coupling configuration example) when two semiconductor logic circuits are coupled by a known means. In this example, the output terminals of two semiconductor logic circuits having different power supply voltage values are connected.

In FIG. 11, 100 is a first semiconductor logic circuit, 101 is a first PMOS transistor having a source S, a gate G, a drain D and a substrate B, and 102 is a source S, a gate G, a drain D and a substrate B. , A first pre-driver circuit 103, a first parasitic diode 104 formed between the drain D of the first PMOS transistor 101 and the substrate B, and a voltage 105 of 3V. First power supply terminal, 1
06 is an output terminal, 107 is a connection bus, 110 is a second semiconductor logic circuit, 111 is a second PMOS transistor having a source S, a gate G, a drain D, and a base B, 11
2 is a second NMOS transistor having a source S, a gate G, a drain D, and a base B, 113 is a second pre-driver circuit, and 114 is formed between the drain D and the base B of the second PMOS transistor. Second parasitic diode, 115 is a second power supply terminal to which a voltage of 5V is supplied, 1
16 is an output terminal.

The first semiconductor logic circuit 100 and the second semiconductor logic circuit 110 are respectively formed of large-scale integrated circuits (LSIs).
In the semiconductor logic circuit 100, the first PMOS transistor 101 constitutes a pull-up circuit, and the source S and the base B are commonly connected to the first power supply terminal 105 and the gate G.
Is connected to the output terminal of the first pre-driver circuit 103, and the drain D is connected to the output terminal 106. First NM
The OS transistor 102 constitutes a pull-down circuit,
The drain D is connected to the drain D of the first PMOS transistor 101, the gate G is connected to the output terminal of the first predriver circuit 103, and the source S is connected to the reference potential point. On the other hand, in the second semiconductor logic circuit 110, the second PMOS transistor 111 constitutes a pull-up circuit, and the source S and the base B are commonly used by the second power supply terminal 11
5, the gate G is connected to the output terminal of the second pre-driver circuit 113, and the drain D is connected to the output terminal 116. The second NMOS transistor 112 constitutes a pull-down circuit, the drain D is the drain D of the second PMOS transistor 111, the gate G is the output terminal of the first pre-driver circuit 113, and the source S is the reference potential point. Each is connected. The output terminals 106 and 116 of the first and second semiconductor logic circuits 100 and 110 are interconnected via a connection bus 107.

In the above configuration, in the first semiconductor logic circuit 100, when one or a plurality of control signals are supplied to the input terminal of the first predriver circuit 103, the first predriver circuit 103 is turned on. A predetermined logic operation is performed in response to the control signal, and the first PMOS transistor 101 and the first NM are controlled by the logic signal obtained at the output terminal thereof.
The OS transistor 102 is logically driven, and the first PMOS
Transistor 101 and first NMOS transistor 1
02 is alternately turned on and off to generate a logic 1 or a logic 0 at the output terminal 106, or the first PMO.
The S transistor 101 and the first NMOS transistor 102 are turned off at the same time to cause a high impedance state at the output terminal 106. On the other hand, the same applies to the second semiconductor logic circuit 110, and when one or more control signals are supplied to the input terminal of the second predriver circuit 113, the second predriver circuit 113 , A predetermined logical operation is performed in response to the control signal, and the second PMOS transistor 111 and the second NMOS transistor 112 are logically driven by the logical signal obtained at the output terminal, and the second PMOS transistor 111 is driven. And the second NMOS transistor 112 are alternately turned on and off to generate a logic 1 or a logic 0 at the output terminal 116, or to turn off the second PMOS transistor 111 and the second NMOS transistor 112 at the same time. , A high impedance state is generated at the output terminal 116.

Next, FIG. 12 is a circuit diagram showing a second configuration example (hereinafter referred to as a known second coupling configuration example) in the case where two semiconductor logic circuits are similarly coupled by a known means. This is an example in which two semiconductor logic circuits having different power supply voltage values are connected in cascade.

In FIG. 12, 120 is a third semiconductor logic circuit, 121 is a third PMOS transistor having a source S, a gate G, a drain D and a substrate B, and 122 is a source S, a gate G, a drain D and a substrate B. , A third NMOS transistor having a resistor 123, a pull-up resistor connected between the source S and the gate G of the third PMOS transistor, a third power supply terminal 124 to which a voltage of 5 V is supplied, an output terminal 125, Reference numeral 126 denotes an input terminal, and other components that are the same as the components shown in FIG. 11 are given the same reference numerals.

Then, the third semiconductor logic circuit 120 is
Together with the first semiconductor logic circuit 100, it is composed of a separate large-scale integrated circuit (LSI). In the third semiconductor logic circuit 120, the third PMOS transistor 12
Reference numeral 1 denotes a pull-up circuit in which the source S and the base B are commonly connected to the third power supply terminal 125 and the gate G is connected to the input terminal 12
6, the drain D is connected to the output terminal 125, respectively. The third NMOS transistor 122 is a pull-down circuit, and the drain D is the drain D of the third PMOS transistor 121 and the gate G is the input terminal 12.
6, the sources S are connected to the reference potential points, respectively. In addition, the pull-up resistor 123 is the third PMOS.
Between the source S and the gate G of the transistor, that is, the third
Connected between the power supply terminal 125 and the input terminal 126 of
The output terminal 106 of the first semiconductor logic circuit 100 is interconnected to the input terminal 126 of the third semiconductor logic circuit 120 through the connection bus 107.

In the above configuration, the operation of the first semiconductor logic circuit 100 is the same as the operation of the first semiconductor logic circuit 100 of the example shown in FIG. 11, so the description of the operation at this point will be omitted. . On the other hand, in the third semiconductor logic circuit 120, the output terminal 10 of the first semiconductor logic circuit 100 is
When a signal of logic 1 or logic 0 is sent from 6, the third PMOS transistor 12 depending on the signal state thereof.
The first and third NMOS transistors 122 are turned on and off, and the output terminal 125 thereof is similarly logic 1 or logic 0.
Signal is generated. In addition, the first semiconductor logic circuit 100
Of the third PMOS transistor 121 is turned off and the third NMO is turned off.
The S transistor 122 is turned on, and the output terminal 125 of the third semiconductor logic circuit 120 is in a logic 0 state.

[0011]

By the way, in the known first coupling configuration example, the first semiconductor logic circuit 1 is used.
When the output terminal 106 of the second semiconductor logic circuit 110 has a high impedance state, the output terminal 11 of the second semiconductor logic circuit 110
When a signal of logic 1 is output from 6, the output terminal 106 of the first semiconductor logic circuit 100 is originally in the high impedance state, but as shown in FIG. Due to the potential difference of 2V formed between the first power supply terminal 105 and the second power supply terminal 115 of the second semiconductor logic circuit 110, the first PMOS transistor 101 and the parasitic diode 104 receive the transistor current It and the parasitic diode 104, respectively. The diode current Id comes to flow.

Therefore, in the known first coupling configuration example, power consumption in the second semiconductor logic circuit 110 is increased, and at the same time, the first semiconductor logic circuit 100 is also caused.
Since the transistor current It and the diode current Id flow in the
Moreover, latchup occurs due to the diode current Id flowing in the base B of the first PMOS transistor,
There is a problem that the first semiconductor logic circuit 100 is destroyed.

In the known second coupling configuration example, when a signal of logic 1 is output from the output terminal 106 of the first semiconductor logic circuit 100, as shown in FIG. First power supply terminal 10 of logic circuit 100
5 and the third power supply terminal 12 of the third semiconductor logic circuit 120.
Due to the potential difference of 2 V formed between the first power supply terminal 124 and the third power supply terminal 124, the first power supply terminal 124 is connected to the first power supply terminal 124 via the pull-up resistor 123.
PMOS transistor 101 and parasitic diode 10
4, the transistor current It and the diode current Id flow in each.

Therefore, in the known second coupling configuration example, power consumption in the third semiconductor logic circuit 120 increases, and at the same time, the first semiconductor logic circuit 100 simultaneously.
Since the transistor current It and the diode current Id flow in the
Moreover, latchup occurs due to the diode current Id flowing in the base B of the first PMOS transistor,
There is a problem that the semiconductor logic circuit 100 is destroyed.

That is, in the above-described known coupling configuration examples, power consumption is unnecessarily increased when signals are transmitted and received between semiconductor logic circuits operated by power supplies having different voltage values, or the base of a PMOS transistor is used. There is a problem that latch-up occurs due to the current flowing through the semiconductor logic circuit, and the semiconductor logic circuit is damaged or destroyed.

The present invention eliminates the above-mentioned problems, and a first object of the present invention is to combine semiconductor logic circuits with each other.
It is to provide a semiconductor logic circuit which can be electrically isolated from other semiconductor logic circuits.

A second object of the present invention is to provide a semiconductor logic circuit in which power consumption does not increase and a failure of an internal circuit does not occur when a plurality of semiconductor logic circuits having different power supply voltage values are combined. An object is to provide an output coupling circuit.

Further, a third object of the present invention is that when a load driven by a power supply having a voltage value different from the power supply voltage value of the semiconductor logic circuit is coupled, the power consumption does not increase and the internal circuit fails and breaks down. There is not to provide a semiconductor logic switching circuit.

[0019]

In order to achieve the first object, according to the present invention, a PMOS transistor having a source and a base commonly connected to a power supply, and an anode having the PMO are provided.
The drain of the S-transistor has a Schottky barrier diode whose cathode is connected to an output terminal, and one end, the other end, and a control end, one end of which is connected to the output terminal and the other end of which is connected to a reference potential point. And a pre-driver circuit having an input end and an output end, the output end of which is connected to the gate of the PMOS transistor and each control end of the first pull-down circuit. First means configured to control ON / OFF of the PMOS transistor and the first pull-down circuit in response to an input signal supplied to the end.

Further, in order to achieve the second object,
The present invention relates to a first semiconductor logic circuit which operates with a first power supply and an output terminal of the first semiconductor logic circuit,
In an output coupling circuit of a semiconductor logic circuit, which comprises a first semiconductor power supply and a second semiconductor logic circuit which operates with a second power supply having a different voltage value, the first semiconductor logic circuit comprises a source and a source. A first PMOS transistor whose base is commonly connected to the first power supply and an anode of the first PMO transistor.
The drain of the S-transistor has a Schottky barrier diode whose cathode is connected to the output terminal, and one end, the other end, and a control end, one end of which is connected to the output terminal and the other end of which is connected to the reference potential point. And a first pre-driver circuit having an input end and an output end, the output end being connected to the gate of the first PMOS transistor and each control end of the first pull-down circuit. Second means configured to control ON / OFF of the first PMOS transistor and the first pull-down circuit in response to an input signal supplied to an input terminal of the first pre-driver circuit. Equipped with.

Further, in order to achieve the third object,
PMOS in which the source and the base are commonly connected to the first power supply
A transistor, an anode connected to the drain of the PMOS transistor, a cathode connected to a Schottky barrier diode connected to an output terminal, and an input terminal and an output terminal;
A pre-driver circuit having an output terminal connected to the gate of the PMOS transistor, and a reactive load device connected between the output terminal and a second power supply having a voltage value different from the voltage value of the first power supply. And a third means configured to control the PMOS transistor to be turned on and off in response to an input signal supplied to the input terminal of the pre-driver circuit, and to switch drive the load device.

[0022]

According to the first means, the semiconductor logic circuit is
Between the drain of the PMOS transistor and the output terminal,
Since the Schottky barrier diode is connected in the direction of blocking the current flowing from the output terminal to the PMOS transistor, even if a voltage higher than the voltage value of the power supply is applied to the output terminal, the high voltage is The Schottky barrier diode electrically isolates the PMOS transistor from causing an unnecessary current to flow therethrough and a power supply from causing an unnecessary current to flow backward.

Therefore, it is possible to obtain a semiconductor logic circuit which is extremely versatile when connecting to another semiconductor logic circuit.

According to the second means, in the output coupling circuit of the semiconductor logic circuit, the PMO from the output terminal is provided between the drain of the PMOS transistor and the output terminal.
Since the first semiconductor logic circuit to which the Schottky barrier diode is connected is used so as to block the current flowing through the S-transistor, the output voltage of the first semiconductor logic circuit is higher than the voltage value of the power supply. Even if a voltage is applied from another semiconductor logic circuit, the high voltage is electrically isolated by the Schottky barrier diode and does not pass unnecessary current through the PMOS transistor.

Therefore, when the first semiconductor logic circuit is connected to another semiconductor logic circuit having a power supply voltage different from the voltage value of the power supply, an increase in power consumption of the other semiconductor logic circuit is suppressed. Not only can it be prevented, but also failure breakdown due to latch-up can be prevented.

Further, according to the third means, in the semiconductor logic switching circuit, the PMO is provided from the output terminal between the drain of the PMOS transistor and the output terminal.
Since the Schottky barrier diode is connected so as to block the current flowing through the S-transistor, the reactive load device connected to the output terminal transiently transits a voltage higher than the voltage value of the power supply of the semiconductor logic circuit. Even if generated, the high voltage is electrically isolated by the Schottky barrier diode, and may cause an unnecessary current to flow through the body of the PMOS transistor or cause an unnecessary current to flow back to the power supply. Disappear.

Therefore, when connecting the semiconductor switching circuit and the reactive load device, it is not necessary to consider the value of the transient voltage generated by the reactive load device, and a semiconductor switching circuit having a great deal of flexibility is provided. Obtainable.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a semiconductor logic circuit according to the present invention, which is an example in which a tristate buffer circuit is constructed.

In FIG. 1, 1 is a PMOS transistor, 2 is a Schottky barrier diode, 3 is one end, the other end, and a first pull-down circuit having a control end, 4 is one end,
A second pull-down circuit having the other end and a control end, 5 is a pre-driver circuit having two input ends and three output ends, 6
Is a power supply terminal, 7 is an output terminal, and 8 ₁ and 8 ₂ are input signals Si
n and the output enable signal OE are input terminals.

The PMOS transistor 1 constitutes a pull-up circuit in which the source S and the base B are commonly connected to the power supply terminal 6, the gate G is an output terminal of the pre-driver circuit 5, and the drain D is a Schottky barrier. It is connected to the anode of the diode 2 and one end of the second pull-down circuit 4, respectively. The cathode of the Schottky barrier diode 2 is connected to the output terminal 7 and one end of the first pull-down circuit 3. The other ends of the first pull-down circuit 3 and the second pull-down circuit 4 are connected to the common potential point, and the control end thereof is connected to the output end of the pre-driver circuit 5, respectively. The input ends of the pre-driver circuit 5 are connected to the input terminals 8 ₁ and 8 ₂ , respectively. In this case, in this embodiment, the Schottky barrier diode 2 and the second pull-down circuit 4 are newly connected, as compared with the first semiconductor logic circuit 100 in the known first and second coupling configuration examples. Things
The other components are not particularly changed.

The operation of the present embodiment having the above-mentioned structure is as follows.

[0033] When the output enable signal OE of logic 0 to the input terminal ₈₂ is input, irrespective of the logic state of the input signal Sin is supplied to the input terminal 8 _1, pre-driver circuit 5
Outputs a logic signal which turns off the PMOS transistor 1 and the first pull-down circuit 3 and simultaneously turns on the second pull-down circuit 4 from its output terminal. At this time, the current path from the power supply terminal 6 to the output terminal 7 and the current path from the output terminal 7 to the reference potential point are cut off, and the output terminal 7 exhibits a high impedance state. Next, when the output enable signal OE supplied to the input terminal 8 ₂ becomes a logic 1 and the input signal Sin supplied to the input terminal 8 ₁ becomes a logic 1, the pre-driver circuit 5 outputs from its output end. A logic signal that turns on the PMOS transistor 1 and simultaneously turns off the first pull-down circuit 3 and the second pull-down circuit 4 is output.
At this time, from the power supply terminal 6 to the PMOS transistor 1
A current path is formed through the Schottky barrier diode 2 and the output terminal 7, whereby a signal of logic 1 is output to the output terminal 7. Subsequently, the output enable signal OE supplied to the input terminal 8 ₂ remains at logic 1,
When the input signal Sin supplied to the input terminal 8 ₁ becomes a logic 0, the pre-driver circuit 5 outputs the PMOS from its output end.
A logic signal that turns off the transistor 1 and simultaneously turns on the first pull-down circuit 3 and the second pull-down circuit 104 is output. At this time, the first from the output terminal 7
A current path is formed through the pull-down circuit 3 to reach the reference potential point, whereby a signal of logic 0 is output to the output terminal 7.

In this operation, the PM
Since the Schottky barrier diode 2 is connected between the drain D of the OS transistor 1 and the output terminal 7, the voltage value V of the power supply terminal 6 is applied to the output terminal 7 due to some cause.
Even if a higher voltage is applied, the higher voltage is effectively blocked by the reverse transfer characteristic of the Schottky barrier diode 2, so that the higher voltage is not transmitted to the PMOS transistor 1 and the higher voltage is applied. Based on the voltage, the above-mentioned undesired transistor current It or diode current Id does not flow in the PMOS transistor 1.

By the way, in this embodiment, instead of connecting the Schottky barrier diode 2 between the drain D of the PMOS transistor 1 and the output terminal 7, it is connected between the power supply terminal 6 and the source S of the PMOS transistor 1. It is possible to connect the Schottky barrier diode 2 to the power supply terminal 6 and the source S of the PMOS transistor 1
When it is connected to the Schottky barrier diode 2, the transistor current It can be prevented but the diode current Id cannot be prevented. Therefore, the connection point of the Schottky barrier diode 2 is optimally the connection point of this embodiment. Is.

In the present embodiment, the reason why the second pull-down circuit 4 is used in addition to the first pull-down circuit 3 is that the speed of switching the signal at the output terminal 7 from logic 1 to logic 0 is increased. The second pull-down circuit 4 may be omitted as appropriate when both the request for speeding up and the request for reducing the shoot-through current are gradual.

Next, FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the semiconductor logic circuit according to the present invention, which is a first circuit diagram.
3 shows detailed circuits in the first and second pull-down circuits 3 and 4 and the pre-driver circuit 5 of the embodiment.

In FIG. 2, 3 ₁ is a first NMOS transistor, 3 ₂ is a second NMOS transistor, 4 ₁ is a third NMOS transistor, 5 ₁ is an inverter circuit,
5 ₂ is a NAND gate, 5 ₃ is a NOR gate, and other components that are the same as those shown in FIG. 1 are denoted by the same reference numerals.

Then, the first pull-down circuit 3 has a first
Of the NMOS transistor 3 ₁ and the second NMOS transistor 3 ₂ , the second pull-down circuit 4 is composed of the third NMOS transistor 4 ₁ , the pre-driver circuit 5 is an inverter circuit 5 ₁ , a NAND gate 5 ₂ , NO
It consists of an R gate 5 ₃ . In the first NMOS transistor 3 ₁ , the drain D is the output terminal 7, the gate G is the power supply terminal 6, and the source S is the second NMOS transistor 3 1.
_{In the second} NMOS transistor 3 ₂ , the gate G is connected to the output of the NOR gate 5 ₃ and the source S is connected to the reference potential point. Third
Of the NMOS transistor 4 ₁ is, drain D is PMOS
The drain D of the transistor 1, the gate G is the output of the NAND gate 5 _2, the source S is connected to the reference potential point. The input of the inverter circuit 5 ₁ is to the input terminal 8 ₂ via the input end of the pre-driver circuit 5 and the output is NOR.
The NAND gate 5 ₂ has its first input connected to the input terminal 8 ₁ via the input end of the predriver circuit 5 and its second input connected to the second input of the gate 5 ₃ and the predriver circuit 5 respectively.
Is connected to the input terminal 8 ₂ via the input terminals of
The first input of the OR gate 5 ₃ is connected to the input terminal 8 ₁ via the input end of the pre-driver circuit 5.

The operation of the present embodiment having the above-described structure is the same as the operation of the first embodiment, and the effect obtained by the operation is also the same as the effect obtained in the first embodiment. Therefore, detailed description thereof will be omitted.

In this embodiment, like the first embodiment, the second pull-down circuit 4 may be omitted, and the first pull-down circuit 3 to the first NMOS may be omitted.
The transistor 3 ₁ may be omitted.

Next, FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the semiconductor logic circuit according to the present invention, wherein the first and second pull-down circuits 3, 4 and 1 of the first embodiment are shown. 6 shows another example of a detailed circuit in the pre-driver circuit 5.

In FIG. 3, reference numeral 3 ₃ is a first NMOS transistor, 5 ₄ is an inverter circuit, 8 ₃ is an input terminal, and other components are the same as those shown in FIGS. 1 and 2. It is marked.

Then, the first pull-down circuit 3 has a first
Of NMOS transistor 3 ₃ , the pre-driver circuit 5 is composed of an inverter circuit 5 ₄ , and the second pull-down circuit 4 has the same configuration as that of the second embodiment. In the first NMOS transistor 3 ₃ , the drain D is connected to the output terminal 7, the gate G is connected to the output of the inverter circuit 5 ₄ , and the source S is connected to the reference potential point. The input of the inverter circuit 5 ₄ is a pre-driver circuit. It is connected to the input terminal 8 ₃ via the input terminal of 5.

The operation of this embodiment having the above-mentioned structure is as follows.

When the input signal Sin of logic 1 is input to the input terminal 8 ₃ , the inverter circuit 5 of the pre-driver circuit 5
Reference numeral ₄ inverts the input signal Sin to generate a logic signal of logic 0 at the output terminal of the pre-driver circuit 5. This logic 0 logic signal turns on the PMOS transistor 1,
At the same time, the first NMOS transistor 3 ₃ of the first pull-down circuit ₃ and the third NM of the second pull-down circuit 4
Both the OS transistors 4 ₁ are turned off. At this time, a current path from the power supply terminal 6 to the output terminal 7 through the PMOS transistor 1 and the Schottky barrier diode 2 is formed, and a signal of logic 1 is generated at the output terminal 7. Next, the input signal Sin supplied to the input terminal 8 ₃
There becomes a logic 0, the inverter circuit ₄ of the pre-driver circuit 5, similarly to generate a logic signal of logic 1 to the output terminal of the pre-driver circuit 5 inverts the input signal Sin. The logic signal of this logic 1 is the PMOS transistor 1
Is turned off, and at the same time, the first NMOS transistor 3 ₃ and the second pull-down circuit 4 of the first pull-down circuit 3 are turned on.
To turn the third NMOS transistors 4 ₁ of both. At this time, a current path from the output terminal 7 to the reference potential point is formed through the first NMOS transistor 3 ₃ , and a signal of logic 0 is generated at the output terminal 7.

In this operation, also in this embodiment, the Schottky barrier diode 2 is connected between the drain D of the PMOS transistor 1 and the output terminal 7 in this embodiment as in the first and second embodiments. Therefore, even if a voltage higher than the voltage value V of the power supply terminal 6 is applied to the output terminal 7, the high voltage is blocked by the reverse transmission characteristic of the Schottky barrier diode 2 and the high voltage is applied to the PMOS transistor 1. Therefore, the undesired transistor current It and the diode current Id do not flow in the PMOS transistor 1 due to the high voltage.

In this embodiment as well, the second pull-down circuit 4 can be appropriately omitted, as in the first and second embodiments.

The second and third embodiments are the same as the first embodiment.
Although preferable circuit examples are shown for each of the pull-down circuit 3, the second pull-down circuit 4, and the pre-driver circuit 5, the present invention is not limited to those circuit examples, and those Needless to say, it can be appropriately changed within a range that does not impair the functions of the circuits 3 to 5.

Next, FIG. 4 is a sectional view showing an example of the case where the circuit of the second embodiment is formed in a semiconductor device. In particular, the PMOS transistor 1, the Schottky barrier diode 2, It shows a configuration arrangement portion of the first NMOS transistor 3 ₁ .

In FIG. 4, 80 is a P-type semiconductor substrate, and 8
1 is a first N-type well region, 82 is a second N-type well region, 83 is a first P + (P-type high impurity concentration) diffusion region,
84 is a first N + (N-type high impurity concentration) diffusion region, 85
Is a second P + diffusion region, 86 is a third P + diffusion region, 8
7, 92 are gate oxide films, 88, 93 are gate electrodes, 8
9 is the second N + diffusion region, 90 is the third N + diffusion region,
Reference numeral 91 is a fourth N + diffusion region, 94 is a bonding portion, 95 is a connection wiring, and the same components as those shown in FIG. 2 are denoted by the same reference numerals.

Then, on one surface of the P-type semiconductor substrate 80, the first N-type well region 81, the second N-type well region 82, the third N + diffusion region 90, and the fourth N + diffusion region 91 are formed. , The first P + diffusion regions 83 are formed and arranged in this order. The exposed surface of the first N-type well region 81 has a first
N + diffusion region 84, second P + diffusion region 85, third P + diffusion region 86, gate oxide film 87 and gate electrode 8 of
8 are arranged to form the PMOS transistor 1. Here, the second P + diffusion region 85 and the third P + diffusion region 86 configure the source S and the drain D, respectively, and the gate oxide film 87 and the gate electrode 88 configure the gate G. A second N + diffusion region 89 is arranged and formed on the exposed surface of the second N-type well region 82, and the Schottky barrier diode 2 is formed at the junction 94 between the connection wiring 95 and the second N-type well region 82. Composed. Where the joint 9
4 and the second N-type well region 82 constitute an anode and a cathode, respectively. Third N + diffusion region 90, fourth
Of the N + diffusion region 91, the gate oxide film 92 and the gate electrode 93 of the first NMOS transistor 3 ₁
Is configured. Here, the third N + diffusion region 90, the fourth
N + diffusion region 91 constitutes a drain D and a source S,
The gate oxide film 92 and the gate electrode 93 form the gate G.

The P-type semiconductor substrate 80 is set to the reference potential through the P + diffusion region 83, and the first N-type well region 81 is set to the power supply voltage V through the first N + diffusion region 84. Second P + diffusion region 85 and gate electrode 9
3 is connected to the power supply terminal 6, and the third P + diffusion region 86 is connected to the Schottky barrier diode 2 through the connection wiring 95.
Connected to. The second N + diffusion region 89 and the third N +
The diffusion region 90 is connected to the output terminal 7, and the gate electrode 88
Is connected to the output terminal of the pre-driver circuit 5 not shown.

Generally, a PMO forming a pull-up circuit
When an output buffer circuit composed of an S transistor and an NMOS transistor forming a pull-down circuit is formed by a semiconductor device, the PMOS transistor and the NMOS transistor are arranged on the surface of the semiconductor device by about 100 μm in order to prevent destruction due to latch-up. It is usual to arrange them with a space therebetween, and the space portion in the semiconductor device is a dead space which is not used at all.

According to the present invention, when the second embodiment is constituted by a semiconductor device, the PMO formed on one surface of the semiconductor device.
A Schottky barrier diode 2 is newly arranged and arranged in the space between the S transistor 1 and the third NMOS transistor 3 ₁ .

Therefore, the dead space of the semiconductor device is effectively utilized, and a semiconductor device having a high arrangement density can be realized.

Next, FIG. 5 is a circuit diagram showing the configuration of the first embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention, in which a composite high density integrated circuit (LSI) is constructed. Here is an example.

In FIG. 5, 10 is a first semiconductor logic circuit, 11 is a first PMOS transistor, 12 is a Schottky barrier diode, 13 is a first pull-down circuit having one end, the other end, and a control end, and 14 is A second pull-down circuit having one end, the other end, and a control end, 14 ₁ is a first NM
OS transistor, 15 is a first having an input end and an output end
Pre-driver circuit, 16 is a power supply terminal for supplying a voltage value V1, 17 is an output terminal, 18 is a coupled bus, 20 is a second semiconductor logic circuit, 21 is a second PMOS transistor,
22 is a second NMOS transistor, 23 is a second pre-driver circuit having an input end and an output end, and 24 is a voltage value V
A power supply terminal that supplies a voltage value V2 higher than 1 and 25 is an output terminal.

The first semiconductor logic circuit 10 and the second semiconductor logic circuit 20 are separately configured by LSI, and both output terminals 17 and 25 are connected to the coupling bus 18. The first semiconductor logic circuit 10 has almost the same configuration as that of the second embodiment of the semiconductor logic circuit, and the second semiconductor logic circuit 20 has the known first coupling configuration example. Since it has almost the same configuration as the second semiconductor logic circuit 110 in FIG.
The detailed description of the connection configuration regarding the 0 and second semiconductor logic circuits 20 is omitted.

The independent operation of the first semiconductor logic circuit 10 is almost the same as the operation of the second embodiment in the semiconductor logic circuit, and the independent operation of the second semiconductor logic circuit 20 is the same. , Second in the known first coupling configuration example
Since the operation is almost the same as that of the semiconductor logic circuit 110, the description of the operation of each of the first semiconductor logic circuit 10 and the second semiconductor logic circuit 20 is omitted.

By the way, in this embodiment, the voltage value V1
First semiconductor logic circuit 1 having power supply terminal 16 for supplying
0 is a rest state, that is, the first PMOS transistor 11
And the first pull-down circuit 13 are both off and the output terminal 17 is in the high impedance state, the second semiconductor logic circuit 20 having the power supply terminal 24 supplying the voltage value V2 higher than the voltage value V1 is It is assumed that a signal of logic 1 (voltage value V2) is derived from the output terminal 25 to the combined bus 18. At this time, a high voltage having a voltage value V2 based on the signal of logic 1 is applied to the output terminal 17 of the first semiconductor logic circuit 10. However, the first semiconductor logic circuit 10 has the first PMOS. Since the Schottky barrier diode 12 is connected between the drain D of the transistor 11 and the output terminal 17, this high voltage is completely blocked by the reverse transfer characteristic of the Schottky barrier diode 12, and the first PMOS It is not transmitted to the transistor 11 or the power supply terminal 16.

As described above, according to this embodiment, the first and second semiconductor logic circuits 1 having the power supplies having different voltage values are provided.
Even if the output terminals 17 and 25 of 0 and 20 are commonly connected to the coupling bus 18, the unnecessary current flowing through the first semiconductor logic circuit 10 in the idle state increases and the second semiconductor logic circuit in the operating state increases. The increase in power consumption of the circuit 20 is effectively suppressed, and the first semiconductor logic circuit 10 is in a dormant state.
It is possible to prevent the occurrence of failure destruction due to the latch-up of.

Although the present embodiment shows an example in which the second pull-down circuit 14 is used in the first semiconductor logic circuit 10, the second pull-down circuit 14 has a desired operation characteristic. As described above, it can be appropriately omitted.

Next, FIG. 6 is a circuit diagram showing the configuration of the second embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention, in which a composite high density integrated circuit (LSI) is also constructed. It is an example.

In FIG. 6, 30 is a third semiconductor logic circuit, 31 is a second PMOS transistor, 32 is a second NMOS transistor, 33 is a pull-up resistor, and 34 is a resistor.
Is a power supply terminal for supplying a voltage value V2 higher than the voltage value V1,
35 is an input terminal, 36 is an output terminal,
The same components as the components shown in FIG.

Also in the present embodiment, the first semiconductor logic circuit 10 and the third semiconductor logic circuit 30 are separately configured by the LSI, and the first semiconductor logic circuit 1
The output terminal 17 of 0 and the input terminal 35 of the third semiconductor logic circuit 30 are both connected to the combined bus 18. In addition,
The first semiconductor logic circuit 10 has almost the same structure as that of the second embodiment of the semiconductor logic circuit, and the third semiconductor logic circuit 30 has the same structure as that of the known second coupling structure example. Three
Since it has almost the same configuration as the semiconductor logic circuit 120, the detailed description of the connection configuration regarding the first semiconductor logic circuit 10 and the third semiconductor logic circuit 30 will be omitted.

The independent operation of the first semiconductor logic circuit 10 is almost the same as the operation of the second embodiment of the semiconductor logic circuit, and the independent operation of the third semiconductor logic circuit 30 is the same. Since the operation is almost the same as the operation of the third semiconductor logic circuit 120 of the known second coupling configuration example, the explanation of the operation of each of the first semiconductor logic circuit 10 and the third semiconductor logic circuit 30 is independent. Is omitted.

By the way, in this embodiment, the first PMOS transistor 11 of the first semiconductor logic circuit 10 is turned on, the first pull-down circuit 13 and the second pull-down circuit 14 are both turned off, and the first semiconductor transistor 10 is turned off. Semiconductor logic circuit 1
0 is a logic 1 to the coupled bus 18 via its output terminal 17.
It is assumed that the signal (voltage value V1) is derived. At this time, the pull-up resistor 3 is pulled from the third semiconductor logic circuit 30.
3 through the output terminal 17 of the first semiconductor logic circuit 10.
The voltage of the voltage value V2 higher than the power supply voltage value V1 is applied to the first semiconductor logic circuit 10.
Since the Schottky barrier diode 12 is connected between the drain D of the first PMOS transistor 11 and the output terminal 17, this high voltage is completely blocked by the reverse transfer characteristic of the Schottky barrier diode 12, The current is not transmitted to the first PMOS transistor 11 and the power supply terminal 16, and the current flowing through the pull-up resistor 33 is reduced.

As described above, according to this embodiment, the output terminal 17 of the first semiconductor logic circuit 10 and the input terminal 25 of the third semiconductor logic circuit 30 having the power supplies having different voltage values are connected to the coupling bus 18. Even if they are commonly connected to each other, increase in unnecessary current flowing through the first semiconductor logic circuit 10 in the operating state and increase in power consumption of the third semiconductor logic circuit 30 are effectively suppressed, and the operating state is It is possible to prevent the occurrence of failure destruction due to latch-up of the first semiconductor logic circuit 10 in FIG.

Next, FIG. 7 is a circuit diagram showing the configuration of the third embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention, and a composite high density integrated circuit (LSI) is also constructed. Here is an example.

In FIG. 7, 13 ₁ is a first NMOS transistor, 15 ₁ is an inverter circuit, and the same components as those shown in FIGS. 3 and 6 are denoted by the same reference numerals. .

Also in the present embodiment, the first semiconductor logic circuit 10 and the third semiconductor logic circuit 30 are separately configured by LSI, and the first semiconductor logic circuit 1
The output terminal 17 of 0 and the input terminal 35 of the third semiconductor logic circuit 30 are commonly connected to the coupling bus 18. The first semiconductor logic circuit 10 corresponds to the third semiconductor logic circuit
The configuration of the third semiconductor logic circuit 30 is almost the same as that of the third embodiment, and the configuration of the third semiconductor logic circuit 30 is almost the same as that of the third semiconductor logic circuit 120 in the known second coupling configuration example. Therefore, detailed description of the connection configuration regarding the first semiconductor logic circuit 10 and the third semiconductor logic circuit 30 is omitted.

The independent operation of the first semiconductor logic circuit 10 is almost the same as the operation of the third embodiment of the semiconductor logic circuit, and the independent operation of the third semiconductor logic circuit 30 is the same. Since the operation is almost the same as that of the third semiconductor logic circuit 120 in the known second coupling configuration example, the first
The description of the individual operations of the semiconductor logic circuit 10 and the third semiconductor logic circuit 30 will be omitted.

By the way, in the present embodiment, the first PMOS transistor 11 of the first semiconductor logic circuit 10 is turned on, both the first pull-down circuit 13 and the second pull-down circuit 14 are turned off, and the first semiconductor transistor 10 is turned off. Semiconductor logic circuit 1
0 is a logic 1 to the coupled bus 18 via its output terminal 17.
It is assumed that the signal (voltage value V1) is derived. Also at this time, the pull-up resistor 3 is pulled from the third semiconductor logic circuit 30.
3 through the output terminal 17 of the first semiconductor logic circuit 10.
The voltage of the voltage value V2 higher than the power supply voltage value V1 is applied to the first semiconductor logic circuit 10.
Since the Schottky barrier diode 12 is connected between the drain D of the first PMOS transistor 11 and the output terminal 17, this high voltage is completely blocked by the reverse transfer characteristic of the Schottky barrier diode 12, The current is not transmitted to the first PMOS transistor 11 and the power supply terminal 16, and the current flowing through the pull-up resistor 33 is reduced.

As described above, according to this embodiment, the output terminal 17 of the first semiconductor logic circuit 10 and the input terminal 25 of the third semiconductor logic circuit 30 having the power supplies having different voltage values are connected to the coupling bus 18. Even if they are commonly connected to each other, increase in unnecessary current flowing through the first semiconductor logic circuit 10 in the operating state and increase in power consumption of the third semiconductor logic circuit 30 are effectively suppressed, and the operating state is It is possible to prevent the occurrence of failure destruction due to latch-up of the first semiconductor logic circuit 10 in FIG.

Next, FIG. 8 is a circuit diagram showing the structure of a fourth embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention, in which the output terminals of a plurality of semiconductor logic circuits are common to the coupling bus. This is an example of being connected.

In FIG. 8, 19 is an inverter circuit and 4
0 is a fourth semiconductor logic circuit, 41 is a second PMOS transistor, 42 is a second Schottky barrier diode, 43 is a third pull-down circuit, 44 is a fourth pull-down circuit, and 44 ₁ is a second NMOS. Transistor, 45
Is a second pre-driver circuit, 46 is a power supply terminal, 47 is an output terminal, and other components that are the same as those shown in FIG. Although not shown in FIG. 8, a plurality of similar semiconductor logic circuits are arranged between the first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 40.

The first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 40, and the plurality of semiconductor logic circuits not shown in the figure, have substantially the same configuration and their outputs. Terminals 17 and 47 are combined bus 18
Commonly connected to. The coupling bus 18 is the inverter circuit 1
It is also connected to the input terminal of 9. The first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 40, and the plurality of semiconductor logic circuits not shown in the figure are all substantially the same as those in the second embodiment of the semiconductor logic circuit. Since it has the configuration, the detailed description of the connection configuration regarding the first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 40, and a plurality of semiconductor logic circuits not shown in the figure is omitted.

Further, the first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 10
The operation of each of the semiconductor logic circuit 40 and the plurality of semiconductor logic circuits not shown in the figure is almost the same as the operation of the second embodiment of the semiconductor logic circuit. The description of each single operation in the first semiconductor logic circuit 10, the fourth semiconductor logic circuit 40, and the plurality of semiconductor logic circuits not shown in the figure is omitted.

By the way, in this embodiment, when one semiconductor logic circuit outputs a signal to the combined bus 18, for example, when the first semiconductor logic circuit 10 outputs a logic 1 signal, another semiconductor logic circuit. That is, the output terminals 47 of the fourth semiconductor logic circuit 40 and a plurality of semiconductor logic circuits (not shown) are set to the high impedance state. In this high impedance state, in the fourth semiconductor logic circuit 40, the second NMOS transistor 44 ₁ is turned on and the anode of the second Schottky barrier diode 42 is lowered to the reference potential. The second Schottky barrier diode 42 is off, and a plurality of semiconductor logic circuits (not shown) are in the same operating state.

As described above, according to the present embodiment, the capacitive load viewed from the coupling bus 18 side is only the cathode side loads of the second Schottky barrier diode 42 and the other Schottky barrier diodes. Since the load on the anode side is irrelevant, the load on the coupling bus 18 is significantly reduced, and as a result, each semiconductor logic circuit 10, 40 can be operated at a higher speed and each semiconductor logic circuit 10, 40 can be operated. Power consumption during the operation of can be reduced. Further, similarly to each of the above-described embodiments, an increase in unnecessary current flowing through the fourth semiconductor logic circuit 40 in the idle state and a plurality of semiconductor logic circuits not shown is effectively suppressed, and It is possible to prevent occurrence of failure destruction due to latch-up of the first semiconductor logic circuit 10 in the operating state.

Next, FIG. 9 is a circuit diagram showing the configuration of the fifth embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention, in which a composite high density integrated circuit (LSI) is also constructed. It is an example.

In FIG. 9, 50 is a fifth semiconductor logic circuit, 51 is a second PMOS transistor, 52 is a second Schottky barrier diode, 53 is a third pull-down circuit, 54 is a fourth pull-down circuit, 54 ₁ is a second NMOS transistor, 55 is a second pre-driver circuit, 56 is a power supply terminal to which a voltage of V2 is supplied, 5
7 is an output terminal, 60 is a sixth semiconductor logic circuit, 61 is a third PMOS transistor, 62 is a third Schottky barrier diode, 63 is a fifth pull-down circuit, and 64.
5 is a sixth pull-down circuit, 64 ₁ is a third NMOS transistor, 65 is a third pre-driver circuit, 66 is a power supply terminal to which the voltage of the voltage value V3 is supplied, 67 is an output terminal, The same components as the components shown in FIG. Although not shown in FIG. 9, a plurality of similar semiconductor logic circuits are arranged between the fifth semiconductor logic circuit 50 and the sixth semiconductor logic circuit 60.

Then, the first semiconductor logic circuit 10, the fifth
The semiconductor logic circuit 50, the sixth semiconductor logic circuit 60, and the plurality of semiconductor logic circuits not shown in the drawing are
Both are composed of separate LSIs and have substantially the same structure, and their output terminals 17, 57, 6
7 are commonly connected to a combined bus 18. The first semiconductor logic circuit 10, the fifth semiconductor logic circuit 40, the sixth semiconductor logic circuit 60, and a plurality of semiconductor logic circuits not shown in the drawing are supplied to the power supply terminals 16, 56, 66. The first semiconductor logic circuit 10 and the fifth semiconductor logic circuit have almost the same configuration as that of the second embodiment of the semiconductor logic circuit except for the different voltage values. 50, the sixth semiconductor logic circuit 60, and the detailed description of the connection configuration relating to a plurality of semiconductor logic circuits not shown in the figure are omitted.

Further, each of the individual operations of the first semiconductor logic circuit 10, the fifth semiconductor logic circuit 50, the sixth semiconductor logic circuit 60, and a plurality of semiconductor logic circuits not shown therein is Since the operation of the semiconductor logic circuit is almost the same as that of the second embodiment, the first semiconductor logic circuit 10 and the fourth semiconductor logic circuit 40, and a plurality of semiconductor logic circuits not shown in the figure. A description of each individual operation in the circuit is omitted.

Generally, in an output coupling circuit having a configuration in which the output terminals of a plurality of semiconductor logic circuits having different power supply voltage values are commonly connected to a coupling bus,
Some current paths may be formed between the respective power supplies, making it impossible to raise the power supply voltage or destroying other semiconductor logic circuits. Therefore, in a known output coupling circuit of this type of semiconductor logic circuit, a power supply sequence control circuit is separately arranged externally, and the power supply sequence (power supply voltage of the plurality of semiconductor logic circuits is controlled by the control operation of the power supply sequence control circuit). The order of startup and shutdown was carefully controlled.

However, in the present embodiment, the voltage value V for each power source of the first semiconductor logic circuit 10, the fifth semiconductor logic circuit 50, and the sixth semiconductor logic circuit 60.
1, V2, V3 are, for example, V1 is 5V, V2 is 3V,
Even if V3 is different, such as 2.5V, the first semiconductor logic circuit 10 has the first Schottky barrier diode 12 connected between the first PMOS transistor 11 and the output terminal 17. In addition, since the other semiconductor logic circuits 50 and 60 have the same configuration, the conductive path between the output terminals 17, 57 and 67 is unidirectional, and the semiconductor logic circuits 10 and 50, 60
Become irrelevant to their power sequence.

As described above, according to this embodiment, it is not necessary to use the power supply sequence control circuit required in the known output coupling circuit of this type of semiconductor logic circuit, and at the same time, the same as in the above-described embodiments. In addition, the increase in unnecessary current flowing through each semiconductor logic circuit in the idle state is effectively suppressed,
Moreover, it is possible to prevent occurrence of failure destruction due to latch-up of one semiconductor logic circuit in the operating state.

Next, FIG. 10 is a circuit diagram showing the configuration of an embodiment of a semiconductor logic switching circuit according to the present invention, and shows an example of switching-driving a reactive load device.

In FIG. 10, 70 is a semiconductor switching circuit, 71 is a PMOS transistor, 72 is a Schottky barrier diode, 73 is a pre-driver circuit, and 73.
₁ is an inverter circuit, 74 is a power supply terminal for supplying a voltage value V1, 75 is an output terminal, 76 is an input terminal, 77 is a load device, 78 is an inductive load, and 79 is a voltage value V2 smaller than the voltage value V1. It is a power supply terminal.

In the semiconductor switching circuit 70, the PMOS transistor 71 has a source S and a base B.
To the common power supply terminal 74, the output end of the gate G is the pre-driver circuit 73, i.e., the output terminal of the inverter circuit 73 _1, the drain D is connected to the anode of the Schottky barrier diode 72. The cathode of the Schottky barrier diode 72 is connected to the output terminal 75,
The inverter circuit 73 of the _input terminals of the pre-driver circuit 73 is connected to the input terminal 76. In the load device 77, the inductive load 78 has one end connected to the output terminal 75 and the other end connected to the power supply terminal 79.

The present embodiment having the above-mentioned configuration operates as follows.

The input signal Sin supplied to the input terminal 76
Is inverted by the inverter circuit 73 ₁ of the pre-driver circuit 73 is applied to the gate G of the PMOS transistor 71, the PMOS transistor 71 on, to control off switching. When the PMOS transistor 71 is switched from the ON state to the OFF state, the counter electromotive force generated by the inductive load 78 is applied to the cathode of the Schottky barrier diode 72 through the output terminal 75. Even if the voltage is higher than the value V1, the voltage is effectively blocked by the reverse transfer characteristic of the Schottky barrier diode 72 and is not transferred to the PMOS transistor 71 or the power supply terminal 74.
Further, even if the voltage value V2 supplied to the power supply terminal 79 becomes higher than the voltage value V1 for some reason, the high voltage similarly causes the Schottky barrier diode 7 to operate.
2, which is effectively blocked by the reverse transmission characteristic,
It is not transmitted to the S transistor 71 or the power supply terminal 74.

As described above, according to this embodiment, when connecting the semiconductor logic switching circuit 70 and the reactive load device 77, the value of the transient voltage generated by the reactive load device 77 is considered. Not only is it unnecessary to obtain a semiconductor logic switching circuit that is extremely versatile, but it is possible to prevent the occurrence of failure destruction due to latch-up of the semiconductor switching circuit 70 during operation.

[0095]

As described above, according to the semiconductor logic circuit of the present invention, between the drain of the PMOS transistor and the output terminal, the Schottky is oriented so as to block the current flowing from the output terminal to the PMOS transistor. Since the barrier diode is connected, even if a voltage higher than the voltage value of the power supply is applied to the output terminal, the high voltage is electrically isolated by the Schottky barrier diode, and unnecessary current is supplied to the PMOS transistor. There is an effect that an extremely versatile semiconductor logic circuit can be obtained when a common connection is made with other semiconductor logic circuits without causing the current to flow or causing an unnecessary current to flow backward to the power supply.

Further, according to the output coupling circuit of the semiconductor logic circuit of the present invention, the Schottky barrier diode is provided between the drain of the PMOS transistor and the output terminal in the direction of blocking the current flowing from the output terminal to the PMOS transistor. Since the first semiconductor logic circuit connected to the first semiconductor logic circuit is used, even if a voltage higher than the voltage value of the power supply is applied to the output terminal of the first semiconductor logic circuit from another semiconductor logic circuit, the high voltage Is electrically isolated by the Schottky barrier diode,
It is possible to prevent unnecessary current from flowing through the transistor. Then, when the first semiconductor logic circuit is connected to another semiconductor logic circuit having a power supply voltage different from the voltage value of the power supply, increase in power consumption of the other semiconductor logic circuit is suppressed, and the first semiconductor logic circuit is suppressed. With respect to the PMOS transistor of the semiconductor logic circuit, there is an effect that failure destruction due to the latch-up can be prevented.

Further, according to the semiconductor switching circuit of the present invention, a Schottky barrier diode is connected between the drain of the PMOS transistor and the output terminal so as to block the current flowing from the output terminal to the PMOS transistor. Therefore, even if the reactive load device connected to the output terminal transiently generates a voltage higher than the voltage value of the power source of the semiconductor switching circuit, the high voltage is electrically generated by the Schottky barrier diode. And is prevented from flowing an unnecessary current to the PMOS transistor or backflowing an unnecessary current to the power supply. When the semiconductor switching circuit and the reactive load device are connected to each other, Eliminates the need to consider transient voltage values generated by the load , There is an effect that the semiconductor switching circuit rich in very versatility is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor logic circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of a semiconductor logic circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third embodiment of a semiconductor logic circuit according to the present invention.

FIG. 4 is a sectional configuration diagram showing an example of a case where the circuit of the second embodiment shown in FIG. 2 is formed in a semiconductor device.

FIG. 5 is a circuit diagram showing a configuration of a first embodiment of an output coupling circuit of a semiconductor logic circuit according to the present invention.

FIG. 6 is a circuit diagram showing a configuration of a second embodiment of an output coupling circuit of a semiconductor logic circuit according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of a third embodiment of an output coupling circuit of a semiconductor logic circuit according to the present invention.

FIG. 8 is a circuit diagram showing a configuration of a fourth embodiment of an output coupling circuit of a semiconductor logic circuit according to the present invention.

FIG. 9 is a circuit diagram showing a configuration of a fifth embodiment of the output coupling circuit of the semiconductor logic circuit according to the present invention.

FIG. 10 is a circuit diagram showing a configuration of an embodiment of a semiconductor logic switching circuit according to the present invention.

FIG. 11 is a circuit diagram showing a first configuration example when two semiconductor logic circuits are connected by a known means.

FIG. 12 is a circuit diagram showing a second configuration example when two semiconductor logic circuits are connected by a known means.

[Explanation of symbols]

1, 71 PMOS transistor 2, 72 Schottky barrier diode 3 First pull-down circuit 3 ₁ , 13 ₁ , 14 ₁ First NMOS transistor 3 ₂ , 22, 32, 44 ₁ , 54 ₁ Second NMOS transistor 3 ₃ Fourth NMOS transistor 4 Second pull-down circuit 4 ₁ , 64 ₁ Third NMOS transistor 5, 73 Pre-driver circuit 5 ₁ , 15 ₁ , 19, 73 ₁ Inverter circuit 5 ₂ NAND gate 5 ₃ NOR gate 5 _4th 2 inverter circuits 6, 16, 24, 34, 46, 56, 66, 74, 79
Power supply terminal 7, 17, 25, 36, 47, 57, 67, 75 Output terminal 8 ₁ , 8 ₂ , 8 ₃ , 35, 76 Input terminal 10 First semiconductor logic circuit 11 First PMOS transistor 12 First Schottky barrier diode 13, 43, 53 Third pull-down circuit 14, 44, 54 Fourth pull-down circuit 15 First pre-driver circuit 18 Combined bus 20 Second semiconductor logic circuit 21, 31, 41, 51 Second PMOS transistor 23, 45, 55 second pre-driver circuit 30 third semiconductor logic circuit 33 pull-up resistor 40 fourth semiconductor logic circuit 42, 52 second Schottky barrier diode 50 fifth semiconductor logic circuit 60 6th semiconductor logic circuit 61 3rd PMOS transistor 62 3rd Schottky barrier diode 6 Fifth pull-down circuit 64 Sixth pull-down circuit 65 Third pre-driver circuit 70 Semiconductor logic switching circuit 77 Load device 78 Inductive load 79 Power supply terminal 80 P-type semiconductor substrate 81 First N-type well region 82 Second N-type well region 83 First P + diffusion region 84 First N + diffusion region 85 Second P + diffusion region 86 Third P + diffusion region 87, 92 Gate oxide film 88, 93 Gate electrode 89 Second N + diffusion region 90 Third N + Diffusion Region 91 Fourth N + Diffusion Region 94 Junction 95 Connection Wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/08 C 9184-5J 19/0175

Claims (20)

[Claims] 1. A PMOS transistor having a source and a substrate commonly connected to a power supply, a Schottky barrier diode having an anode connected to the drain of the PMOS transistor and a cathode connected to an output terminal, and one end, the other end, and a control end. A first pull-down circuit having one end connected to the output terminal and the other end connected to a reference potential point, and an input end and an output end, the output end being the gate of the PMOS transistor and the first pull-down circuit. A pre-driver circuit connected to each control terminal of the circuit, and in response to a control signal supplied to an input terminal of the pre-driver circuit, the PMOS
A semiconductor logic circuit characterized in that a transistor and the first pull-down circuit are turned on and off. 2. One end, the other end, and a control end are provided between the drain of the PMOS transistor and the reference potential point,
2. A second pull-down circuit having one end connected to the drain of the PMOS transistor, the other end connected to the reference potential point, and the control end connected to the output end of the pre-driver circuit. Semiconductor logic circuit. 3. The first pull-down circuit and the second pull-down circuit are each configured by a circuit including at least one NMOS transistor. Semiconductor logic circuit. 4. The pre-driver circuit has two input terminals and two to three output terminals, and in response to a control signal supplied to the two input terminals, the pre-driver circuit tries the output terminals. The state is set to a state state.
4. The semiconductor logic circuit according to any one of 3 to 3. 5. The pre-driver circuit has one input terminal and one output terminal, and sets the output terminal in a push-pull buffer state in response to a control signal supplied to the one input terminal. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is set to. 6. A first semiconductor logic circuit operating with a first power supply, and a second power supply connected to an output terminal of the first semiconductor logic circuit and having a voltage value different from that of the first power supply. An output coupling circuit of a semiconductor logic circuit including a second semiconductor logic circuit operating in the first semiconductor logic circuit, wherein the first semiconductor logic circuit has a first PMOS transistor whose source and base are commonly connected to the first power supply. A Schottky barrier diode having an anode connected to the drain of the first PMOS transistor and a cathode connected to the output terminal, and one end, the other end, and a control end. One end is the output terminal and the other end is the reference. A first pull-down circuit connected to the potential point, an input end and an output end, and an output end connected to the gate of the first PMOS transistor and each control end of the first pull-down circuit. And a first pre-driver circuit for controlling on / off of the first PMOS transistor and the first pull-down circuit in response to a control signal supplied to an input terminal of the first pre-driver circuit. An output coupling circuit of a semiconductor logic circuit, characterized in that 7. A first end, a second end, and a control end are provided between the drain of the first PMOS transistor and the reference potential point, and one end is the drain of the first PMOS transistor and the other end is the 7. The semiconductor logic circuit according to claim 6, wherein the control terminal is connected to a second pull-down circuit whose control terminal is connected to the output terminal of the first pre-driver circuit. 8. The output coupling of a semiconductor logic circuit according to claim 7, wherein each of the first pull-down circuit and the second pull-down circuit is composed of a circuit including at least one NMOS transistor. circuit. 9. The first pre-driver circuit has two input terminals and two to three output terminals, and is responsive to a control signal supplied to the two input terminals to output the first pre-driver circuit. 9. The output coupling circuit of the semiconductor logic circuit according to claim 6, wherein the output terminal of the first semiconductor logic circuit is set in a tri-state state. 10. The first pre-driver circuit has one input end and one output end, and is responsive to a control signal supplied to the one input end, to the first semiconductor. 9. The output coupling circuit of a semiconductor logic circuit according to claim 6, wherein the output terminal of the logic circuit is set in a push-pull buffer state. 11. In the second semiconductor logic circuit, a source and a base are connected to the second power supply, a drain is connected to an output terminal, and a second PMOS transistor is connected, and a drain is the drain of the second PMOS transistor. And a third NMOS transistor whose source is connected to the reference potential point,
An input end and an output end, the output end being the second PM
An OS transistor and a second pre-driver circuit connected to each gate of the third NMOS transistor, and the second pre-driver circuit is responsive to a control signal supplied to an input terminal of the second pre-driver circuit. 11. The PMOS transistor and the third NMOS transistor are controlled to be turned on and off, and the output circuit is connected to an output terminal of the first semiconductor logic circuit. An output coupling circuit of any one of the semiconductor logic circuits. 12. In the second semiconductor logic circuit, a source and a substrate are connected to the second power source, a drain is connected to an output terminal, and a third PMOS transistor is connected, and a drain is the drain of the third PMOS transistor. And a fourth NMOS transistor whose source is connected to the reference potential point,
The third PMOS transistor and the fourth NMOS
An input terminal connected to each gate of the transistor and a pull-up impedance connected between the second power source and the input terminal, and the third terminal is responsive to a control signal supplied to the input terminal. 11. The PMOS transistor and the fourth NMOS transistor are controlled to be turned on and off, and the input terminal is connected to an output terminal of the first semiconductor logic circuit. An output coupling circuit of any one of the semiconductor logic circuits. 13. The output coupling circuit of the semiconductor logic circuit according to claim 6, wherein a common coupling bus is connected to an output terminal of the first semiconductor logic circuit. 14. The second semiconductor logic circuit is composed of a plurality of different semiconductor logic circuits having the same configuration, and in each of the different semiconductor logic circuits, a source and a base are commonly connected to a power supply. And a second Schottky barrier diode whose anode is connected to the drain of the fourth PMOS transistor and whose cathode is connected to the output terminal, and which has one end, the other end, and a control end, one end of which is the output terminal Has a fifth pull-down circuit having the other end connected to the reference potential point, an input end and an output end, and the output end is the fourth P
A third pre-driver circuit connected to the gate of the MOS transistor and each control terminal of the fifth pull-down circuit, and responsive to a control signal supplied to the input terminal of the third pre-driver circuit, The fourth PMOS transistor and the fifth pull-down circuit are controlled to be turned on and off, and the output terminals of the respective semiconductor logic circuits are commonly connected to the output terminal of the first semiconductor logic circuit. 14. The output coupling circuit of a semiconductor logic circuit according to claim 6, wherein the output coupling circuit is a semiconductor logic circuit. 15. A first end, a second end, and a control end are provided between the drain of the fourth PMOS transistor and the reference potential point, one end of which is the drain of the fourth PMOS transistor and the other end of which is the control end. 15. The semiconductor logic circuit according to claim 14, wherein a sixth pull-down circuit having a control end connected to an output end of the third pre-driver circuit is connected to the reference potential point. 16. The power source of each of the different semiconductor logic circuits has a different voltage value, and the voltage values thereof are also different from the voltage value of the power source of the first semiconductor logic circuit. 16. An output coupling circuit for a semiconductor logic circuit according to claim 14, wherein the output coupling circuit is a semiconductor logic circuit. 17. The first semiconductor logic circuit and the second semiconductor logic circuit are each separately configured as a high density integrated circuit (LSI), and a composite LSI is formed as a whole. An output coupling circuit for a semiconductor logic circuit according to any one of claims 6 to 16. 18. A PMOS transistor whose source and substrate are commonly connected to a first power supply, and whose anode is said PM.
The drain of the OS transistor comprises a Schottky barrier diode having a cathode connected to the output terminal, and a pre-driver circuit having an input end and an output end, the output end of which is connected to the gate of the PMOS transistor. A reactive load device driven by a second power supply having a voltage value different from the voltage value of the first power supply is connected to the terminal, and in response to a control signal supplied to the input end of the pre-driver circuit, Turning on the PMOS transistor,
A semiconductor logic switching circuit, which is off-controlled to drive the load device by switching. 19. The voltage value of the second power source is the first voltage value.
19. The semiconductor logic switching circuit according to claim 18, wherein the voltage value is lower than the voltage value of the power supply. 20. At least the source and the base are common to each other.
Semiconductor logic including a PMOS transistor connected to the power supply, a Schottky barrier diode having an anode connected to the drain of the PMOS transistor, a cathode connected to the output terminal, and an NMOS transistor having a drain connected to the output terminal. A circuit is configured by a semiconductor device, wherein a first N-type region is arranged and arranged on a P-type semiconductor substrate to form the PMOS transistor therein, and the circuit is adjacent to the first N-type region. And forming a second N-type region different from the first N-type region in a space region between the first N-type region and the formation region of the NMOS transistor. A Schottky barrier diode is formed by arranging and forming and connecting a connection wiring to this second N-type region. Body logic circuit.