JPH07135304A - Compound semiconductor device, its fabrication and defect measuring method for compound semiconductor layer - Google Patents

Abstract

PURPOSE:To provide a compound semiconductor device, it fabrication, and defect measuring method for compound semiconductor layer in which a high quality Gaps layer can be formed on an InGaP/InGaAs based crystal laminate and the roughness of underlying InGaP layer and InGaAs layer can be measured by observing the GaAs layer. CONSTITUTION:An i-GaAs layer 2, an i-InGaAs layer 3, an n-InGaP layer, etc., having different lattice constants are grown on a GaAs substrate 1. A first n-GaAs layer 51 thinner than a target thickness is grown on the layer 4, and then it is annealed in arsenic atmosphere. Subsequently, a second n-GaAs layer 52 is grown up to a target thickness thus restraining the uppermost second n-GaAs layer 52 from being bored. The boring is restrained by employing an off-substrate having orientation inclining in (100) just direction or (111) A direction as the GaAs substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device such as a high speed electron mobility transistor, a method for manufacturing the same, and a method for measuring a defect in a compound semiconductor layer.

In recent years, various semiconductor devices formed by using compound semiconductor crystals (herein referred to as compound semiconductor devices) have been developed. When the compound semiconductor layers are stacked while paying attention to the energy gap in order to improve the electrical characteristics of these compound semiconductor devices, strain may occur in the stacked compound semiconductor layers due to the lattice mismatch.

Also, InG having a lattice mismatch with the GaAs substrate
Paying attention to the fact that the saturation rate of electrons in the aAs layer is high,
An InGaAs layer and an InGaP layer having different lattice constants may be stacked, and in this case, compressive strain and tensile strain occur in the GaAs layer and the InGaP layer. This phenomenon is widespread and occurs in photoelectric conversion devices such as semiconductor laser devices, semiconductor light emitting devices, and semiconductor light receiving devices that use compound semiconductors, or in compound semiconductor devices such as high-speed electron mobility transistors (HEMTs).

As a method for evaluating such a strained semiconductor layer, a photoluminescence (PL) method and a Hall effect (Hall Effect) method are used, but the evaluation is performed by several hundred nm or more on the strained semiconductor layer. It was performed after growing the compound semiconductor layer having the film thickness of. In these evaluation methods, the evaluation is performed by confining the carriers in the strained semiconductor layer to cause PL light emission, or by causing the carriers to travel in the strained semiconductor layer.

[0005]

2. Description of the Related Art FIG. 8 shows a conventional InGaP / InGaA.
It is a structural diagram of an s-based crystal laminate. In this figure, 21
Is a GaAs substrate, 22 is an i-GaAs layer, and 23 is an i-I.
nGaAs layer, 24 is n-InGaP layer, 25 is n-G
It is an aAs layer.

In this InGaP / InGaAs type crystal laminated body, i-GaAs is formed on the GaAs substrate 21.
Layer 22, i-InGaAs layer 23, n-InGaP layer 2
4. The n-GaAs layer 25 is sequentially grown.

InGaP / InGa using this laminated body
When forming an As-based HEMT, the i-GaAs layer 2
2 is a buffer layer, the i-InGaAs layer 23 is an electron transit layer, the n-InGaP layer 24 is thinner than 30 nm to be an electron supply layer, and the n-GaAs layer 25 is a cap layer thinner than 4 nm.

The n-GaAs layer 25 serving as a cap layer is formed by 4
The reason for making the thickness thinner than nm is to remove a part of the n-GaAs layer 25 by etching, form a gate electrode of the D-mode HEMT on the n-GaAs layer 25, and form the E-mode on the n-InGaP layer 24. Form the gate electrode of HEMT,
This is for optimally designing the threshold value.

In this case, the strained layer becomes an electron transit layer i-
The InGaAs layer 23 is formed on the n-InGaP layer 24 serving as an electron supply layer and the n-G serving as a cap layer.
Although the aAs layer 25 is formed, conventionally, as described above, the extremely thin n-InGaP layer 24 and n-GaAs layer 25 are formed.
However, it was not confirmed how it is affected by the strained i-InGaAs 23.

[0010]

The inventors of the present invention have grown a GaAs layer on an InGaP / InGaAs type crystal stack by a conventional method, and have examined the surface state of the grown GaAs layer by an atomic force microscope (AFM). ), It was discovered that many holes were formed in the n-GaAs layer 25.

Here, a GaAs layer is grown on the InGaP / InGaAs type crystal laminated body by the MOVPE method, a depressurizing barrel type furnace is used as a growth furnace, and a group III raw material is trimethylgallicim (TMG) or triethylgallium ( TEG), trimethylindium (TMI), V
The group material was arsine (AsH ₃ ). In addition, the pressure in the depressurized barrel type furnace during the growth of the compound semiconductor layer was set to 50 torr.
r, the growth temperature was 660 ° C., and the growth substrate was a 3-inch GaAs (100) 2.5 ° off substrate.

FIG. 9 shows a conventional InGaP / InGaAs
3 is an atomic force micrograph showing the structure of a GaAs layer on a system crystal laminated body. According to this atomic force micrograph, n
It is observed that a large number of holes of about 3.4 × 10 ⁸ / cm ² are formed on the surface of the GaAs layer 25.

When the n-InGaP layer 24 and the n-GaAs layer 25 were grown without the intervention of the i-InGaAs layer 23, no holes were observed on the surface of the n-GaAs layer 25. In addition, the n-InGaP layer 24 and the n-Ga
Even if the growth condition of the interface of the As layer 25 was changed, this hole was not eliminated.

This is because the lattice constants of GaAs and InGaP differ greatly from the lattice constants of InGaAs.
-Strain is generated in the InGaAs layer 23, P in the V group is desorbed from the strained portion, and a small region in which composition switching from the n-InGaP layer 24 to the n-GaAs layer 25 is poor does not depend on the growth conditions. It is thought to occur.

The thickness of the n-InGaP layer 24 is 100 nm.
If the thickness is about the same, no holes are formed on the surface of the n-GaAs layer 25. This is from the n-InGaP layer 24 to the n-
The switching interface to the GaAs layer 25 has a strained i-
This is because it is separated from the InGaAs layer 23.

This InGaP / InGaAs HEMT
In the InGaP / InGaAs-based crystal laminated body for forming the n-InGaP layer 25, it is necessary to reduce the film thickness of the n-InGaP layer 24 as described above, and therefore it is necessary to avoid the formation of holes on the surface of the n-GaAs layer 25. However, if an etching stopper layer made of InGaP having a large etching rate difference is formed on the n-GaAs layer 25 in which such a hole is formed, InGaP enters into the hole and the etching stopper layer is etched. When removing
Since the etching rate of InGaP is extremely high, the electron supply layer made of InGaP under the hole is also etched.

When a D-mode gate electrode is formed on the surface of the n-GaAs layer 25 having the hole, the gate electrode may come into contact with the n-InGaP layer 24 which is the electron supply layer. Even when the n-type GaAs layer does not penetrate the n-GaAs layer 25, the phenomenon that the threshold voltage shifts occurs due to the mixture of the D-mode characteristic and the E-mode characteristic.

It is also observed that the holes formed on the surface of the n-GaAs layer 25 will be filled if the n-GaAs layer 25 is grown thicker than 20 nm. n-Ga
Under the hole of the As layer 25, n-InG, which is an electron supply layer, is formed.
There is an aP layer 24 and its surface is strained into InGaAsP and G
It is considered that aAs is hard to grow.

Although it is considered that GaAs grows from the side wall of the hole in the hole, the side wall of the hole has a (311) plane, etc.
The growth rate of As is extremely slow. Therefore, it takes a long time to fill the hole, and as a result, the hole is filled when the n-GaAs layer 25 as the cap layer is thickened. However, for the above reason, in this case, the thickness of the n-GaAs layer 25, which is the cap layer, needs to be suppressed to about 5 nm, so that the generation of holes cannot be avoided.

The present invention provides a compound semiconductor device and a method of manufacturing the same, and in particular, provides a means for growing a high quality GaAs layer on an InGaP / InGaAs crystal stack.
Another object of the present invention is to provide a method for measuring a defect in a compound semiconductor layer.

[0021]

In the compound semiconductor device according to the present invention, the GaAs substrate and the lattice constant formed on the GaAs substrate include a strain due to the mismatch of lattice constants, but have no dislocation and are thin. Compound semiconductor layer and GaA formed on the thin compound semiconductor layer containing the strain
A structure including the s layer, in which the GaAs layer is a layer that has been grown to a target film thickness after being interrupted in growth before growing to a target film thickness and annealed in an arsenic atmosphere, was adopted.

In this case, the film thickness of the GaAs layer when the growth is interrupted and annealed in the arsenic atmosphere can be set to a film thickness of 30 atomic layers or less.

In this case, the compound semiconductor layer containing strain is formed of InGaAsP, InGaAs,
GaAsP, GaP, InAs, GaAsSb, InG
aAsSb, GaSb, InSb, and a film thickness of 50n between the compound semiconductor layer containing strain and the GaAs layer.
A compound semiconductor layer containing P of m or less can be present.

In this case, InGaP / InGaA
s type or AlGaInP / InGaAs type HEMT
GaAs cap layer is formed on the InGaP or AlGaInP electron supply layer, and the growth is interrupted before the GaAs cap layer grows to a target thickness, and the target thickness is obtained after annealing in an arsenic atmosphere. Can be a layer that has been grown up to.

Further, in the method of manufacturing a compound semiconductor device according to the present invention, a step of growing a thin compound semiconductor layer having a non-matching lattice constant on a GaAs substrate and a GaAs layer growing on the thin compound semiconductor layer. It is possible to adopt a step of suspending the growth before the thickness of the GaAs layer grows to a target thickness, annealing it in an arsenic atmosphere and growing it to a target thickness.
In this case, the electron supply layer may be AlGaInP.

In this case, when the GaAs layer is grown to have a thickness of 30 atomic layers or less, the growth can be interrupted, the annealing can be performed in the arsenic atmosphere, and the growth can be performed again.

Further, in this case, the annealing temperature is made equal to or higher than the growth temperature, or the arsenic pressure during annealing is made equal to or higher than that at the time of growing the GaAs layer,
Further, the GaAs layer can be grown by the metal organic chemical vapor deposition method.

Another compound semiconductor device according to the present invention is made of a compound semiconductor and has a plane orientation of (10
0) A structure in which a compound semiconductor layer grown on an off substrate inclined in the just direction or the (111) A direction was used as a carrier transit layer was adopted.

In this case, the off-substrate tilt angle can be set within 4 °, the compound semiconductor device can be a high electron mobility transistor (HEMT), and the compound semiconductor layer can be a III-V group compound semiconductor. , A layer containing As and a layer containing P can be configured to include a heterojunction.

In this case, the substrate made of compound semiconductor may be GaAs, the electron transit layer may be InGaAs, and the electron supply layer may be InGaP or AlGaInP.

Further, in the method of manufacturing a compound semiconductor device according to the present invention, carrier travel is performed on an off substrate made of a compound semiconductor and having a plane orientation inclined in the (100) just direction or the (111) A direction. A step of growing a compound semiconductor layer used as a layer was adopted.

In this case, the compound semiconductor layer can be grown by the metalorganic vapor phase epitaxy with the off-substrate tilt angle within 4 °.

Further, in another compound semiconductor device according to the present invention, a GaAs substrate having a plane orientation inclined in the (100) just direction or the (111) A direction, and the G
a thin compound semiconductor layer formed on the aAs substrate, which includes strain but does not have dislocations due to mismatching of lattice constants, and a GaAs layer formed on the thin compound semiconductor layer including strain, A structure was adopted in which the GaAs layer was a layer that was grown to a target film thickness after being interrupted in growth before being grown to a target film thickness and annealed in an arsenic atmosphere.

In another method of manufacturing a compound semiconductor device according to the present invention, the plane orientation is (100) just.
The step of growing a thin compound semiconductor layer having a non-matching lattice constant on a GaAs substrate inclined in the (111) A direction or the step of growing a GaAs layer on the thin compound semiconductor layer. A process was adopted in which the growth was interrupted before the GaAs layer was grown to a desired film thickness, annealed in an arsenic atmosphere, and then grown to a desired film thickness.

In the method of measuring a defect of a compound semiconductor layer according to the present invention, after a plurality of compound semiconductor layers are laminated and formed on a substrate, the upper compound semiconductor layer is removed by selective etching to form an intermediate layer. By observing the surface roughness of the layer, and also observing the roughness of the surface of the compound semiconductor layer of the uppermost layer, by comparison, caused the roughness of the surface of the compound semiconductor layer of the intermediate layer or the uppermost layer,
The method of indirectly measuring the state of minute defects and composition fluctuations in the lower compound semiconductor layer was adopted.

[0036]

OPERATION As in the compound semiconductor device of the present invention, GaAs
In the process of growing a thin compound semiconductor layer with a non-matching lattice constant on the substrate and growing a GaAs layer that will be a cap layer on this thin compound semiconductor layer, the thickness of this GaAs layer becomes the target thickness. A hole is generated in this GaAs layer by adopting a step of interrupting the growth before the growth, for example, at a stage where the film has grown to a film thickness of 30 atomic layers or less, annealing again in an arsenic atmosphere, and then growing again. Can be suppressed. In this case, it is possible to effectively suppress the generation of holes by setting the temperature and As pressure during this annealing to be the same as or higher than those for growing the GaAs layer.

This is annealing, especially temperature and As pressure,
The Ga atoms on the surface of the GaAs layer are energized by annealing that is the same as or higher than when the GaAs layer is grown,
By breaking the bond with As, expressing the effect of migrating the surface, and increasing the As pressure, Ga is prevented from diffusing from the surface into the gas phase. It is considered that Ga atoms migrate to the surface so that the surface free energy is minimized, and as a result, the holes that increase the surface free energy are closed.

[0038]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) In the method of manufacturing a compound semiconductor device of this embodiment, an InGaP / InGaAs crystal laminated body for manufacturing an InGaP / InGaAs HEMT is grown by the MOVPE method. Then, as in the prior art, a depressurized barrel type furnace was used as the growth furnace, the group III raw material was trimethylgallicim (TMG), triethylgallium (TEG), trimethylindium (TMI), and the group V raw material was arsine (AsH). ₃ ) and. The pressure during crystal growth was 50 torr, the growth temperature was 660 ° C., and the growth substrate was 3 inches (10 inches) made of GaAs.
0) A 2.5 ° off substrate was used, and the surface of the grown uppermost n-GaAs, which is a cap layer, was observed by an atomic force microscope (AF).
It was evaluated by M).

FIG. 1 shows InGaP / I according to the first embodiment.
FIG. 3 is a structural diagram of an nGaAs-based crystal laminated body. In this figure, 1 is a GaAs substrate, 2 is an i-GaAs layer, and 3 is an i-GaAs layer.
InGaAs layer, 4 is n-InGaP layer, 5 ₁ a first n-GaAs layer, 5 ₂ is a second n-GaAs layer.

InGaP / InGaA according to this embodiment
In the s-based crystal laminate, the i-GaAs layer 2 serving as a buffer layer and the i layer serving as a channel layer are formed on the GaAs substrate 1.
-The thickness of the InGaAs layer 3 and the electron supply layer is 30 nm
Thinner n-InGaP layer 4, a first n-GaAs layer 5 ₁ and the second n-GaAs layer 5 ₂ are sequentially grown at a growth condition described above for the cap layer.

Then, when growing the uppermost cap layer, the first n-thickness is set to a film thickness within 30 atomic layers under the above growth conditions.
After the growth of the -GaAs layer 5 _1, once the growth was suspended,
At a growth temperature of from 50 ° C. higher temperatures, AsH ₃ flow rate was doubled during the growth, and increased to annealing for 10 minutes As pressure, the second n-GaAs layer 5 ₂ again the growth conditions, the first
The n-GaAs layer 5 ₁ and the second n-GaAs layer 5 ₂ were grown to a thickness of 5 nm.

According to this embodiment, the second n-GaAs
Hole that occurs in the prior art to the layer 5 _second surface was reduced.

FIG. 2 shows InGaP / InG of the first embodiment.
3 is an atomic force micrograph showing the structure of a GaAs layer on an aAs-based crystal laminated body. From this atomic force micrograph, it can be seen that there are no holes on the surface of the _second n-GaAs layer 52 formed on the InGaP / InGaAs-based crystal laminated body.

The effect of annealing temperature and As pressure is remarkable when the temperature is higher than the growth condition. When the temperature and As pressure are lower than the growth temperature or the AsH ₃ flow rate is lower than that of the growth, annealing is performed. The holes on the surface of the _second n-GaAs layer 52 were not blocked even if the steps were added. InGaP is formed on the surface of the _second n-GaAs layer 52 formed by this embodiment.
When an etching stopper layer consisting of
Even if the mode HEMT and the E mode HEMT were made separately, no problem occurred in terms of characteristics.

In this embodiment, the compound semiconductor layer containing strain is formed of InGaAsP, In having a critical film thickness or less.
GaAs, GaAsP, GaP, InAs, GaAsS
b, InGaAsSb, GaSb, InSb.

Further, an InG film having a thickness of 50 nm or less is formed between the compound semiconductor layer containing strain and the GaAs layer serving as the cap layer.
When a compound semiconductor layer containing P such as aP exists, it is possible to suppress the scattering of P that is easily released due to strain.

As described above, the atomic force micrograph of FIG. 2 in this embodiment shows InGaP / In.
Second n-GaA formed on GaAs-based crystal stack
By observing the surface of the s layer 5 _2, in which the roughness of indirect n-InGaP layer 4 and i-InGaAs layer 3 on the surface of the underlying tried to measure. The present inventors have further made the first n-GaAs layer 5 ₁ and the second n-GaAs on the InGaP / InGaAs-based crystal laminated body.
After forming the layer 5 _2, the second n-GaAs layer 5 ₂ and the first n-GaAs layer 5 _1, or the surface of the n-InGaP layer 4 directly removed by etching n-InGaP layer 4 Ya The roughness of the surface of the i-InGaAs layer 3 was observed by an atomic force microscope.

[0048] More specifically, the first n-GaAs layer 5 ₁ and the second n-GaAs layer 5 ₂ (hydrofluoric acid + H ₂ O ₂ + H ₂
The surface of the n-InGaP layer 4 and the surface of the i-InGaAs layer 3 were observed with an atomic force microscope.

However, from the above observation, the n of the lower layer is
A second n-GaAs layer 5 ₂ roughness of roughness and the top layer of the surface or i-InGaAs layer 3 of the surface of the -InGaP layer 4 was found to be different to the extreme. That is, even if the second n-GaAs layer 5 _{and second} surface of the uppermost large number of holes occurs and observing the underlying n-InGaP layer 4 on the surface or i-InGaAs layer 3 on the surface directly, In some cases no holes were observed.

The reason for this is that even in the i-InGaAs layer 3, composition fluctuations and minute defects in which the minute portions of InAs and the minute portions of GaAs are separated can be observed by an atomic force microscope. No, i-InGaA
No abnormality is observed on the surface of the s layer 3.

However, such a composition fluctuation influences the growth mode of the semiconductor layer formed thereon, and therefore the surface of the n-InGaP layer 4 or the first n-G layer.
On the surfaces of the aAs layer 5 ₁ and the second n-GaAs layer 5 ₂ , i
-It is considered that this appears in the form that the composition fluctuation of the InGaAs layer 3 is revealed.

Since the i-InGaAs layer 3 is an electron transit layer, composition fluctuations in this layer adversely affect the characteristics. Therefore, composition fluctuations should normally be observed when the i-InGaAs layer 3 is grown. However, the method for observing this has not been established.

Using this knowledge, by observing the surface of the upper semiconductor layer, minute defects such as composition fluctuation of the lower layer are estimated, and the substrate is excluded from the manufacturing process or composition fluctuation occurs. It can be used as a sample to investigate the cause. In addition, in order to directly observe the roughness of the surface of the i-InGaAs layer 3,
When the temperature is lowered after the growth of n and the surface is observed, the roughness becomes completely different from the surface roughness of the i-InGaAs layer 3 when the n-InGaP layer 4 and the like are continuously grown on the surface. It was found that the effect on HEMT properties cannot be observed.

(Second Embodiment) Metal Organic Chemical Vapor Deposition (MOVP) of Compound Semiconductor Layer for Manufacturing Compound Semiconductor Device
In the case of growing by the method E), conventionally, an off-substrate made of a compound semiconductor having a (2-4 °) plane orientation slightly deviated from the (100) direction has been used as the substrate. The off direction was the (100) direction.

This is because when the compound semiconductor substrate turned off in the above-mentioned direction is used, a large number of kinksites are formed, and it has been considered from the result of chloride growth that it is essential for epitaxial growth. Moreover, since the high current gain of the AlGaAs HEMT cannot be obtained without using the off-substrate, it is necessary to turn off the substrate in order to improve the steepness of the composition of the hetero interface and prevent the inclusion of oxygen impurities. Was believed to exist.

However, recently, In was added to the electron supply layer.
The HEMT using GaP has excellent low noise characteristics and
Due to the physical properties of GaP, the layer can be made thin so that a high current gain can be obtained, and since it does not contain Al, it is attracting attention because it is strong against oxidation, and it is being replaced with an AlGaAs HEMT.

When InGaAs is used for the electron transit layer in this InGaP HEMT, As and P of both compositions are switched at an important hetero interface which determines the two-dimensional electron gas characteristics, but the V group has a large vapor pressure. Since it is easy to detach from the surface, it is necessary to improve the steepness of the switching of group V. II
It is more difficult than that of the I group. Therefore, AlGa
It is difficult to obtain good characteristics only by the know-how accumulated regarding the growth of As-based HEMT, and it is necessary to devise the growth sequence itself.

HEM using InGaP for electron supply layer
It has not been confirmed whether the plane orientation of the growth substrate, which is one of the growth conditions for each crystal layer of T, may be the same as in the case of the conventional AlGaAs HEMT. InGaAs
Since the electron transit layer has a lattice mismatch with GaAs, the electron transit layer contains strain, which causes a problem of increasing the roughness of the hetero interface.

The largest factor for increasing the roughness of the hetero interface is irregular two-dimensional growth called step bunching. It is considered that this irregular two-dimensional growth is likely to occur when the step of the off-substrate is on the surface, and it seems to be related to the step shape of the off-substrate, but it has not been confirmed.

The present inventors have examined the relation between the roughness of the hetero interface and the plane orientation of the growth substrate due to the lattice mismatch between the InGaAs electron transit layer and the GaAs electron supply layer. (100) Just direction,
It was discovered that the roughness at the hetero interface can be minimized and the composition steepness can be improved by turning off in the (111) A plane direction, particularly by setting the off angle to within 4 °.

Thus, the plane orientation of the growth substrate is set to (10
0) just or by turning off in the (111) A plane direction from the direction, the step can be eliminated or only the A step can be exposed on the surface, and the group V element enters the epitaxial layer at the time of switching the group V. Can be minimized. As a result, it is possible to improve the steepness of switching between As and P, and by keeping the surface direction within 4 °, it is possible to prevent excessive occurrence of step bunching.

FIG. 3 shows InGaP / I according to the second embodiment.
FIG. 3 is a structural diagram of an nGaAs-based crystal laminated body. In this figure, 11 is a GaAs substrate, 12 is an i-GaAs layer, and 13
Is an i-InGaAs layer, 14 is an i-InGaP layer, 15
Is an n-InGaP layer, and 16 is an n-GaAs layer.

InGaP / InGaA according to this embodiment
In the s-based crystal laminate, on the GaAs substrate 11,
I-GaAs layer 12 which becomes a buffer layer, i-InGaAs layer 13 which becomes an electron transit layer, i which becomes an impurity scattering suppressing layer
-InGaP layer 14 and n-InGaP serving as an electron supply layer
A layer 15 and an n-GaAs layer 16 to be a cap layer are sequentially formed.

InGaP / InGaA shown in this figure
The crystal laminated body for producing the s-based HEMT is grown by MOVPE method using a decompression barrel type furnace as a growth furnace, TMG, TEG, TMI as a group III raw material, and AsH ₃ , PH ₃ as a group V raw material. , Growth pressure 50 torr
r, the growth temperature was 660 ° C., and a GaAs substrate 11 with a diameter of 3 inches having various off angles was used as the growth substrate. Then, the roughness of the hetero interface when the off angle was changed was evaluated by an atomic force microscope (AFM).

FIG. 4 is a diagram showing the relationship between electron mobility and roughness when the off direction of the growth substrate is changed. In this figure,
It becomes an electron transit layer when the off direction of the growth substrate is changed i
The relationship between the electron mobility in the -InGaAs layer 13 and the surface roughness of the n-GaAs layer 16 serving as the cap layer is shown, but the off angles are all 2 °.

The n-GaAs layer 1 which will be the cap layer
The surface roughness of No. 6 is the same as that of the i-InGaAs layer 13 and i-
Since the roughness of the heterojunction between the InGaP layers 14 is reflected, the roughness of the heterojunction can be indirectly evaluated by evaluating the roughness of the surface of the n-GaAs layer 16 serving as the cap layer. .

From this figure, the off direction of the growth substrate is (10
It can be seen that when 0) just, the roughness is the smallest and the mobility is also high. It can be seen that when the growth substrate is off from (100) just, there is a few nm of roughness, due to step bunching. Also, it can be seen that the roughness of the off-substrate in the (111) A, (110), and (111) B directions is almost the same, but there is a large difference in the mobility of electrons.

The electron mobility is highest when turned off in the (111) A plane, followed by the conventional (110) direction, and worst when turned off in the (111) B direction. It has been discovered that the composition steepness of the interface determines the mobility in addition to the roughness of the heterojunction, and that the switching steepness of the V group has a great influence on the characteristics. Therefore,
It was examined by the PL method whether or not there is a difference in composition steepness due to OFF.

FIG. 5 is a diagram for explaining changes in the PL emission wavelength when AsH ₃ is flown on the surface of the InGaP layer. The horizontal axis of this figure shows the emission wavelength (nm), and the vertical axis shows the PL intensity (arbitrary unit). The curve a in this figure shows the PL emission intensity from the InGaP surface when grown by a normal growth method and GaAs is not formed on it.
Curve b shows the PL emission intensity from the surface when InGaP was grown and then annealed in AsH ₃ .

When AsH ₃ is flown on the surface of the InGaP layer and annealed, As is incorporated into InGaP, the result of measurement at 77 K shows that the center of the emission wavelength is approximately 6.
The wavelength shifts from 55 nm to almost 690 nm toward the long wavelength side. Since this shift amount is proportional to the As incorporation amount, it was decided to use it for the evaluation of switching steepness.

6 and 7 are PL emission spectrum diagrams when the off direction of the substrate is changed, and (A) to (D) show PL emission spectra when the off direction is changed. The three curves drawn in these figures show that the PL emission spectra at three points on the surface of the InGaP layer are measured. From these figures, the center of the emission wavelength shifts most when turned off in the (111) B direction, and the center of this emission wavelength when turned off in the (100) just and (111) A directions. It can be seen that the shift of is small. Therefore, (100) just and (1
11) It can be said that the composition steepness becomes the best when it is turned off in the A-plane direction.

From the above, rather than turning off in the conventional (110) direction, (100) just or (111)
The composition steepness is better when turned off in the A plane direction, and the HEM
The characteristics of T can be further improved. Further, when the off angle is set to 4 ° or more, the stability of the surface free energy of InGaAs makes the formation of the (311) plane remarkable and deteriorates the roughness of the hetero interface. Therefore, the off angle is set to 4 ° or less. I found it desirable to do.

In the first embodiment described above, when a thin compound semiconductor layer whose lattice constant does not match is grown on a GaAs substrate and a GaAs layer is grown thereon, this GaAs is used.
The second embodiment is a method of manufacturing a compound semiconductor device, in which the growth is interrupted when the layer has grown to have a thickness of 30 atomic layers or less, annealed in an arsenic atmosphere, and then grown again. The present invention relates to a method for manufacturing a compound semiconductor device in which a compound semiconductor layer used as a carrier traveling layer is grown on an off-substrate whose plane orientation is inclined within 4 ° in the (100) direction or the (111) A direction. However, a compound semiconductor device having better characteristics can be realized by combining the features of both the embodiments.

In each of the above-mentioned embodiments, the case where the HEMT is manufactured has been described, but the present invention will be described.
It can also be applied to other field effect semiconductor devices.

[0075]

According to the present invention, the yield of the InGaP / InGaAs HEMT manufacturing process by MOVPE growth can be improved, and such low noise HEMT and HE can be manufactured.
It greatly contributes to the reduction of the manufacturing cost of MTLSI.

[Brief description of drawings]

FIG. 1 is a structural diagram of an InGaP / InGaAs-based crystal laminated body according to a first embodiment.

FIG. 2 is an atomic force microscope photograph showing the structure of a GaAs layer on the InGaP / InGaAs-based crystal laminated body of the first embodiment.

FIG. 3 is a structural diagram of an InGaP / InGaAs-based crystal laminated body according to a second embodiment.

FIG. 4 is a graph showing the relationship between electron mobility and roughness when the off direction of the growth substrate is changed.

FIG. 5 is an explanatory diagram showing a change in PL emission wavelength when AsH ₃ is flown on the surface of the InGaP layer.

FIG. 6 is a PL emission spectrum diagram (1) when the off direction of the substrate is changed, and (A) and (B) show PL emission spectra when the off direction is changed.

FIG. 7 is a PL emission spectrum diagram (2) when the off direction of the substrate is changed, and (C) and (D) show PL emission spectra when the off direction is changed.

FIG. 8 is a structural diagram of a conventional InGaP / InGaAs-based crystal laminated body.

FIG. 9 is an atomic force microscope photograph showing the structure of a GaAs layer on a conventional InGaP / InGaAs-based crystal laminated body.

[Explanation of symbols]

1 GaAs substrate 2 i-GaAs layer 3 i-InGaAs layer 4 n-InGaP layer 5 ₁ 1st n-GaAs layer 5 ₂ 2nd n-GaAs layer 11 GaAs substrate 12 i-GaAs layer 13 i-InGaAs layer 14 i-InGaP layer 15 n-InGaP layer 16 n-GaAs layer 21 GaAs substrate 22 i-GaAs layer 23 i-InGaAs layer 24 n-InGaP layer 25 n-GaAs layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/205

Claims (21)

[Claims] 1. A GaAs substrate, a thin compound semiconductor layer having strains and no dislocations due to mismatch of lattice constants formed on the GaAs substrate, and a thin compound semiconductor layer having the strains. A layer including a GaAs layer formed above, the growth being interrupted before growing to a target thickness, and being grown to a target thickness after annealing in an arsenic atmosphere And a compound semiconductor device. 2. The compound semiconductor device according to claim 1, wherein the film thickness of the GaAs layer when the growth is interrupted and annealed in an arsenic atmosphere is within 30 atomic layers. 3. The compound semiconductor layer containing strain is made of InGaAsP, InGaAs, GaAsP, G having a critical thickness or less.
aP, InAs, GaAsSb, InGaAsSb, G
The compound semiconductor device according to claim 1, wherein the compound semiconductor device is aSb or InSb. 4. The compound semiconductor device according to claim 1, wherein a compound semiconductor layer containing P having a film thickness of 50 nm or less is present between the compound semiconductor layer containing strain and the GaAs layer. 5. InGaP / InGaAs system or A
After the GaAs cap layer is formed on the InGaP or AlGaInP electron supply layer of the lGaInP / InGaAs HEMT, the growth is interrupted before the GaAs cap layer grows to a target thickness, and after annealing in an arsenic atmosphere. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a layer grown to a target film thickness. 6. A method comprising: growing a thin compound semiconductor layer having a non-matching lattice constant on a GaAs substrate; and growing a GaAs layer on the thin compound semiconductor layer.
A method of manufacturing a compound semiconductor device, characterized in that the growth is interrupted before the aAs layer is grown to a desired film thickness, and the film is grown to a desired film thickness after annealing in an arsenic atmosphere. 7. The method according to claim 6, wherein when the GaAs layer is grown to a thickness of 30 atomic layers or less, the growth is interrupted, the GaAs layer is annealed in an arsenic atmosphere, and then grown again.
A method for manufacturing the compound semiconductor device according to 1. 8. The method of manufacturing a compound semiconductor device according to claim 6, wherein the annealing temperature is equal to or higher than the growth temperature. 9. The method of manufacturing a compound semiconductor device according to claim 6, wherein the arsenic pressure at the time of annealing is the same as or higher than that at the time of growing the GaAs layer. 10. The method of manufacturing a compound semiconductor device according to claim 6, wherein the GaAs layer is grown by a metal organic chemical vapor deposition method. 11. A compound semiconductor, having a plane orientation of (1
00) A compound semiconductor device characterized by using a compound semiconductor layer grown on an off-substrate tilted in the just direction or the (111) A direction as a carrier transit layer. 12. The compound semiconductor device according to claim 11, wherein the off-substrate has an inclination angle of 4 ° or less. 13. The compound semiconductor device according to claim 11, wherein the compound semiconductor device is a high electron mobility transistor. 14. The compound semiconductor device according to claim 11, wherein the compound semiconductor layer is made of a III-V group compound semiconductor and includes a heterojunction of a layer containing As and a layer containing P. 15. A substrate made of a compound semiconductor is GaAs.
12. The compound semiconductor device according to claim 11, wherein the electron transit layer is InGaAs and the electron supply layer is InGaP or AlGaInP. 16. A compound semiconductor, having a plane orientation of (1
00) A method of manufacturing a compound semiconductor device, which comprises growing a compound semiconductor layer used as a carrier transit layer on an off-substrate tilted in the just direction or the (111) A direction. 17. The method of manufacturing a compound semiconductor device according to claim 16, wherein the off-substrate has an inclination angle of 4 ° or less. 18. The method of manufacturing a compound semiconductor device according to claim 16, wherein the compound semiconductor layer is grown by a metal organic chemical vapor deposition method. 19. A GaAs off-substrate having a plane orientation inclined in the (100) just direction or the (111) A direction and a strain due to a mismatch of lattice constants formed on the GaAs off-substrate. A thin compound semiconductor layer having no dislocations and a GaAs layer formed on the thin compound semiconductor layer containing the strain, the growth is interrupted before the GaAs layer grows to a target film thickness, and arsenic A compound semiconductor device, which is a layer grown to a target film thickness after being annealed in an atmosphere. 20. A step of growing a thin compound semiconductor layer having a non-matching lattice constant on a GaAs substrate having a plane orientation inclined in the (100) just direction or the (111) A direction, and the thin compound semiconductor layer A step of growing a GaAs layer on the GaAs layer, the growth of the GaAs layer is interrupted before it grows to a target film thickness, and the film is grown to a target film thickness after annealing in an arsenic atmosphere. Method of manufacturing compound semiconductor device. 21. After stacking a plurality of compound semiconductor layers on a substrate, the upper layer compound semiconductor layer is removed by selective etching to observe the surface roughness of the intermediate layer, and the uppermost compound semiconductor layer. By observing and comparing the roughness of the surface of the layer, the state of minute defects and composition fluctuations of the lower compound semiconductor layer, which causes the roughness of the surface of the intermediate layer or the uppermost compound semiconductor layer, can be indirectly determined. A method for measuring a defect in a compound semiconductor layer, comprising: