JPH07134161A - Aging board considering testing board - Google Patents

Abstract

PURPOSE:To test an aged semiconductor element without replacing by laying the wiring conductor of a split board into states suitable for aging and testing, respectively. CONSTITUTION:A semiconductor element to be aged and tested is connected to each IC socket 23 of each split board 20, and the male electric connector 24 of the board 20 is fitted to the corresponding female electric connector of an aging board body. A clip 26 is fitted to a flip connector 25. Thus, the wiring conductor of the board 20 has the connection relation suitable for aging, and the combined aging board is aged in a constant temperature bath. After aging, each board 20 is removed from the aging board body as the semiconductor element is still connected to the socket 23, and applied to a higher tester followed by testing. At this time, the clip 26 is removed from the connector 25, and the connecting terminal connected to each terminal of the socket 23 is separated from the connecting terminal connected to the wiring conductor to lay the wiring conductor into the state suitable for testing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an aging board for aging semiconductor elements such as ICs, and a test board for performing various tests.

[0002]

2. Description of the Related Art Initially, semiconductor devices such as semiconductor memories always have an initial defect. If a defect occurs after being handed over to a user, it becomes a fatal problem. Therefore, aging is performed to remove the initial defective element.

The relationship between the usage time of a semiconductor element and the failure occurrence rate is shown in a graph with the usage time on the horizontal axis and the failure occurrence rate on the vertical axis. The curve of the graph is exactly the shape of a bath tub. , This curve is called the bathtub curve. As can be seen from such a bathtub curve, generally, when a semiconductor device is used at room temperature (25 ° C. to 30 ° C.), an initial defect appears within 1000 hours, and
The real life comes to the end in about 10,000 hours or more.

Therefore, if the aging is performed at room temperature, it takes a very long time of about 1000 hours for the aging. Therefore, the aging that is generally performed is performed at 125 ° C. in the case of a memory, and it takes about 50 to 90 hours instead of 1000 hours.

In order to perform such aging of a semiconductor memory or the like, conventionally, a large number of IC sockets are arranged in a matrix on a substrate having a width of about 300 to 450 mm and a length of about 500 to 650 mm. I am using an aging board with a wiring conductor to the terminal.

[0006]

However, the density of the semiconductor memory has been quadrupled every four years and the density of 1 Mbit,
After the 4M-bit era, it is now 16Mbit. As described above, all the semiconductor memories must be aged at the same time, and all the bits must be measured at the same time, and each judgment item must be tested and judged. Therefore, a tester for performing such a test is very expensive, and the number of semiconductor elements that can be tested at one time is limited.

On the other hand, in the conventional aging board, 128 to 256 semiconductor elements can be mounted on each aging board so that as many semiconductor elements as possible can be aged at one time. Such an aging board has a relatively large size as described above, and with such a large board, the waveform on the entrance side is combined with the reflected wave, which is not preferable as a test waveform requiring accuracy. It becomes a thing. Therefore, after aging a large number of semiconductor elements with such an aging board, it was not possible to hang it on the tester as described above with the large number of semiconductor elements mounted on the aging board. Therefore, in the past, after aging, after aging, each semiconductor element was removed from each IC socket on the aging board, and each semiconductor element was reattached to the IC socket of the test board, and then mounted on the tester. I had to do a test. If a large number of semiconductor elements have to be replaced with test boards after aging in this way, it is very troublesome and time consuming.

Therefore, there is a demand for a system in which as many semiconductor elements as possible can be mounted at the same time for aging, and it is not necessary to replace each semiconductor element after aging, and moreover, accurate testing can be performed on a relatively small substrate. Is coming.

An object of the present invention is to provide an aging board considering a test board, which can meet such a demand.

[0010]

According to one feature of the present invention, a semiconductor element socket for connecting a semiconductor element to be aged and tested, a wiring conductor to each terminal of the semiconductor element socket, and the wiring conductor. A plurality of divided boards each having an electric connector terminating at the time of aging, the divided boards are coupled to each other through the electric connectors during aging, and the wiring conductors are interconnected in a state suitable for aging. Thus, an aging board is provided which can make each of the wiring conductors in a state suitable for the test by separating the respective electrical connectors from each other at the time of the test.

According to another feature of the present invention, each of the divided boards of the aging board as described above can selectively connect and disconnect between each terminal of each semiconductor element socket and the wiring conductor. Clip means for doing so.

[0012]

The present invention will now be described in more detail with reference to the accompanying drawings.

FIG. 1 of the accompanying drawings is a schematic perspective view showing an aging board in consideration of a test board as one embodiment of the present invention, and FIG. 2 is an example of a divided board constituting the aging board of FIG. It is a schematic perspective view which shows a sheet. As shown in FIG. 1, the aging board 100 of this embodiment is formed by connecting a plurality of divided boards 10 (four of which are shown in FIG. 1) having the same structure in cascade connection. To be done.

As shown in FIG. 2, each divided board 10 has ten IC sockets 13 arranged in a matrix on a printed circuit board 12 framed by a reinforcing metal frame 11. These IC sockets 13
May be conventional for mounting semiconductor devices such as semiconductor memories to be aged and tested. Although a large number of wiring conductors for each terminal of each IC socket 13 are provided on the printed circuit board 12, they are not shown in FIGS. 1 and 2 for the sake of simplicity. . Such a wiring conductor will be described later.

A male electric connector 14 for connecting wiring conductors between the divided boards is provided on one edge of the divided board 10, and a female electric connector 15 is provided on the other edge. Is provided. These electrical connectors may be constructed like ordinary edge connectors. The male electrical connector 14 of one split board 10 is replaced by the corresponding female electrical connector 1 of the other split board 10.
As shown in FIG. 1, it is possible to configure an edge board in which a plurality of divided boards 10 are connected in series by fitting them to each other.
The wiring conductors of 0 have a connection relation suitable for aging through fitting of the electric connectors.

Further, the split board 10 of this embodiment is provided with a clip means for selectively connecting and disconnecting each terminal of each IC socket 13 and the wiring conductor. In FIG. 1, these clip means are omitted for simplicity of the drawing. In this embodiment, the clip means is arranged on the printed circuit board 12, and the first connection terminals connected to the respective terminals of the corresponding IC socket 13 are arranged in a line and connected to the corresponding wiring conductors. The clip connector 16 in which the second connection terminals are arranged in a row apart from the first connection terminal, and the first connection terminal and the second connection terminal which are fitted into the clip connector 16 and correspond to each other And a clip 17 for short-circuit connection between them. The terminals of the IC socket 13, the wiring conductor on the printed circuit board 12, the first connection terminal of the clip connector 16, and the second connection terminal of the clip connector 16.
The connection relationship with the connection terminal will be described later.

FIG. 3 is a schematic perspective view showing an aging board in consideration of a test board as another embodiment of the present invention, and FIG. 4 shows one of the divided boards constituting the aging board of FIG. It is a schematic perspective view shown. As best shown in FIG. 3, the aging board 200 of this embodiment.
Is constituted by connecting a plurality of, in this embodiment, 10 divided boards 20 of the same structure in parallel on an aging board body 202 framed by a reinforcing metal frame 201.

As shown in FIG. 4, each divided board 20 has ten IC sockets 23 arranged in a matrix on a printed circuit board 22 framed by a reinforcing metal frame 21. These IC sockets 23
May be conventional for mounting semiconductor devices such as semiconductor memories to be aged and tested. A large number of wiring conductors for each terminal of each IC socket 23 are provided on the printed circuit board 22, but are not shown in FIGS. 3 and 4 to simplify the drawing. . Such a wiring conductor will be described later.

At the lower edge of the split board 20, there are provided a wiring conductor (not shown in FIG. 3 for simplification of the drawing) provided on the aging board body 202 and a wiring conductor of the split board. A male electrical connector 24 is provided for making connections between them. Although not shown in FIG. 3, at a corresponding position of the aging body 202, a corresponding number, in this example, ten female electrical connectors are juxtaposed in parallel. These electrical connectors may be constructed like ordinary edge connectors. By fitting the male electrical connector 24 of each split board 20 to the corresponding female electrical connector (not shown in FIG. 3) of the aging board body 202, as shown in FIG. Multiple divided boards 20
Can be configured to be connected in parallel, and the wiring conductors of each divided board 20 have a connection relationship suitable for aging through fitting of the electric connectors.

Further, the split board 20 of this embodiment is also provided with a clip means for selectively connecting and disconnecting each terminal of each IC socket 23 and the wiring conductor. In FIG. 3, these clip means and the IC socket are omitted for the sake of simplicity. In this embodiment, this clipping means is arranged on the printed circuit board 22 and corresponds to the corresponding IC socket 2
Arrange the first connection terminals connected to each terminal of 3 in a line,
The second connection terminal connected to each corresponding wiring conductor is
Clip connector 25 that is arranged in a row apart from the connection terminals, and a clip that is fitted to the clip connector 25 and short-circuits the corresponding first connection terminal and second connection terminal It consists of 26. Each terminal of these IC sockets 23, printed circuit board 2
The connection relationship between the wiring conductor on the second wiring terminal 2 and the first connection terminal and the second connection terminal of the clip connector 25 will be described later.

According to the structure of the aging board of the embodiment as shown in FIGS. 3 and 4, when the width of the aging board body 202 is 300 mm and the length is 600 mm, the aging board body 202 is placed on the aging board body 202. The maximum number of the split boards 20 that can be connected in parallel can be set to 20 with a parallel arrangement pitch of about 25 mm. In this case, when the IC sockets 23 are arranged in two rows with eight in each row on each divided board 20,
An aging board on which 20 × 320 semiconductor elements can be mounted for aging. When the IC sockets 23 are arranged in three rows on each divided board 20, it is possible to use an aging board on which 24 × 20 = 480 semiconductor elements can be mounted for aging.

FIG. 5 shows each divided board 10 as described above.
Or between the wiring conductor provided on the printed circuit board 12 or 22 of 20, the terminals of each IC socket 13 or 23, and the first connection terminal and the second connection terminal of the clip connector 16 or 25. FIG. 3 is a partial view for explaining the connection relationship of FIG. As partially shown in FIG.
On the printed circuit board of the split board, wiring conductors 34 for aging and various tests are provided so as to be connected to corresponding terminals of corresponding electric connectors. Further, a wiring conductor 33 connected to each terminal of each IC socket 13 or 23 is also provided. Wiring conductor 31
Is connected to the first connection terminal 31 of the clip connector 16 or 25, and the other end of the wiring conductor 34 is connected to the corresponding second connection terminal 3 of the clip connector 16 or 25.
Connected to 2.

Next, with reference to FIGS. 6 and 7, a mode for performing aging and testing using the aging board in consideration of the test board of the present invention as described above will be described. In order to perform aging and various tests using the aging board 200 of the embodiment described with reference to FIGS. 3 and 4, first, with respect to each IC socket 23 of each divided board 20, the semiconductor memory to be aged and tested is tested. By connecting such semiconductor elements and fitting the male electric connectors 24 of the respective split boards 20 to the corresponding female electric connectors of the aging board body 202 as shown in FIG. Complete the combination as a board.
The aging board combined in this way is
As usual, it is placed in a constant temperature bath and aged as usual. At this time, if the burn-in monitor aging system is used, it is possible to perform a test that does not require so much accuracy, such as checking whether there is an output that occupies about 5% of the necessary test items. With such monitor aging, it takes about 100 hours in 50 to 90 hours.
The 00 semiconductor memories can be monitored and aged.

As described above, in the check of the presence or absence of the output in the monitor aging, the semiconductor element determined to have already failed due to the absence of the output should be identified and stored by the computer attached to the system. You can

After such aging, the divided boards 20 are removed from the aging board body 202, and the aging board main body 202 is removed as shown in FIG.
As shown in, the batch tester 300 is applied to perform a batch test. At this time, each semiconductor element may remain fitted in the IC socket 23, and the clip 26 may also remain fitted in the clip connector 25. Note that FIG.
In order to simplify the drawing, the IC socket 23
The semiconductor element connected to is omitted.

In the batch tester 300, a test such as measurement of a refresh time (about 100 nanoseconds), which occupies about 75% of necessary test items and requires relatively high precision, is performed. Each item of the batch tester 300 can be tested in about 30 to 40 minutes with 256 semiconductor devices. At the time of this batch test, a semiconductor element which has already been determined to have failed in the aforementioned monitor aging based on the memory of the computer can be removed from the test. In this batch test, a semiconductor element determined to have an abnormal refresh time or the like can be identified and stored by a computer attached to the system.

After the batch test by such a batch tester 300, as shown in FIG. 7, each divided board 20 is hung on the high-grade tester 400 with the clip 26 removed from the clip connector 25. Also in this case, the semiconductor element may remain fitted and connected to each IC socket 23. The test by the high-level tester 400 is a test that requires very high accuracy, such as measurement of an access time (about 1 nanosecond) that accounts for about 25% of the remaining required test items. Also in this high-grade test, based on the memory of the computer, regarding the semiconductor element which is already judged as not normal in the batch test,
It can be removed from the test.

Each clip connector 2 of each divided board 23
When the clip 26 is removed from 5, the first connection terminals 31 connected to the respective terminals of the IC sockets 23 are connected to the wiring conductors 34, as is apparent from what has been described with reference to FIG.
Since it is separated from the second connection terminal 32 connected to
The terminals of each IC socket 23 are independent for each socket. Therefore, as shown in FIG.
Test probe pins 4 arranged on the head of the high-grade tester 400 so as to correspond to the terminals of each IC socket.
At 01, a high-grade test can be performed by probing each terminal of each IC socket 23 independently of each terminal of another IC socket. Even in this high-grade test, a semiconductor element determined to have an abnormal access time or the like can be identified and stored by a computer attached to the system.

The above-mentioned usage mode is for the aging board of the embodiment described with reference to FIGS. 3 and 4, but the aging board of the embodiment described with reference to FIGS. 1 and 2 has substantially the same usage mode. It can be aged and tested.

The wiring conductors provided on the printed circuit board described above also include capacitors, resistors, diodes, etc. necessary for aging or testing.
Therefore, the wiring conductor provided on the printed circuit board 12 of the divided board 10 includes a resistor, a capacitor, a diode, etc. necessary for aging, as well as a capacitor, a resistance, etc. necessary for a test. Further, the wiring conductors provided on the aging board body 202 include capacitors, resistors, diodes, etc. necessary for aging, and the printed circuit board 22 of each divided board 20 has capacitors and resistors required for testing. Etc. are included.

Further, by assigning an identification number to each divided board, it becomes easy to classify the semiconductor elements after the test. By doing so, it is only necessary to insert the semiconductor device into the IC socket of the divided board, that is, without having to transfer each semiconductor device from the aging board to the separate test board. It can be performed through both steps of the test.

Outputs from the divided boards necessary for monitoring the output of each semiconductor device are output even during aging. The output terminals of each divided board have the same output terminal number, but a plurality of divided boards are connected. The outputs can be monitored by scanning sequentially. When this divided board is applied to a batch tester, there is no problem because only one output is output from the divided board. If it is desired to output two or more outputs from the same terminal for one divided board, it is necessary to set one so that only the output terminal number can be selected.

[0033]

According to the aging board in consideration of the test board of the present invention, the semiconductor element board can be attached to the semiconductor element socket of each divided board only by first inserting the semiconductor element to be aged and tested. Since it can be performed in a form that goes through aging and a high-grade test without needing to change hands and the like, the labor for that is very simple.

During a monitor aging that takes a relatively long time, a very large number of semiconductor elements can be mounted on a single aging board, and a relatively small division board can be used during a test requiring a relatively high accuracy. It is possible to perform aging of more elements within the same time because it can be mounted on the device, and more accurate tests can be performed without using a very expensive tester.

Since the burn-in monitor, the batch tester and the high-grade tester can be hung up without re-inserting the semiconductor element in the semiconductor element socket, necessary test items can be divided without much trouble. The burn-in monitor, the batch tester, and the high-grade tester can be effectively used, respectively, and as a whole, aging and testing can be performed very easily and inexpensively.

Semiconductor devices which have been found to be defective by the burn-in monitor can be removed from the test by the batch tester, and semiconductor devices which are not normal by the batch tester can be removed from the test by the high-grade tester. Therefore, it is possible to perform a test without waste as a whole, reduce the aging and test time as a whole, and reduce the cost.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing an aging board considering a test board as one embodiment of the present invention.

FIG. 2 is a schematic perspective view showing one of the divided boards constituting the aging board of FIG.

FIG. 3 is a schematic perspective view showing an aging board considering a test board as another embodiment of the present invention.

FIG. 4 is a schematic perspective view showing one of the divided boards constituting the aging board of FIG.

FIG. 5 is a connection diagram between a wiring conductor provided on a printed circuit board of a split board according to the present invention, each terminal of each IC socket, and a first connection terminal and a second connection terminal of a clip connector. It is a partial view for explaining a relation.

FIG. 6 is a schematic perspective view for explaining a case where a batch test is performed using the aging board shown in FIGS. 3 and 4.

FIG. 7 is a schematic perspective view for explaining a case where a high-grade test is performed using the aging board shown in FIGS. 3 and 4.

[Explanation of symbols]

 10 division board 11 reinforcing metal frame 12 printed circuit board 13 IC socket 14 male electric connector 15 female electric connector 16 clip connector 17 clip 20 division board 21 reinforcing metal frame 22 printed circuit board 23 IC socket 24 male electric connector 25 clip connector 26 clip 31 first connection terminal 32 second connection terminal 33 wiring conductor 34 wiring conductor 100 aging board 200 aging board 201 reinforcing metal frame 202 aging board body 300 batch tester 400 high-grade tester 401 probe pin

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Ueshima 3-13-12 Miyazaki, Miyamae-ku, Kawasaki-shi, Kanagawa Urban Heights 304

Claims (5)

[Claims] 1. A plurality of divided boards having a semiconductor element socket for connecting a semiconductor element to be aged and tested, a wiring conductor to each terminal of the semiconductor element socket, and an electric connector terminating the wiring conductor. Prepare,
The divided boards are mutually coupled through the electric connectors during aging, so that the wiring conductors can be interconnected in a state suitable for aging,
An aging board, wherein at the time of a test, the wiring conductors can be brought into a state suitable for the test by separating the respective electrical connectors from each other. 2. The aging board according to claim 1, wherein the plurality of divided boards form an aging board by cascade connection with each other through the electric connector. 3. The aging board according to claim 1, wherein the plurality of divided boards constitute an aging board by connecting the respective electrical connectors in parallel to a single aging board body. 4. The clip board according to claim 1, 2 or 3, wherein each of the divided boards comprises a clip means for selectively connecting and disconnecting each terminal of each semiconductor element socket and the wiring conductor. Aging board. 5. The aging board according to claim 1, 2 or 3 or 4, wherein an identification number is assigned to each of the divided boards.