JPH07131809A - Video signal processor - Google Patents

Abstract

PURPOSE:To prevent gradations from decreasing when a video signal is converted into digital data and processed. CONSTITUTION:Luminance data(YD) and carrier chrominance data(CD) are obtained from video signal data(Dig through a color separating circuit 12, a white balance control circuit 13, a color difference matrix circuit 14, and a balanced modulating circuit 15. The luminance data(YD) and carrier chrominance data(CD) are added to color synchronizing data(BD) to generate video data D2, which are inputted to a D/A converting circuit 18. An offset voltage is superposed on the analog output of the D/A converting circuit 18 in response to a composite synchronizing signal CS to insert the synchronizing signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device which handles color video signals as digital data.

[0002]

2. Description of the Related Art Generally, a color composite video signal is
It is obtained by subjecting color component signals (R, G, B) representing the three primary colors of red, green and blue to processing such as color difference matrix and parallel modulation. These processes are performed by a video signal processing device called a color encoder as shown in FIG.

The color separation circuit 1 distributes a video signal (Y1) in which color components of three primary colors (or a combination of complementary colors thereof) are repeated in a predetermined order, and separates the color component signals (R, G, respectively). B) is generated. The video signal (Y1) is obtained, for example, from the output of an image pickup device to which a mosaic color filter is attached, and one vertical scanning period and one horizontal scanning are performed by a predetermined number of horizontal scanning lines and pixel information, respectively. The period is configured. The white balance control circuit 2 uses color component signals (R, G, B)
By giving a unique gain to each of the above, the average level of each color component signal (R, G, B) is made uniform, and white can be reproduced on the reproduction screen for a white subject. The operation control of the white balance control circuit 2 is performed, for example, by feedback control such that an integrated value of color difference signals (RY, BY) described later approaches a predetermined value. The color difference matrix circuit 3 takes in three types of video signals (R, G, B) whose white balance has been adjusted, and sets each component in a predetermined ratio [R: 30%, G: 59].
%, B: 11%] to generate a luminance signal (Y),
Further, the luminance signal (Y) is subtracted from the video signal (R, B) to generate two types of color difference signals (RY, BY). The balanced modulation circuit 4 amplitude-modulates the two color subcarriers (SC1, SC2) having a phase difference of 90 ° with the color difference signals (RY, BY), and synthesizes both to generate a carrier color signal (C).
C) is generated.

On the other hand, the color synchronization signal generation circuit 5 generates a color synchronization signal (CB) called a color burst. This color synchronization signal (CB) is a color subcarrier (SC1, SC2)
The same cycle as the color subcarrier (SC1, SC2)
, And has a predetermined phase difference, and is generated every 8 to 9 cycles at a specific timing in the horizontal blanking period. The adder circuit 6 adds the carrier color signal (CC) and the luminance signal (Y) to the color sync signal (CB) and the composite sync signal (CS) supplied from a sync signal generation circuit 7 described later, and a predetermined television. A video signal (Y2) according to the John system is generated. Then, the synchronization signal generation circuit 7 generates various synchronization signals based on a reference clock having a frequency determined for each television system, and supplies these synchronization signals to each unit,
Synchronize each other's movements. At the same time, 2 from the reference clock
One color subcarrier (SC1, SC2) is generated and supplied to the balanced modulation circuit 4.

As shown in FIG. 6, the video signal (Y2) generated in the above manner is such that the video information for one line is continuous in each horizontal scanning period and serves as a boundary between the horizontal scanning periods. The color synchronization signal (CB) and the horizontal synchronization signal are inserted in the line erase period.

[0006]

In a recent television camera system or the like, a video signal processing adopting digital signal processing which is easy to adjust and has little deterioration of the video signal is used instead of the conventional video signal processing apparatus by analog signal processing. It is considered to use the device. In this case, analog / digital (A / D) conversion is performed at the input stage of the video signal (Y1), and color component signals (R, G,
B) and color difference signals (RY, BY) can be handled as digital data, and after predetermined processing is completed, digital / analog (D / A) conversion is performed to obtain a video signal (Y
2) is obtained.

By the way, a video signal (Y
2) is composed of a video component (including a luminance component and a color component) and a synchronization component (including scanning timing synchronization and color synchronization) having different possible voltage ranges. Therefore, when handling each signal as digital data,
Depending on the resolution of the conversion circuit, the gradation represented by the video component becomes insufficient. That is, since the video component and the synchronization component of the video signal (Y2) have voltages in different ranges, the minimum value (V) of the voltage that the video signal (Y2) can have.
_{Even if L} ) and the maximum value ( _VH ) are selected as the reference voltage of the D / A conversion circuit, the range substantially assigned to the video component is narrower than the range of the reference voltage.
Therefore, even if the D / A conversion circuit has a sufficient resolution, the gradation is reduced by the reduction of the allocation range for the video component.

Therefore, it is an object of the present invention to fully utilize the resolution of a D / A conversion circuit in a video signal processing device that handles a video signal as digital data and to secure a sufficient gradation of the video signal.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a signal processing for converting a video signal into digital data and performing a predetermined process. In the apparatus, means for obtaining video data corresponding to a video signal according to a predetermined format at a reference clock cycle, and color sync data corresponding to the color sync signal of the video signal as part of the video data in the horizontal blanking period. Means for adding, a digital-analog conversion circuit for converting the video data to which the color synchronization data is added into an analog value, and a constant analog output of the digital-analog conversion circuit in response to a horizontal synchronization signal of the video signal. And a means for superposing an offset voltage.

[0010]

According to the present invention, the color synchronizing data is replaced with a value within the range that the luminance data and the carrier color data can take, and the synchronizing signal is inserted by superposing the offset voltage on the output of the digital-analog conversion circuit. There is. Therefore, data that exceeds the range that the video component can take is not input to the digital-analog conversion circuit, and the range from the minimum value to the maximum value of the video component can correspond to the entire range of the reference voltage. It will be possible.

[0011]

1 is a block diagram showing the configuration of a video signal processing circuit according to the present invention. The A / D conversion circuit 11 converts the video signal (Y1) into digital data in 1-bit units,
The video signal data (D1) is output. Here, the video signal (Y1) is obtained from the output of the image sensor as in the case of FIG. 5, and, for example, the color components of the three primary colors are repeated in a predetermined order. The color separation circuit 12 includes an A / D conversion circuit 11
The video data (D1) given from the image data is taken in, sorted for each color component, and the independent color component data (R
1, G1, B1) is generated. The white balance control circuit 13 multiplies each of the color component data (R1, G1, B1) by unique gain data to obtain each color component data (R
1, G1, B1) to make the average level within a certain period uniform. The operation control of the white balance control circuit 13 is
For example, it is performed by feedback control so that an integrated value of color difference data (RY, BY) described later approaches a predetermined value. The color difference matrix circuit 14 uses three types of color component data (R2, G) whose white balance has been adjusted.
2, B2), and a predetermined coefficient [R2 ×
0.30, G2 × 0.59, B2 × 0.11] and then added together to generate luminance data (YD). At the same time, from the color component data (R2, B2) to the luminance data (Y
D) is subtracted for each of the two types of color difference data (RY,
BY) is generated. The balance modulation circuit 15 balance-modulates the two types of color difference data (RY, BY) to generate carrier color data (C
D) is generated. In the normal signal processing, this balanced modulation is performed by amplitude-modulating two types of color subcarriers whose phases are shifted by 90 ° with color difference signals (RY, BY), but is digitized. The color difference data (RY, BY) is processed by the following process. That is, in order to perform the same processing on the color difference data (RY) as the amplitude modulation of the color subcarrier, as shown in FIG. 2, the color difference data (RY RY) to (RY), 0,-(R
Sampling may be performed in the order of Y), 0, (RY) ... Similarly, for color difference data (BY), 9
Considering the phase difference of 0 °, the color difference data (BY) is converted into the color difference data (BY) by the sampling clock having a frequency four times that of the color subcarrier.
The sampling may be performed in the order of 0, (BY), 0,-(BY), 0 ... The carrier color data (CD) can be obtained by adding these sampling data. In the actual processing, the color difference data (RY, B
Y), (RY), (BY),-(RY),-
Carrier color data (CD) is generated by sequentially associating sampling data of (BY), (RY) ...

On the other hand, the color synchronization data generation circuit 16 generates color synchronization data (BD) corresponding to a color burst in synchronization with the carrier color data (CD). As shown in FIG. 3, the color synchronization data (BD) is a value obtained by sampling a color synchronization signal having a frequency of 3.58 MHz with a reference clock having a frequency of 14.32 MHz which is four times as high as the color synchronization signal corresponding to the NTSC system. , That is, data that is repeated in the order of 0, 1, 2, 1, 0, ... According to the reference clock. This color synchronization data (B
D) is represented by data of 0, 1, and 2, but as actual data, the minimum value of the luminance data (YD) and the carrier color data (CD) with respect to 0, that is, the black reference level is set. The data to be represented is associated, and 1 and 2 are associated with data of an appropriate number of bits according to the amplitude of the color synchronization signal. Further, the color synchronization data (BD) has a constant phase difference from the carrier color data (CD), and 32 to 36 data are generated at a specific timing in the horizontal blanking period. The adder circuit 17 uses the color synchronization data (BD)
Then, the luminance data (YD) and the carrier color data (CD) are added to the image data (D2). Then, the D / A conversion circuit 18 converts the video data (D2) into an analog value with reference to the two reference voltages ( _VL , _VH ).
Here, the reference voltages ( _VL , _VH ) referred to by the D / A conversion circuit 19 are set to the minimum and maximum values of the range that the video component can take. Further, the offset control circuit 19 inserts a synchronization signal by superimposing a constant offset voltage on the output of the D / A conversion circuit 18 in response to a composite synchronization signal CS given from a timing control circuit 20 described later. . That is, according to the horizontal synchronization signal, the offset voltage is superposed except for a part of the horizontal blanking period, so that the black reference level or less is obtained at a specific timing of the horizontal blanking period as shown in FIG. Will be inserted. In the vertical blanking period, since the horizontal synchronizing signal is inverted, the period in which the offset voltage is superimposed is reversed, and the offset voltage is superimposed only in the period representing the horizontal synchronizing signal. In this way, the output of the reference voltage (V _L ) or less is output to the D / A conversion circuit 1
If it is made on the output side of 8, all the voltages extracted from between the reference voltages ( _VL , _VH ) can be assigned to the carrier color data (CD) and the luminance data (YD) representing the video information. become.

The timing control circuit 20 generates various timing signals on the basis of a reference clock having a frequency determined for each television system, and supplies these timing signals to the respective parts, so that the color separation circuit 12 is controlled. The operations of the balance modulation circuit 15 and the color synchronization data generation circuit 16 are synchronized with each other. For example, the color synchronization signal data generation circuit 16 is configured to be supplied with a timing signal of a horizontal scanning period to generate predetermined data for each horizontal blanking period. The timing control circuit 21 also generates a composite sync signal CS that is a combination of horizontal and vertical scan sync signals, supplies the composite sync signal CS to the offset control circuit 19, and supplies the composite sync signal CS to the image sensor to set the scan timing of the image sensor. Synchronize with movement. This allows
The video signal Y1 input to the A / D conversion circuit 11 and the operation of each unit are synchronized, and signal processing is performed at appropriate timing.

[0014]

According to the present invention, the offset voltage is applied to the output of the D / A conversion circuit by using the color synchronization data replaced with the value between the minimum level and the intermediate level that the video component of the video signal can take. By superimposing and inserting the horizontal synchronizing signal and the vertical synchronizing signal, all of the voltages extracted from between the two reference voltages are assigned to the video component. Therefore, the gradation that can be represented by the D / A conversion circuit does not decrease, and the resolution of the D / A conversion circuit can be effectively utilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal processing circuit of the present invention.

FIG. 2 is a diagram illustrating an operation of a balanced modulation circuit.

FIG. 3 is a diagram illustrating an operation of a color synchronization data generation circuit.

FIG. 4 is a waveform diagram of a video signal output from the video signal processing device of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 6 is a waveform diagram of a video signal output from a conventional video signal processing device.

[Explanation of symbols]

 11 A / D conversion circuit 12 Color separation circuit 13 White balance control circuit 14 Color difference matrix circuit 15 Balance modulation circuit 16 Color synchronization data generation circuit 17 Adder circuit 18 D / A conversion circuit 19 Offset control circuit 20 Timing control circuit

Claims (2)

[Claims] 1. Means for obtaining video data corresponding to a video signal according to a predetermined format at a reference clock cycle,
Means for adding color synchronization data corresponding to the color synchronization signal of the video signal to a part of the video data in the horizontal blanking period,
A digital-analog conversion circuit that converts the video data to which the color synchronization data is added into an analog value, and a fixed offset voltage is superimposed on the analog output of the digital-analog conversion circuit in response to a horizontal synchronization signal of the video signal. And a video signal processing device. 2. A formula difference matrix circuit for generating luminance data and color difference data from color component data corresponding to each color component of a video signal, and a balance modulator circuit for balance-modulating two types of formula difference data to obtain carrier color data. A color synchronization data generation circuit that generates color synchronization data corresponding to the color synchronization signal of the video signal and replaced with data representing a value between the black reference level and the intermediate level of the video signal; An adder circuit for adding the above-mentioned carrier color data to the data and for adding the above-mentioned color synchronization data to a part of the horizontal blanking period to obtain video data, and a digital-analog conversion circuit for converting this video data into an analog value. And an offset control circuit that superimposes a constant offset voltage on the analog output of the digital-analog conversion circuit in response to the horizontal synchronizing signal of the video signal. A video signal processing device characterized by the above.