JPH07130848A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an exposure surface flatly by burying plug metal into a via hole without any clearance. CONSTITUTION:A lower-layer metal wiring 30 of Al is formed on an Si substrate body 10. Then, after an interlayer insulation film 40 is formed on it, a via hole is made Then, a via plug 51 is selectively deposited in the via hole by a chemical vapor growth method and then the via plug 51 is protruded upward from the open hole edge of the via hole. Then, an SOG film 35 which is harder than the plug metal is formed on the interlayer insulation film 40 thicker than the via plug which is protruded from the surface to reinforce the via plug. Then, the via plug which is protruded is eliminated along with the SOG film 35 by chemical mechanical polishing and then the surface is flattened. After that, an upper-layer metal wiring 60 is formed on it to form a multilayer wiring structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure, and more particularly to a technique for flattening an exposed surface in a multilayering process.

[0002]

2. Description of the Related Art In recent years, multi-layer wiring technology has been attracting attention as semiconductor elements are becoming higher in density and higher in integration. In this multilayer wiring structure, there is a technique using a buried via structure as a technique for connecting metal wirings in vertically adjacent layers. In this structure, a via hole is provided in the interlayer insulating film, a metal is embedded in the via hole to form a via plug, and the via plug connects the upper wiring layer and the lower wiring layer.

As a method of forming this via plug, selective CVD (Chemical Vapor) by chemical vapor deposition is used.
Deposition) method, Al or A in the via hole
A method of embedding an l-alloy has been proposed (JP-A-3-2).
91920).

[0004]

The problem to be solved by the invention is shown in FIG.
A state in which a via plug is formed in the via hole by the D method is shown. In this way, when the head of the via plug is located inside the via hole 101, the plug metal 102 may be formed in a mountain shape protruding upward, and in this case, the plug metal 102 A space 103 is formed between the bottom of the head and the inner wall of the via hole 101. In this way, with the void 103 formed,
When the upper wiring 105 is formed on the interlayer insulating layer 104, as shown in FIG. 13B, the coverage of the upper wiring 105 is reduced in the vicinity of the void 103, and the EM (electromigration) resistance is deteriorated. There was a point.

Further, in order to make up for such a defect, FIG.
As shown in (a), when the plug metal 102 is deposited so as to fill the open end of the via hole 101, when the upper layer metal 105 is deposited thereon, the interlayer insulating layer 104 is formed.
The thickness of the upper upper layer metal 105 has a drawback that only this portion is formed thick.

The present invention has been made to solve the above problems, and its purpose is to provide a multi-layering process,
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a plug metal is embedded in a via hole without a gap and the exposed surface of the plug metal is formed flat while the via metal is embedded in the via hole.

[0007]

In a first method for manufacturing a semiconductor device according to the present invention, first, as a first step, a first thin film containing Al is formed on a substrate and the first thin film is patterned. Thus, the lower metal wiring is formed. Next, as a second step, an interlayer insulating film is formed on the lower metal wiring to insulate the wiring from the upper wiring formed on the upper layer. Next, as a third step, a via hole is formed in this interlayer insulating film, and the lower layer metal wiring is exposed at the bottom of this via hole. Next, as a fourth step, a plug metal containing Al is selectively deposited in the via hole by a chemical vapor deposition method to project the plug metal upward from the open end of the via hole. Next, as a fifth step, an insulating protective film (eg, SiO ₂ , SiN, etc.) thicker than the plug metal protruding from the open end of the via hole and harder than this plug metal is formed on the interlayer insulating film. Form. On this occasion,
When a void is formed on the inner wall of the via hole, the SOG with excellent embedding property can be filled also in the void.
It is desirable to deposit using a film method or a CVD method using TEOS as a raw material. Then, in a sixth step, the surface of the protective film is subjected to chemical mechanical polishing (CMP) to remove the plug metal protruding from the open end of the via hole together with the protective film to flatten the exposed surface. . If the plug metal is not sufficiently embedded in the via hole, a protective film is filled in the gap between the inner wall of the via hole and the via plug so that almost all of the protective film is removed. It is desirable that the exposed surface of the interlayer insulating film is flattened by removing even the upper layer portion of the insulating film. Then, as a seventh step, a second thin film containing Al to be upper wiring is formed on the exposed flattened surface.

In a second method for manufacturing a semiconductor device according to the present invention, first, as a first step, a first thin film containing Al is formed on a substrate, and the first thin film is patterned to form a lower layer. Form metal wiring. Next, as a second step, an interlayer insulating film is formed on the lower metal wiring to insulate the wiring from the upper wiring formed on the upper layer. Next, as a third step, a via hole is formed in the interlayer insulating film, and the lower layer metal wiring is exposed at the bottom of the via hole. Next, as a fourth step, a plug metal containing Al is selectively deposited in the via hole by a chemical vapor deposition method to fill the via metal with no gap.
At this time, it is desirable to sufficiently deposit the plaque metal so that the plug metal rises from the surface of the interlayer insulating film. Next, in a fifth step, the plug metal protruding from the open end of the via hole is electrolytically polished to remove the protruding plug metal and flatten the exposed surface. Then, as a sixth step, a second thin film containing Al to be an upper wiring is formed on the exposed surface after the fifth step.

The electropolishing is to electrolyze a sample surface in an electrolytic solution with the sample surface as an anode and remove the convex portions on the surface to obtain a smooth surface. For example, a substrate or a plug part is used as an anode. A method of electrolyzing in a mixed aqueous solution of acetic anhydride and perchloric acid to preferentially remove the plug metal protruding from the via hole by electrolysis is cited.

[0010]

In the first method of manufacturing a semiconductor device, the Al-containing plug metal deposited in the via hole is softer than the plug metal such as tungsten, so if CMP is performed as it is, the plug metal is torn off. The shape embedded in the via hole cannot be left. Therefore, in the fourth step, the head of the plug metal is deposited so as to project from the open end of the via hole, and then in the fifth step, SiO that is harder than the plug metal is used so that the protruding plug metal is hidden. ₂ Cover with a protective film such as a film. As a result, this protruding plug metal is, so to speak, reinforced. Then, by performing such pretreatment, it becomes possible to carry out CMP on this surface.

In the second semiconductor device manufacturing method,
The plug metal is deposited sufficiently so as to rise from the surface of the interlayer insulating film so that no void is formed on the inner wall of the via hole. Then, when this surface is subjected to electrolytic polishing, only the plug metal protruding from the surface of the interlayer insulating film is removed.
In electropolishing, the dissolved metal reacts with the oxidizing agent of the electrolytic solution to form a thin electrogenerated film on the sample surface, but in the convex portion of the sample, the electric current flows strongly because the electrogenerated film is thin. This is because it progresses faster than the part.

[0012]

EXAMPLE 1 A method for manufacturing a semiconductor device according to Example 1 will be described below with reference to the flow chart of FIG. 1 and the process diagrams of FIGS.

First, a base insulating film 20 is formed on the surface of the Si substrate body 10, and then an Al alloy containing 0.5 wt% of Cu is formed on the base insulating film 20 by sputtering.
The Al alloy film 31 is formed by depositing it to a film thickness of 00 nm (FIG. 2A, step 101).

Next, the Al alloy film 31 is processed into a predetermined pattern to form the lower layer metal wiring 30 (step 10).
2). The wiring pattern is formed by forming a resist pattern using an exposure device and then performing RIE using a chlorine-based gas.
(Reactive ion etching).

Next, an interlayer insulating film 40 is formed on the base insulating film 20 on which the lower layer metal wiring 30 is formed (FIG. 2).
(B), step 103). The interlayer insulating film 40 is formed by depositing a SiO ₂ film by a plasma CVD method, forming an SOG film on the SiO ₂ film, and then utilizing etchback.

Next, after forming a photoresist film on the interlayer insulating film 40, the via holes 50 having a diameter of 0.8 μm are formed by the RIE using a fluorine-based gas.
At a predetermined position (FIG. 2C, step 10).
4).

Next, the alumina film 70 existing on the surface of the lower metal wiring 30 exposed at the bottom of the via hole 50 is removed by plasma etching using a chlorine-based gas (FIG. 2 (d), step 105). .

Next, after transferring to the reaction vessel without exposing to the atmosphere, DMAH and hydrogen are supplied into this reaction vessel, and the via hole 5 is formed by the CVD method using this mixed gas as a raw material.
Al is selectively deposited only on 0. Thereby, the via plug 51 is formed (FIG. 2E, step 10).
6).

Next, the SOG film 35 is applied on the interlayer insulating film 40 to a thickness such that the most protruding surface of the interlayer insulating film 40 or the via plug 51 is hidden, and the SOG film 35 is heat-cured (if necessary). Cure) (FIG. 3 (f)). At this time, a nearly complete SiO ₂ film can be obtained by curing at a temperature of 400 ° C. or higher for 30 minutes or more, but for example, it is only cured at 300 ° C. for 2 minutes to evaporate the solvent. However, it sufficiently serves as a protective film.

Next, by chemical mechanical polishing (CMP), the head of the via plug 51 protruding from the surface of the interlayer insulating film 40 together with the SOG film 35 is polished and removed to flatten the exposed surface (FIG. 3 (g), step 107). At this time, as the polishing liquid, silica sol having a pH of 10 is used, and polishing is performed using a polishing pad at a pressure of 120 kg / cm ² . In addition, FIG. 13 (a) described above.
When the head of the via plug is located in the via hole and a gap is formed between the outer edge portion of the via plug and the inner wall of the via hole as shown in FIG.
The upper layer portion of the interlayer insulating film 40 is also polished and removed, as shown in FIG.
The exposed surface is flattened as shown in FIG.

Next, the interlayer insulating film 4 thus flattened
In the same manner as the method of forming the lower layer metal wiring 30 described above on the surface of the aluminum alloy, the Al alloy 4 was formed by sputtering.
The Al alloy film 61 is formed by depositing the film having a thickness of 00 to 1000 nm (FIG. 3H). After this, the Al alloy film 6
1 is processed into a predetermined pattern to form the upper layer metal wiring 60. (FIG. 3 (i), step 108). The Al alloy used in this case may be an alloy of the same component or an alloy of different components used for the upper layer metal wiring 60 and the lower layer metal wiring 30.

Incidentally, structures necessary for a semiconductor device such as a diffusion layer and a gate electrode are formed in and on the surface of the Si substrate body 10. At the required position of the base insulating film 20,
There is a contact hole, and a contact structure for connecting the lower metal wiring 30 and the diffusion layer or the gate electrode or other structure is formed.

<Embodiment 2> Another embodiment will be described with reference to the flowchart of FIG. 4 and the process diagrams of FIGS.

First, a base insulating film 20 is formed on the surface of the Si substrate body 10, and then an Al alloy containing 0.5% by weight of Cu is formed on the base insulating film 20 by sputtering.
The Al alloy film 31 is formed by depositing it to a film thickness of 00 nm (FIG. 5A, step 201).

Next, the Al alloy film 31 is processed into a predetermined pattern to form the lower layer metal wiring 30 (step 20).
2). The wiring pattern is formed by forming a resist pattern using an exposure device and then performing RIE using a chlorine-based gas.
(Reactive ion etching).

Next, an interlayer insulating film 40 is formed on the base insulating film 20 on which the lower layer metal wiring 30 is formed (FIG. 5).
(B), step 203). The interlayer insulating film 40 is formed by depositing a SiO ₂ film by a plasma CVD method, forming an SOG film on the SiO ₂ film, and then utilizing etchback.

Next, after forming a photoresist film on the interlayer insulating film 40, the via holes 50 having a diameter of 0.8 μm are formed in the interlayer insulating film 40 by RIE using a fluorine-based gas.
At a predetermined position (FIG. 5C, step 20).
4).

Next, the alumina film 70 existing on the surface of the lower metal wiring 30 exposed at the bottom of the via hole 50 is removed by plasma etching using chlorine-based gas (FIG. 5 (d), step 205). .

Next, after transferring to the reaction vessel without exposing to the atmosphere, DMAH and hydrogen are supplied into this reaction vessel, and the via hole 5 is formed by the CVD method using this mixed gas as a raw material.
Al is selectively deposited only on 0. This forms the via plug 51 (FIG. 5E, step 20).
6).

Next, ethanol is applied to the surface of the substrate having the via plug 51 formed thereon by a spin coating method and dried. After drying, tetraethoxysilane (TE
OS) and O ₃ as raw materials at room temperature CVD (O ₃ -TE
The SiO ₂ film 36 is formed on this surface by the OS-CVD method).
Are deposited (FIG. 6 (f)). The formed SiO ₂ film (O
_{The 3-} TEOS-CVD film) has an excellent embedding property and also fills a delicate gap between the inner wall of the via hole and the deposited via plug. This SiO ₂ film has a property of being particularly easily deposited on the metallic surface, and as a result, it is deposited well in the gap between the inner wall of the via hole and the via plug, and at the parts other than the plug portion. Even if the film thickness is reduced, the plug head can be completely covered. Therefore, the protruding portion of the plug is fixed with a thin SiO ₂ film as compared with the first embodiment, and damage given to the plug in the subsequent CMP process can be prevented and the reliability of the plug can be improved. it can.

Thereafter, the head portion of the via plug protruding from the surface of the interlayer insulating film 40 is covered with SiO ₂ (O ₃ -TEOS-) by a chemical mechanical polishing (CMP) method.
The CVD film 36 is polished and removed to be planarized (FIG. 6G, step 207). At this time, as the polishing liquid, silica sol having a pH of 11 is used and polishing is performed using a polishing pad having a pressure of 135 kg / cm ² . In this case, the pressure in the raised portion of the plug portion locally increases initially, and only that portion advances the polishing at an extremely high speed. After the raised portion is polished and the entire surface is substantially flattened, the polishing proceeds at a constant rate over the entire surface. However, if the thickness of the SiO ₂ film other than the plug portion is reduced, By comparison, CMP can be completed in a short time.

Next, the interlayer insulating film 4 thus flattened
In the same manner as the method of forming the lower layer metal wiring 30 described above on the surface of the aluminum alloy, the Al alloy 4 was formed by sputtering.
Al alloy film 6 deposited to a film thickness of 00 to 1000 nm
1 is formed (FIG. 6 (h)). After this, the Al alloy film 61
Is processed into a predetermined pattern to form the upper metal wiring 60 (FIG. 6 (i), step 208). The Al alloy used in this case may be an alloy of the same component or an alloy of different components used for the upper layer metal wiring 60 and the lower layer metal wiring 30.

<Embodiment 3> Another embodiment will be described with reference to the flowchart of FIG. 7 and the process drawings of FIGS.

First, a base insulating film 20 is formed on the surface of the Si substrate body 10, and then an Al alloy containing 0.5 wt% of Cu is formed on the base insulating film 20 by sputtering.
The Al alloy film 31 is formed by depositing it to a film thickness of 00 nm (FIG. 8A, step 301).

Next, the Al alloy film 31 is processed into a predetermined pattern to form the lower layer metal wiring 30 (step 30).
2). The wiring pattern is formed by forming a resist pattern using an exposure device and then performing RIE using a chlorine-based gas.
(Reactive ion etching).

Next, an interlayer insulating film 40 is formed on the base insulating film 20 on which the lower layer metal wiring 30 is formed (FIG. 8).
(B), step 303). The interlayer insulating film 40 is formed by depositing a SiO ₂ film by a plasma CVD method, forming an SOG film on the SiO ₂ film, and then utilizing etchback.

Next, after forming a photoresist film on the interlayer insulating film 40, the via holes 50 having a diameter of 0.8 μm are formed by the RIE using a fluorine-based gas.
At a predetermined position (FIG. 8C, step 30).
4).

Next, the alumina film 70 existing on the surface of the lower metal wiring 30 exposed at the bottom of the via hole 50 is removed by plasma etching using a chlorine-based gas (FIG. 8 (d), step 305).

Next, after transferring to the reaction vessel without exposing to the atmosphere, DMAH and hydrogen are supplied into the reaction vessel, and the via hole 5 is formed by the CVD method using this mixed gas as a raw material.
Al is selectively deposited only on 0. Thereby, the via plug 51 is formed (FIG. 9E, step 30).
6). At this time, the inner wall of the via hole 50 and the via plug 51
Sufficiently deposited so that no gap is formed between them.

Next, the substrate on which the via plug is formed is replaced with J
Electrolyte composition similar to acquet method (60% perchloric acid 2
Electrolytic polishing of the plug metal (Al) protruding from the open end of the via hole 50 under 20 cc and 780 cc of 90% non-hydrogenic acid under the electrolysis conditions of current density of 10 A / dm ² , bath temperature of 30 ° C. and electrolysis time of 3 minutes. Remove by. As a result, the surface of the interlayer insulating film 40 is flattened (FIG. 9).
(F), step 307).

Next, the interlayer insulating film 4 thus flattened
In the same manner as the method of forming the lower layer metal wiring 30 described above on the surface of the aluminum alloy, the Al alloy 4 was formed by sputtering.
Al alloy film 6 deposited to a film thickness of 00 to 1000 nm
1 is formed (FIG. 9 (g)). After this, the Al alloy film 61
Is processed into a predetermined pattern to form the upper layer metal wiring 60. (FIG. 6 (h), step 308). The Al alloy used in this case may be an alloy of the same component or an alloy of different components used for the upper layer metal wiring 60 and the lower layer metal wiring 30.

<Embodiment 4> Another embodiment will be described with reference to the flowchart of FIG. 10 and the process drawings of FIGS.

First, the base insulating film 20 is formed on the surface of the Si substrate body 10, and then an Al alloy containing 0.5 wt% of Cu is formed on the base insulating film 20 by sputtering.
The Al alloy film 31 is formed by depositing it to a film thickness of 00 nm (FIG. 11A, step 401).

Next, the Al alloy film 31 is processed into a predetermined pattern to form the lower metal wiring 30 (see FIG. 11B, step 402). The wiring pattern is formed by RIE (reactive ion etching) using a chlorine-based gas after forming a resist pattern using an exposure device.

Next, an interlayer insulating film 40 is formed on the base insulating film 20 on which the lower layer metal wiring 30 is formed (FIG. 11).
(B), step 403). The interlayer insulating film 40 is formed by depositing a SiO ₂ film by a plasma CVD method, forming an SOG film on the SiO ₂ film, and then utilizing etchback.

Next, after forming a photoresist film on the interlayer insulating film 40, a via hole is formed at a predetermined position of the interlayer insulating film 40 by RIE using a fluorine-based gas (FIG. 11C). ), Step 404). At this time,
Via hole A with different diameter and depth (0.5μm diameter x 0.8μ
m depth), B (0.8 μm diameter × 1.8 μm depth) and C
(0.5 μm diameter × 1.5 μm depth) was formed.

Next, the alumina film 70 existing on the surface of the lower metal wiring 30 exposed at the bottom of the via holes A to C is removed by plasma etching using a chlorine-based gas (FIG. 11D, step). 405).

Next, after transferring to the reaction container without exposing to the atmosphere, DMAH and hydrogen are supplied into this reaction container, and the via hole A is formed by the CVD method using this mixed gas as a raw material.
Al is selectively deposited only on C. by this,
The via plug 51 is formed (FIG. 12E, step 406). As for the degree of deposition, since there are via holes with different diameters and depths, for the deepest via B,
Al was deposited until the area ratio of the via plug to the via hole was 0.8 or more when the cross section on the uppermost surface of the via hole was considered. Therefore, other via holes A
In C and C, Al was projected and overflowed.

Next, the substrate on which the via plug is formed is Ja
Electrolyte composition similar to cquet method (60% perchloric acid 22
In 0 cc, 90% acetic anhydride 780 cc), Al protruding from the via hole is removed by electropolishing under a current density of 10 A / dm2, a bath temperature of 30 ° C., and an electrolysis time of 3 minutes to perform flattening (FIG. 12). (F), step 40
7). Since the electrolysis is preferentially carried out from the protruding portion, the protruding and overflowing Al in the via holes A and C is first removed, and the via hole B is hardly electrolyzed.
The whole is flattened. The method of flattening the substrate surface is not limited to such electrolytic polishing, and the method of Example 1 or 2
As shown in, the SOG film and 0 ₃ -TEOS-CVD
The CMP method may be carried out after fixing the protruding Al while filling the gap between the inner wall of the via hole and the plug with the film.

Next, the interlayer insulating film 4 thus flattened
An Al alloy was formed on the surface of No. 0 by sputtering in the same manner as the method of forming the lower metal wiring 30 described above.
Al alloy film 6 deposited to a film thickness of 00 to 1000 nm
1 is formed (FIG. 12 (g), step 408).

Next, the Al alloy film 61 is processed into a predetermined pattern to form the upper metal wiring 60 to form a multi-layer wiring structure (FIG. 12 (h), step 408). The Al alloy used at this time may be an alloy of the same component as that used for the upper layer metal wiring 60 and the alloy used for the lower layer metal wiring 30, or may be an alloy of different components.

In each of the examples, as the insulating protective film harder than the plug metal, SiO by the SOG method is used.
₂ film, 0 ₃ is exemplified film SiO ₂ film by -TEOS-CVD method, the addition to, may also be used such as SiN film.

[0053]

As described above, according to the first semiconductor device manufacturing method of the present invention, the plug metal is deposited so as to project upward from the open end of the via hole, and the projecting plaque is formed. Since the metal is covered with the hard protective film such as the SOG film, it is possible to apply CMP to the relatively soft plug metal containing Al to flatten the surface.

Further, even if the plug metal is not sufficiently embedded in the via hole, the protective film is also filled in the gap between the inner wall of the via hole and the via plug.
By using P, the exposed surface can be flattened by removing the upper layer portion of the interlayer insulating film together with the protective film.

Further, according to the second method for manufacturing a semiconductor device of the present invention, the plug metal is deposited in the via hole without leaving a gap so that the plug metal rises from the surface of the interlayer insulating film, and thereafter, Since the surface of the interlayer insulating film is electrolytically polished, only the plug metal protruding from the surface of the interlayer insulating film can be removed, and the exposed surface can be flattened.

[Brief description of drawings]

FIG. 1 is a flowchart showing a manufacturing process according to a first embodiment.

2A to 2E are process diagrams sequentially showing each manufacturing process according to the first embodiment.

3 (f) to (i) are process diagrams sequentially showing the manufacturing process following FIG.

FIG. 4 is a flowchart showing a manufacturing process according to the second embodiment.

5A to 5E are process diagrams sequentially showing each manufacturing process according to the first embodiment.

6 (f) to (i) are process diagrams sequentially showing the manufacturing process following FIG.

FIG. 7 is a flowchart showing a manufacturing process according to the third embodiment.

8A to 8D are process diagrams sequentially showing each manufacturing process according to the third embodiment.

9E to 9H are process diagrams sequentially showing the manufacturing process subsequent to FIG.

FIG. 10 is a flowchart showing a manufacturing process according to the fourth embodiment.

11A to 11D are process diagrams sequentially showing each manufacturing process according to the fourth embodiment.

12 (e) to (h) are process drawings sequentially showing the manufacturing process following FIG.

13A and 13B are process diagrams showing a conventional manufacturing method.

14A and 14B are process diagrams showing a conventional manufacturing method.

[Explanation of symbols]

10 ... Si substrate main body, 20 ... Base insulating film, 30 ... Lower metal wiring, 35 ... SOG film (protective film), 36 ... SiO
₂ (protective film), 40 ... interlayer insulating film, 50 ... via hole, 5
1 ... Via plug, 60 ... Upper layer metal wiring

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Eiichi Kondo 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Corporation Technical Research Headquarters (72) Inventor Hiroshi Yamamoto 1 Kawasaki-cho, Chuo-ku, Chiba-shi Address Kawasaki Steel Co., Ltd. Technical Research Division (72) Inventor Yoyo Ota 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Co., Ltd. Technical Research Division

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising forming a first thin film containing Al on a substrate, and patterning the first thin film to form a lower metal wiring. 1 step, a second step of forming an interlayer insulating film on the lower metal wiring, which insulates the wiring and an upper wiring formed in the upper layer, and a via hole is formed in the interlayer insulating film. A third step of exposing the lower metal wiring to the bottom of the hole, and a selective deposition of a plug metal containing Al in the via hole by a chemical vapor deposition method. A fourth step of projecting at least a portion of the plug metal upward, and an insulating protective film, which is harder than the plug metal, on the interlayer insulating film, the plug projecting from an open end of the via hole. Than metal A fifth step of forming a thick film, and chemical mechanical polishing of the surface of the protective film removes the plug metal protruding from the open end of the via hole together with the protective film to flatten the exposed surface. A sixth step, and forming the upper layer wiring on the flattened exposed surface A
a seventh step of forming a second thin film containing l, and a method of manufacturing a semiconductor device. 2. The sixth step is characterized in that the exposed surface of the interlayer insulating film is planarized by removing from the protective film to the upper layer portion of the interlayer insulating film by chemical mechanical polishing. The method for manufacturing a semiconductor device according to claim 1. 3. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising forming a first thin film containing Al on a substrate, and patterning the first thin film to form a lower metal wiring. 1 step, a second step of forming an interlayer insulating film on the lower metal wiring, which insulates the wiring and an upper wiring formed in the upper layer, and a via hole is formed in the interlayer insulating film. A third step of exposing the lower metal wiring to the bottom of the hole, and a chemical vapor deposition method for selectively depositing a plug metal containing Al in the via hole to form a plug without a gap in the via hole. A fourth step of filling the metal, and electrolytically polishing the plug metal protruding from the open end of the via hole to remove the protruding plug metal and remove the exposed surface of the interlayer insulating film. flat Fifth step and, on the exposed surface through the fifth step, the method of manufacturing a semiconductor device characterized by having a sixth step of forming a second thin film containing Al serving as the upper layer wiring of.