JPH07130748A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To stabilize mounting performance for mounting parts in a semiconduc tor device where a solder bump is formed on the surface of an optical semicon ductor element and its production method. CONSTITUTION:An Au metal layer 12 is, for example, formed on the surface of a semiconductor layer 11 where an optical semiconductor element is fabricated. Then a SiNx insulation film 14 patterned correspondingly to an electrode formation area 13 is formed thereon by deposition. After an electrode 22 consisting of a Ti sticking metal layer 15, a Pt barrier layer 16 and an Au contact metal layer 17 is formed in the area 13, an Sn core metal 18 which is easily oxidized due to its strong ionization tendency is formed as a core and an Au top layer 19 which is hardly oxidized due to its weak ionization tendency is formed through an electric-field plating. Thus, such a semiconductor device is provided with a solder bump 20 on the electrode 22 which is made by an Au and Sn eutectic solder with multilayered construction and in which an oxide film is hardly formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which solder bumps are provided on electrodes of a semiconductor element and a method for manufacturing the same, and is particularly used for an optical semiconductor element such as a photodiode.

[0002]

2. Description of the Related Art Conventionally, in an optical semiconductor element such as a photodiode, a solder bump has been formed on the surface of the element due to the flip chip formation. In particular, as the solder bumps of InP / InGaAs photodiodes, avalanche photodiodes, or laser diodes for optical fiber communication, which have rapidly increased in demand in recent years, for example, from the viewpoint of environment resistance, heat resistance, and reliability, AuSn eutectic solder having a high melting point is used.

FIG. 3 shows an example of a solder bump using a conventional AuSn eutectic solder. That is, the insulating film 4 in which the solder bump forming region 3 is patterned according to the metal electrode 2 is formed on the surface of the optical semiconductor element 1, and Au is formed so that the solder bump forming region 3 has a eutectic composition. After depositing Sn, the ball-shaped solder bumps 5 are formed by heating to the eutectic temperature.

In the case of the solder bump 5 made of an alloy of Au and Sn, an oxide film is formed on the surface of the bump 5. This is because Sn in the surface layer is oxidized because Sn has a large ionization tendency.

The oxide film formed on the solder bump 5 cannot be removed only by melting, and it is necessary to scrub and remove the chip when mounting the chip on the mounted component. However, when the chip is scrubbed during chip mounting, the area of the molten solder metal from which the oxide film has been removed spreads over the metal surface on the mounted component increases, so there is a problem in that the mounting position accuracy decreases.

However, if the scrubbing is not performed, the oxide film on the surface of the solder bump 5 cannot be fixed because it has no wettability with respect to the metal surface on the mounted component, resulting in a marked decrease in mount strength or a chip failure. There was a drawback that the self-alignment effect peculiar to the mount could not be expected.

[0007]

As described above, conventionally, in the case of a solder bump made of an alloy of Au and Sn, the wettability is lost because an oxide film is formed on the surface of the bump. There are problems in reliability and performance, such as a decrease in strength, a good self-alignment effect not being obtained, and an attempt to remove the oxide film by scrubbing the chip lowers the mount position accuracy.

Therefore, an object of the present invention is to provide a semiconductor device capable of preventing the formation of an oxide film on the surface of a solder bump and improving reliability and performance, and a method of manufacturing the same.

[0009]

To achieve the above object, in a semiconductor device according to the present invention, a solder bump is provided on an electrode of a semiconductor element, wherein the solder bump has an ionization tendency. It is composed of a plurality of different metal layers, and a metal layer having the smallest ionization tendency is formed on the outermost surface side of the bump.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming an insulating film on the surface of the semiconductor element, and the resist layer patterned on the insulating film corresponding to the solder bump formation region And a step of removing the insulating film exposed in the solder bump formation region of the resist layer, and the surface of the semiconductor element corresponding to the solder bump formation region of the insulating film removed,
A step of forming a first metal layer thicker than the resist layer, and forming a second metal layer having an ionization tendency smaller than that of the first metal layer around the first metal layer as a nucleus It consists of a process.

[0011]

According to the present invention, since the solder bumps having good wettability can be obtained by the above-mentioned means, it is possible to perform stable mounting on the mounted component without requiring scrubbing operation. It is a thing.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a semiconductor device according to the present invention. For example, an Au metal layer 12 for plating contact is formed on the surface of a semiconductor layer 11 in which an optical semiconductor element is formed, and an insulating film 14 made of SiNx or the like patterned on the electrode forming region 13 is formed thereon. Have been deposited.

In the electrode forming region 13, the semiconductor layer 11 is formed.
From the surface side of the Ti adhesive metal layer 15, Pt barrier layer 1
6 and Au contact metal layer 17 are sequentially formed. Then, on the Au contact metal layer 17,
A substantially mushroom-shaped Sn core metal 18 having a thicker hemispherical shape on the tip side, and an Au outermost layer 19 formed so as to cover the Sn core metal 18, thereby forming a solder bump made of a Au / Sn eutectic solder having a multilayer structure. 20 is provided.

Next, a method of manufacturing the semiconductor device having the above structure will be described. FIG. 2 shows a solder bump 2 having a multilayer structure.
7 shows a manufacturing process of a semiconductor device in which 0 is provided.

First, in order to allow the same current to flow in each patterning region at the time of patterning plating on the surface of the semiconductor layer 11, for example, 0.5 is formed by a vacuum deposition method.
An Au metal layer 12 for plating contact having a thickness of nm is formed ((a) in the same figure).

Next, after depositing, for example, a 0.2 nm thick SiNx insulating film 14 on the Au metal layer 12 for plating contact, a resist layer 21 is uniformly applied on the SiNx insulating film 14. It

Then, an electrode forming region 13 having a diameter of about 50 μm is patterned on the resist layer 21, and the SiNx insulating film 14 exposed on the patterned electrode forming region 13 is removed by etching (the same). Figure (b)).

Then, on the Au metal layer 12 for plating contact in the electrode forming region 13, a Ti adhesion metal layer 15, a Pt barrier layer 16, and a Ti adhesion metal layer 16 are formed by, for example, a vacuum deposition method.
And an Au contact metal layer 17 are sequentially formed.

Then, the unnecessary layers in the peripheral portion are lifted off, so that the electrodes 22 are formed in the electrode forming region 13.
Are formed ((c) in the figure). Then, a resist layer 23 having a thickness of about 5 μm is formed in other regions except the electrode forming region 13.
Is applied.

Then, Sn of about 10 μm thickness is formed on the Au contact metal layer 17 by, for example, an electrolytic plating method.
The core metal 18 is formed ((d) in the figure). In this case, the Sn core metal 18 grows in a cylindrical shape up to the thickness of the resist layer 23 (about 5 μm), and the plating thickness is 5 μm.
When it exceeds the above, it jumps out from the resist layer 23 and grows in the lateral direction, and finally is formed into a substantially mushroom shape having a thicker hemispherical shape on the tip side.

Then, after the resist layer 23 is removed, an Au outermost layer 19 having a thickness of about 30 μm is formed around the Sn core metal 18 by, for example, an electrolytic plating method (FIG. 7E).

In this case, the Au outermost layer 19 is formed as the outermost layer of the solder bump 20 by using the Sn core metal 18 as a core and growing so as to cover it. In addition,
In this embodiment, the weight ratio of the Sn core metal 18 and the Au outermost layer 19 forming the solder bump 20 is set to a eutectic composition, for example, 20% to 80%.

As described above, when the solder bump 20 is formed, the Sn core metal 18 having a large ionization tendency is used as a core, and the periphery thereof is formed of Au having a smaller ionization tendency.
The wrapping with the outermost layer 19 can prevent the oxide film from being formed on the surface of the solder bump 20.

Thus, the solder bump 20 having no oxide film on the bump surface is formed on the electrode 22 on the surface of the semiconductor layer 11. When the semiconductor device is mounted on a mounting component (not shown), the solder bump 20 is heated to a eutectic temperature while the solder bump 20 is in contact with the metal surface of the mounting component. To be done.

As a result, the alloy reaction rapidly progresses from the interface between the Sn core metal 18 and the Au outermost layer 19 in the solder bump 20, and the solder bump 20 is instantly melted. In this case, the solder bump 20 having no oxide film on the bump surface is in direct contact with the metal surface of the mounted component, so that the solder bump 20 has excellent wettability and can be firmly fixed, and a good self-alignment effect can be obtained.

Incidentally, when the mount strength was measured by applying a force from the side surface of the mounted semiconductor device, the peeling limit was 0.5 Kgf in the conventional device, whereas it was improved to 2 Kgf in the device of this embodiment. .

Further, since the scrubbing operation for removing the oxide film on the bump surface is unnecessary, the mount position accuracy of the prior art is improved to ± 5 μm in comparison with the conventional mount position accuracy of ± 20 μm. It has become possible.

As described above, solder bumps having good wettability are obtained. That is, solder bumps
A multi-layer structure including an n-core metal and an Au outermost layer is used, and the entire circumference of Sn, which has a high ionization tendency and is easily oxidized, is covered with Au, which has a low ionization tendency and is hard to be oxidized. This makes it possible to prevent an oxide film from being formed on the bump surface and impairing the wettability of the solder bump, so that it is possible to perform stable mounting on the mounted component without requiring scrubbing. It will be possible. Therefore, it is possible to firmly mount on the mounted component, a good self-alignment effect is obtained, and the scrubbing operation for removing the oxide film is not required, so that the mounting position accuracy can be improved.

In the above embodiments, the optical semiconductor element has been described as an example, but the present invention is not limited to this, and the present invention can be applied to various semiconductor devices to be flip-chiped, for example. Further, the solder bump is not limited to the two-layer structure made of Sn and Au, and may be made of, for example, another metal layer, or may have a multi-layer structure of two or more layers. Of course, various modifications can be made without departing from the scope of the invention.

[0030]

As described above in detail, according to the present invention, it is possible to prevent the formation of an oxide film on the surface of a solder bump, and to improve the reliability and performance of a semiconductor device and a method of manufacturing the same. Can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view schematically showing the manufacturing process of the semiconductor device.

FIG. 3 is a cross-sectional view of a semiconductor device shown for explaining a conventional technique and its problems.

[Explanation of symbols]

11 ... Semiconductor layer, 12 ... Au metal layer for plating contact, 13 ... Electrode formation region, 14 ... Insulating film, 15 ... Ti adhesion metal layer, 16 ... Pt barrier layer, 17 ... Au contact metal layer, 18 ... Sn core metal, 19 ... Au outermost layer, 2
0 ... Solder bumps 21, 23 ... Resist layer, 22 ... Electrodes.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 7630-4M 31/02 B

Claims (5)

[Claims] 1. A semiconductor device in which a solder bump is provided on an electrode of a semiconductor element, wherein the solder bump is composed of a plurality of metal layers having different ionization tendencies, and a metal layer having the smallest ionization tendency on the outermost surface side of the bump. A semiconductor device comprising: 2. Each metal layer constituting the solder bumps,
The semiconductor device according to claim 1, having a weight ratio that provides a eutectic composition. 3. The solder bump comprises an Sn layer having a large ionization tendency and an A layer having an ionization tendency smaller than that of the Sn layer.
The semiconductor device according to claim 1, comprising a u layer. 4. A step of forming an insulating film on a surface of a semiconductor element, a step of forming a patterned resist layer on the insulating film so as to correspond to a solder bump forming region, and the solder bump of the resist layer. A step of removing the insulating film exposed in the formation region, and forming a first metal layer thicker than the resist layer on the surface of the semiconductor element corresponding to the solder bump formation region where the insulating film is removed And a step of forming a second metal layer having an ionization tendency smaller than that of the first metal layer around the first metal layer as a nucleus, and manufacturing the semiconductor device. Method. 5. A Ti adhesion metal layer, a Pt barrier layer, on the surface of the semiconductor element corresponding to the solder bump formation region,
The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming an electrode made of an Au contact metal layer.