JPH07129115A - Error diffusion processing circuit of display device - Google Patents

Abstract

PURPOSE:To obtain an error diffusion processing circuit of a display device which can process error diffusion and emphasize a profile simultaneously by a level of the detected edge of an image signal. CONSTITUTION:In a device which adds a reproduced error which occurs in the past before an original picture element to an original picture element picture signal which is input to obtain a diffusion output signal and outputs with less bits than an original picture element picture input signal for pseudo-half tone display, an error detection circuit 35 which processes error diffusion and emphasizes an edge simultaneously based on the diffusion output signal is provided to diffuse and process a picture signal which is input and reduce the number of bits further. At the same time, the picture signal is sent to an edge emphasis section 47 and a level judgement section 48 to divide it into multi-stage threshold in accordance with an edge detection level. A target correction luminance line is selected from the data stored previously in a memory 38 by the threshold and is output so that profile emphasis processing is also carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error diffusion processing circuit of a display device for performing pseudo halftone display such as error diffusion.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP (plasma display panel). This PDP driving method is completely different from the conventional CRT driving method and is a direct driving method using a digitized video input signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs can be divided into two types, AC type and DC type, which have different basic characteristics. In DC type PDPs, there have been reports of improvement methods for brightness and life, which have already been issues, and progress toward practical application is being made. is there.

However, in the AC type PDP, although sufficient characteristics have been obtained in terms of brightness and service life, with regard to gradation display, only a maximum of 64 gradation display has been reported at the prototype level. A future 256-gradation method based on the die driving method (ADS subfield method) has been proposed. A panel structure of a PDP (plasma display panel) 10 used in this method is shown in FIG.
The drive sequence and drive waveforms are shown in FIGS.

In FIG. 7, an X sustain electrode 12 and a Y sustain electrode 13 which form a pair are formed on the lower surface of the surface glass substrate 11 on the display surface side by a transparent electrode and an auxiliary electrode. The auxiliary electrode forms the bus electrode 23 on a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. A dielectric layer 14 is provided on the X sustain electrode 12 and the Y sustain electrode 13, and a stripe rib 18 is formed on the dielectric layer 14 to separate the coupling between the cells. Further, a protective layer 15 made of a MgO film is deposited. Address electrodes 17 are formed on the back glass substrate 16 facing each other. The stripe-shaped ribs 18 on the stripes are provided between the address electrodes 17, and the address electrodes 17 are covered with R.
The (red) phosphor 19, the G (green) phosphor 20, and the B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is enclosed.

In FIG. 8A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
It is composed of 8 sub-fields, and 256 gradations are displayed by combining the brightness of 8 screens. In FIG. 8B, each subfield is refreshed 1
It is composed of an address period for writing data for the screen and a sustain period for determining the luminance level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the AC driving method as described above, as the number of gradations is increased, the number of bits in the address period as a preparation period for lighting and emitting the panel within one frame period is increased. The period is relatively short and the maximum brightness is low. In this way, since the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is reduced, and conversely If the number of bits is reduced, the light emission luminance is increased, but gradation display is reduced and the image quality is deteriorated.

The error diffusion process for reducing the grayscale error between the input signal and the emission brightness while reducing the bit number of the output drive signal more than the bit number of the input signal is a process for expressing pseudo halftone. , Used when expressing light and shade with few gradations. A conventional general error diffusion processing circuit is shown in FIG. In this circuit, the video signal input terminal 30
, The video signal of the original pixel Ai, j of n (for example, 8) bits is input, passes through the vertical direction addition circuit 31, the horizontal direction addition circuit 32, and is further converted into the number of bits m by the bit conversion circuit 33.
The process of reducing the number of bits (for example, 4) is performed, and the PDP 10 emits light through the PDP drive circuit.

The error diffusion signal from the horizontal direction adder circuit 32 is stored in advance with the error detection circuit 3.
5, the error weighting circuits 40 and 4 are compared by taking the difference.
The weighting is performed by multiplying a predetermined coefficient by 1, and the error detection output as shown in FIG. 6 is output to the pixel h line before the original pixel Ai, j, for example, the reproduction error Ej− that has occurred in the past by one line.
The original pixel Ai, j is added to the vertical direction addition circuit 31 via the h line delay circuit 36 that outputs 1.
It is added to the horizontal addition circuit 32 via a d-dot delay circuit 37 that outputs a reproduction error Ei−1 that occurred one pixel before d dots, for example, one dot in the past. In addition,
The coefficients in the error weighting circuits 40 and 41 are generally set so that the sum of all is 1.

As a result, as shown in FIG. 5, the output terminal of the bit conversion circuit 33 momentarily outputs a light emission luminance level represented by 4 bits like a step like a solid line, though it is output. Actually, the upper and lower emission luminance levels of the solid line are alternately output at a predetermined ratio, so that they are recognized in an averaged state and a corrected luminance line of y = x like a dotted line is obtained.

[0010]

In the error diffusion processing circuit as described above, pseudo-halftone display is performed uniformly regardless of the contents and purpose of the video signal. What could enhance the contour was desired.

It is an object of the present invention to obtain an edge of a video signal and a correction luminance line for error diffusion can be selected according to its level.

[0012]

SUMMARY OF THE INVENTION According to the present invention, a reproduction error generated in the past from an original pixel is added to a quantized input original pixel video signal to obtain a diffused output signal to obtain the original pixel video input signal. An apparatus for performing pseudo-halftone display that outputs with fewer bits includes an error detection circuit 35 for simultaneously performing error diffusion processing and edge enhancement based on the diffusion output signal. The error detection circuit 35 includes: An edge emphasizing unit 47 for detecting an edge of an image, and a level judging unit 48 for judging an output level of the edge emphasizing unit 47.
Then, the output of the level determining unit 48 is divided into a plurality of threshold values and a correction luminance line selecting unit 49 for selecting from preset correction luminance lines, and a correction luminance line corresponding to the threshold values are preset. An error diffusion processing circuit of a display device including a memory 38 for storing the data.

[0013]

The input n (for example, 8) -bit video signal is subjected to diffusion processing in the vertical and horizontal addition circuits 31 and 32, and further subjected to processing for reducing the number of bits to m (for example, 4) bits, and output terminal. To 34. At the same time, the video signal is sent to the edge emphasis unit 47 of the error detection circuit 35. The output of the edge emphasizing unit 47 is sent to the level determining unit 48, and is divided into, for example, three levels of threshold values of high, low, and intermediate according to the edge detection level. As a result, a target corrected luminance line is selected from the data stored in advance in the memory 38, output, and added to the vertical / horizontal addition circuits 31 and 32, and the contour enhancement is performed simultaneously with the error diffusion processing.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 30 is an original pixel Ai, j of n bits.
This video signal input terminal 30 is a video signal input terminal of
After passing through the vertical direction addition circuit 31 and the horizontal direction addition circuit 32,
Further, the bit conversion circuit 33 performs a process of reducing the number of bits, and is connected to the video output terminal 34.

An error detection circuit 35 for performing error diffusion processing and edge enhancement is connected to the output side of the horizontal direction addition circuit 32. This error detection circuit 35
Is an edge emphasizing section 47 which is composed of a high-pass filter and detects an edge of an image, a level judging section 48 for judging the output level of the edge emphasizing section 47, and a level judging section 48.
The corrected luminance line selection unit 4 that selects the output of a plurality of stages, for example, three stages of threshold values from preset corrected luminance lines, and selects the corrected luminance line.
9. A memory 38 for presetting and storing correction luminance lines when the threshold is high, when the threshold is low, and when the threshold is intermediate.

The correction luminance line stored in the memory 38 is, as shown in FIG. 2, specifically, the first correction luminance line P1 when the threshold value is high is a 4-bit like step shape. The light emission brightness level Q represented by
The second line when the threshold value is low is composed of a straight line of a linear function as shown by a dotted line along the slightly upper side of the emission brightness level Q.
The correction luminance line P2 of No. 1 does not intersect the light emission luminance level Q as much as possible, and is composed of a linear function line as indicated by a two-dot chain line along the slightly lower side of the light emission luminance level Q, and the threshold value is between these values. In this case, the third corrected luminance line P3 is assumed to be a straight line of a linear function as shown by the solid line intersecting the substantially middle position of the emission luminance level Q.

Since the output of the level determining section 48 has three stages, the correction luminance line also has three stages, but the number of stages may be two, or four or more. Although the correction luminance lines P1, P2, P3 are all straight lines, they may be curves of an m-order function, the polarities of the curves may be changed, or a combination of a straight line of a linear function and a curve of an m-order function. You can also

On the output side of the memory 38, the original pixel A
It is connected to the vertical direction addition circuit 31 through a pixel h line before i, j, for example, an h line delay circuit 36 that outputs a reproduction error Ej−1 generated in the past by one line, and the original pixel Ai, The horizontal addition circuit 3 is supplied via a d-dot delay circuit 37 that outputs a reproduction error Ei-1 generated by d dots before j, for example, one dot in the past.
Connected to 2.

In the above structure, the video signal input terminal 30 is connected to the n (eg, 8) -bit original pixel Ai, j.
Image signal is input, the vertical direction adder circuit 31 and the horizontal direction adder circuit 32 perform diffusion processing, and the bit conversion circuit 33 further reduces the number of bits to m (for example, 4) bits, and outputs the output terminal 34. Output.

At the same time, the output from the horizontal direction addition circuit 32 is sent to the edge emphasis section 47 of the error detection circuit 35. The edge emphasizing unit 47 serves as an address and is sent to the memory 38 and also to the level determining unit 48. The level determination unit 48 divides the threshold value into three levels according to the edge detection level. When the threshold value is high, the corrected luminance line selection unit 49 indicates the data stored in advance in the memory 38 with a dotted line. Such a first corrected luminance line P1 is selected and output, and the error output as shown in FIG.
The pixel before the h line, for example, is added to the vertical direction addition circuit 31 via the h line delay circuit 36 that outputs the reproduction error Ej−1 generated by one line in the past, and d is added from the original pixel Ai, j. It is added to the horizontal addition circuit 32 through a d-dot delay circuit 37 that outputs a reproduction error Ei-1 generated by the pixel before the dot, for example, one dot in the past, and the edge enhancement is performed simultaneously with the error diffusion processing. Similarly, when the threshold value is low, the second correction luminance line P2 as indicated by the chain double-dashed line is selected and output from the memory 38. The third corrected luminance line P3 as shown is selected and output, and the contour enhancement is performed simultaneously with the error diffusion processing.

[0021]

According to the present invention, since the error detection circuit 35 for simultaneously performing the error diffusion processing and the edge enhancement based on the diffusion output signal is provided, the edge of the video signal is detected and the correction brightness of the error diffusion is adjusted according to the level thereof. The line can be selected and the contour can be emphasized simultaneously with the error diffusion process.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error diffusion processing circuit of a display device according to the present invention.

FIG. 2 is a characteristic diagram of a correction luminance line and a light emission luminance level stored in a memory 38 of FIG.

FIG. 3 is a characteristic diagram of error output in the case of FIG.

FIG. 4 is a block diagram showing an error diffusion processing circuit of a conventional display device.

5 is a characteristic diagram of drive signal vs. emission brightness level according to the case of FIG. 4;

FIG. 6 is a characteristic diagram of error output according to the case of FIG.

FIG. 7 is a perspective view of a PDP used in a 256 gradation method.

FIG. 8 is a drive sequence diagram and a drive waveform diagram in the 256 gradation method.

[Explanation of symbols]

10 ... PDP (plasma display panel), 1
1 ... Surface glass substrate, 12 ... X sustain electrode, 13 ...
Y sustain electrode, 14 ... Dielectric layer, 15 ... Protective layer, 1
6 ... Back glass substrate, 17 ... Address electrode, 18 ... Strip-shaped rib, 19 ... R (red) phosphor, 20 ... G (green)
Fluorescent material, 21 ... B (blue) fluorescent material, 22 ... Discharge space, 23
... bus electrodes, 30 ... video signal input terminals, 31 ... vertical direction addition circuit, 32 ... horizontal direction addition circuit, 33 ... bit conversion circuit, 34 ... output terminal, 35 ... error detection circuit, 36 ... h
Line delay circuit, 37 ... d dot delay circuit, 38 ... Memory, 40 ... Error weight circuit, 41 ... Error weight circuit, 47 ...
Edge enhancement section, 48 ... Level determination section, 49 ... Corrected luminance line selection section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayuki Kobayashi, 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa, Fujitsu General Co., Ltd.

Claims (3)

[Claims] 1. A quantized input original pixel video signal is added with a reproduction error generated in the past from the original pixel to obtain a diffused output signal, which is output with less bits than the original pixel video input signal. An error diffusion processing circuit for a display device, comprising the error detection circuit 35 for simultaneously performing error diffusion processing and edge enhancement based on the diffusion output signal. 2. The error detection circuit 35 includes an edge enhancement unit 47 for detecting an edge of an image, a level determination unit 48 for determining the output level of the edge enhancement unit 47, and a plurality of outputs of the level determination unit 48. Corrected luminance line selection unit 49 that selects from the preset corrected luminance lines by dividing the threshold value of the step
2. The error diffusion processing circuit for a display device according to claim 1, further comprising: a memory 38 for presetting and storing a correction luminance line according to a threshold value. 3. The error detection circuit 35 includes an edge enhancement unit 47 which is composed of a high-pass filter and detects an edge of an image.
A level determination unit 48 for determining the output level of the edge enhancement unit 47, and a correction luminance line selection unit for dividing the output of the level determination unit 48 into three levels of threshold values and selecting from preset correction luminance lines. 49 and the first when the threshold is high
The correction luminance line P1 of 1 is a linear function line which does not intersect the stepwise emission luminance level Q as much as possible and is slightly higher than the emission luminance level Q, and the second correction luminance line when the threshold value is low. Let P2 be a straight line of a linear function along the slightly lower side of the light emission luminance level Q, which does not intersect the light emission luminance level Q as much as possible, and the third corrected luminance line P3 when the threshold value is in the middle of them. The error diffusion processing circuit of the display device according to claim 1, further comprising: a memory 38 that stores in advance a straight line of a linear function that intersects a substantially intermediate position of the emission luminance level Q.