JPH07128426A - Satellite reception system - Google Patents

Abstract

PURPOSE:To facilitate handling of a satellite reception system where radio waves are received by using plane antenna elements in a GPS (global positioning system), etc. CONSTITUTION:The satellite reception system is provided with a converter body 4 which includes a PLL circuit and has an antenna converter 5 where a converter for down-converting received radio waves and a plane antenna device are integrated, and an operation display equipment 8 which includes a means for demodulating the signals from the body 4, a means for applying specified digital-signal processing to the demodulated data and a display means for displaying the information resulted from the processing. A PLL lock circuit 7 is provided in the body 4 so as to supply specified signals to the PLL circuit, a DC power supply is prepared within the equipment 8, a reference oscillation circuit 6 is prepared in either of the body 4 and the equipment 8, and the signals issued from the body 4, the DC power supply from the equipment 8 and the clock from the circuit 6 are superimposed, thus sending signals between the body 4 and the equipment 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite receiving system, and more particularly to a satellite receiving system for receiving radio waves by using a planar antenna element in GPS (Global Positioning System) or the like.

[0002]

2. Description of the Related Art GPS is a system for knowing a user's current position (latitude, longitude, altitude) by utilizing radio waves radiated to the ground from a plurality of GPS satellites, which are usually antenna units, It is composed of a receiving unit, a signal processing unit, a display unit, and the like.

Radio waves radiated from the artificial satellite to the ground are received by an antenna unit, amplified by a low noise amplifier, and then supplied to a receiving section. The receiving unit demodulates the signal from the antenna unit and then supplies it to the signal processing unit.

The signal processing unit performs signal processing for positioning based on the demodulated data from the receiving unit. On the display,
The result of positioning processing by signal processing is displayed on the map.
This GPS is used, for example, as a navigation system for automobiles.

FIG. 5 is a block diagram of an example of a conventional satellite receiving system. In FIG. 5, 1 is a planar antenna device, 2
Is a converter, and 3 is a demodulation and operation display device.

Radio waves received from the planar antenna device 1 are converted by the converter 2 into an intermediate frequency (I) of 1.023 MHz.
F OUT) is down-converted. Converter 2
Is an RF amplifier (not shown), first and second mixers, first
And a second IF, VCO, and PLL circuit have a well-known configuration. The converter 2 is also 18MHz
Of the reference oscillator (TCXO).

The IF OUT and the TCXO are superimposed and supplied to the demodulation and operation display device 3. The operation display device 3 has a built-in power supply circuit, and the DC power supply DC
It is supplied to the converter 2 by being superimposed on the UT and TCXO.

Further, a low enable signal (LE), DATA, and CLOCK are supplied from the operation display device 3 to the PLL circuit in the converter 2. However, it was difficult to superimpose these signals and supply them with a single cable.

[0009]

However, in the above-mentioned conventional satellite receiving system, the number of connecting cables between the converter 2 and the operation display device 3 is large, and the converter 2 is a separate body from the antenna. There was a problem that the handling of 2 became complicated.

Therefore, an object of the present invention is to provide a satellite receiving system that solves the above problems.

[0011]

[Means for Solving the Problems] The above problems can be solved by the following constitution.

That is, a satellite receiving system that demodulates a signal of a predetermined frequency obtained by down-converting the received radio wave from the planar antenna device, performs predetermined digital processing, and displays information according to the received radio wave based on the processing result. In, a converter that includes a PLL circuit and down-converts a radio wave received from a flat antenna device, a converter body having an antenna converter that integrates the flat antenna device, and means for demodulating a signal from the converter body. A PLL that includes a means for performing a predetermined digital signal processing on demodulated data and an operation display device including a display means for displaying information based on a processing result, and supplies a predetermined control signal and data to a PLL circuit. A lock circuit is provided in the converter body, a DC power supply is provided in the operation display unit, and The reference oscillator circuit is provided in either the converter main body or the operation display device, and the converter main body and the operation display device are superposed by superimposing the signal from the converter main body, the DC power supply from the operation display device, and the clock from the reference oscillation circuit. It is solved by performing signal transmission with.

[0013]

According to the present invention having the above-described structure, the antenna converter has a structure in which the converter and the planar antenna device are integrated, so that the transmission loss of radio waves and the interference are reduced.

Further, a PLL lock circuit for supplying a predetermined control signal and data to the PLL circuit of the antenna converter is provided inside the converter main body, and signal transmission between the converter main body and the operation display device is performed from the converter main body. It is performed by superimposing the signal, the DC power supply from the operation display device, and the clock from the reference oscillation circuit, so that the signal transmission between the converter main body and the operation display device acts as if it were performed by a single signal line. .

[0015]

FIG. 1 is a schematic system configuration diagram of a first embodiment of the present invention.

The converter main body 4 has an antenna converter 5 in which a planar antenna device and a converter for down-converting a radio wave received from the planar antenna device are integrated, which will be described briefly with reference to FIG. The antenna converter 5 includes a PLL circuit (not shown).

Further, in the converter main body 4, 18 MHz
Of the low-enable signal (LE), D
PLL lock circuit 7 for supplying ATA and CLOCK
Is provided.

A DC power supply device (not shown) is provided on the set board 9 in the operation display device 8, and the signal IF OUT from the converter main body 4 is demodulated to perform predetermined digital processing, and the signal is received based on the processing result. Information corresponding to the radio waves (display of current position on map, etc.) is displayed.

The set board 9 operates using TCXO OUT supplied from the converter main body 4 via the transmission cable 10 as a reference clock. Each of these signals and power supplies,
IFOUT, TCXO OUT, and DC are superimposed on each other and transmitted via a single transmission cable 10.

FIG. 2 is a detailed block diagram of the first embodiment of the present invention. 2, the same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, the antenna converter 5 comprises a planar antenna device 11 and a converter 12. The planar antenna device 11 includes an antenna element 13 and a low noise amplifier 14.

The converter 12 includes an RF amplifier 15, a first mixer 16, and a 19.437 MHz first IF 17.
, Second mixer 18, and 1.023 MHz second IF1
9, a PLL circuit 20, and a voltage controlled oscillator (VCO) 21 of 1555.983 MHz are well-known configurations.

The converter body 4 also includes TCXO, IF
It has a synthesizing circuit (multiplexing circuit) 22. This TCX
The O, IF combining circuit (multiplexing circuit) 22 superimposes the reference oscillation frequency TCXO OUT from the TCXO 6 and the intermediate frequency IF OUT from the second IF 19 on the transmission cable 10.
The DC power supply DC supplied from the transmission cable 10 is separated and supplied to each circuit.

The operation display device 8 has a DC power supply device on a set substrate which does not appear in FIG.
A separation circuit (multiplexing circuit) 23, a GPS demodulation circuit 24,
CPU 25, ROM (Read Only Memory) 26,
RAM (random access memory) 27 and CPU 28
The ROM 29, the RAM 30, the LCD display 31, and the key input device 32.

This TCXO, IF separation circuit (multiplex circuit)
23 is T which is superposed and supplied from the transmission cable 10.
Reference oscillation frequency TCXO OUT from CXO6 and second
The intermediate frequency IF OUT from the IF 19 is separated, and the DC power source DC from the DC power source device is transmitted by the transmission cable 1.
Supply to 0.

The separated TCXO OUT is the CPU 2
It becomes a reference clock such as 5. Also, the separated IF O
The UT is demodulated by the GPS demodulator 24 and the demodulated data is CP.
Supplied to U25. The CPU 25 is connected to the ROM 26, the RAM 27, and the CPU 28 via a bus line.

The CPU 28 is a ROM via a bus line.
29, RAM 30, and LCD display 31, and performs predetermined digital processing according to a command from the key input device 32, and displays information according to received radio waves on the LCD display 31 based on the processing result. It has become.

As described above, according to this embodiment, since the antenna converter 5 is integrated, there is an advantage that the handling is easy. Further, the integration reduces radio wave transmission loss, interference, etc., and high-quality position information can be obtained.

A PLL lock circuit 7 for supplying a predetermined control signal and data to the PLL circuit 20 of the antenna converter 5 is provided in the converter main body 4, and signals of the converter main body 4 and the operation display device 8 are provided. Transmission includes a signal IF OUT from the converter body 4, a DC power source DC from the operation display device 8, and a TC from the reference oscillation circuit.
Since it is carried out by superimposing XO OUT, the signal transmission between the converter main body 4 and the operation display device 8 can be facilitated even if it is carried out by a single signal line.

Next, FIG. 3 is a schematic system configuration diagram of the second embodiment of the present invention, and FIG. 4 is a detailed block configuration diagram of the second embodiment of the present invention. 3 and 4,
The same components as those in FIGS. 1 and 2 are designated by the same reference numerals.

That is, in the satellite receiving system shown in FIG. 3, the TCXO 6 is not provided in the converter main body 4a, but is provided in the small board box 35 in the operation display device 8a.

The converter body 4a is composed of TCXO, I
The F separation circuit (multiplex circuit) 33 is displayed on the operation display device 8a as T
It has a CXO and IF combining circuit (multiplexing circuit) 34, respectively.

This TCXO, IF separation circuit (multiplex circuit)
33 is a reference oscillation frequency T from the TCXO 6 in the operation display device 8a which is superimposed and supplied from the transmission cable 10.
The CXO OUT and the DC power supply DC from the DC power supply device are separated, and the intermediate frequency IF O from the second IF 19 is separated.
The UT is superimposed and supplied to the transmission cable 10. DC power supply DC is supplied to each circuit.

Also, TCXO, IF synthesis circuit (multiplex circuit)
34 is a reference oscillation frequency TCXO O from the TCXO 6
The UT and the DC power supply DC from the DC power supply device are superposed and supplied to the transmission cable 10, and the IF supplied from the converter main body 4a is superposed and supplied from the transmission cable 10.
OUT is separated and supplied to the GPS demodulator 24.

It is needless to say that this embodiment can also obtain the same effects as those of the first embodiment.

[0036]

As described above, according to the present invention, since the antenna converter has a configuration in which the converter and the planar antenna device are integrated, the transmission loss of radio waves is reduced,
Since there is little interference etc., high performance can be achieved, and P
The LL lock circuit is provided in the converter body,
Signal transmission between the converter main body and the operation display device is performed by a signal from the converter main body, a DC power supply from the operation display device,
Since it is performed by superimposing the clock from the reference oscillation circuit, the signal transmission between the converter main body and the operation display device is performed by a single signal line, which has the advantage of being easy to handle.

[Brief description of drawings]

FIG. 1 is a schematic system configuration diagram of a first embodiment of the present invention.

FIG. 2 is a detailed block diagram of the first embodiment of the present invention.

FIG. 3 is a schematic system configuration diagram of a second embodiment of the present invention.

FIG. 4 is a detailed block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of an example of a conventional satellite receiving system.

[Explanation of symbols]

 4,4a converter body 5 antenna converter 6 TCXO 7 PLL lock circuit 8, 8a operation display device 9 set substrate 10 transmission cable 10 11 planar antenna device 12 converter 20 PLL circuit 22, 34 TCXO, IF combination circuit (multiplex circuit) 23, 33 TCXO, IF separation circuit (multiplex circuit) 24 GPS demodulator 25, 28 CPU 31 LCD display

Claims (1)

[Claims] 1. A satellite receiver that demodulates a signal of a predetermined frequency obtained by down-converting a received radio wave from a planar antenna device, performs predetermined digital processing, and displays information according to the received radio wave based on the processing result. In the system, a converter that includes a PLL circuit and down-converts a radio wave received from a planar antenna device, a converter main body having an antenna converter that integrates the planar antenna device, and a signal from the converter main body is demodulated. Means for performing predetermined digital signal processing on the demodulated data, and an operation display device including display means for displaying information based on the processing result, wherein the PLL circuit has predetermined control signals and data. Supply P
An LL lock circuit is provided in the converter body, a DC power source is provided in the operation display device, a reference oscillation circuit is provided in either the converter body or the operation display device, and a signal from the converter body and the operation are provided. A satellite receiving system characterized by performing signal transmission between the converter body and the operation display device by superimposing a DC power supply from the display device and a clock from the reference oscillation circuit.