JPH0712785A - Ultrasonic signal processing device - Google Patents

Abstract

PURPOSE:To perform the highly precise digital phasing processing of an ultrasonic device at low cost. CONSTITUTION:A device is supplied with an input signal obtainable when a reflected wave having a central angle frequency omega reaches a receiver element having an element number (n) after the elapse of a propagation time taun. Then, when the standardized period of an input signal processing system is Ts and the time taun is quantized with Ts, the phases of the carriers are aligned with each other because of a phase difference due to the time taun among receiver elements, provided that the carriers or waves are made to travel along a time axis having a unit of Ts via delay circuits 11 to 1m. Then, for integrating the waveforms of all receiver elements, complex multipliers 21 to 2m are used to make correction for the phase terms of the carriers. Also, real and complex parts are added in adders 31 and 32, thereby enabling a filter circuit to be used in common via a plurality of input signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device configuration for signal processing such as an ultrasonic device for nondestructively inspecting an object by ultrasonic waves, or an ultrasonic device used for medical diagnosis, and more particularly to time accuracy of phasing addition. The present invention relates to an ultrasonic signal processing apparatus suitable for numerical calculation of received signal processing, such as improvement of cost and cost reduction by reducing filter.

[0002]

2. Description of the Related Art In a conventional electronic scanning type ultrasonic wave receiving device, a reflected wave obtained due to a transmitted sound wave radiated to a target such as a body is received by an array of receiving elements.
Since each reflected signal from the target received by each receiving element has a difference in the propagation time of the sound wave, it is necessary to adjust the delay time given to the received signal of each element and integrate them after they are in phase. As a result, the received signals of the respective elements are strengthened, detected, and converted into a luminance signal of the display device, whereby a tomographic image is obtained. Further, the signals based on the reflections from other than the target object are suppressed by canceling each other at the time of the integration processing because the phases of the carrier waves of the respective signals are different. In this case, in the conventional case, since a plurality of analog delay circuits perform phasing of signals received by a plurality of receiving elements and the resolution is formed by adding them, an analog delay with a wide delay time and high accuracy is provided. Many circuits were needed. However, increase in the number of elements that transmit and receive (for example, about 100)
As a result, the signal dynamic range in the integration process increases, making it difficult to secure phasing accuracy in the analog element. As a result, it has become necessary to perform phasing of signals received by a plurality of receiving elements by digital processing. In order to perform phasing by digital processing, it is necessary to discretize the received signal, but since the delay and addition of the discrete received signal are performed with the sampling time at that time as the unit, the received signal with respect to the sampling frequency If the frequency of the carrier wave is high, sufficient phasing accuracy cannot be realized, and since the operating frequency is high, the analog-to-digital converter and the digital signal processing system with large power consumption are expensive. To avoid this,
After demodulating the envelope of the received signal by detection and then adding the delay and addition of the discrete received signal in units of the above sampling time, it is sufficient even if the sampling frequency is low compared to the case where a carrier wave exists in the signal. Achieves excellent phasing accuracy.

On the other hand, as a digital signal processing technique in the communication field, there is a demodulation method already known as quadrature detection. This is a demodulation method in which a received signal is mixed with a reference wave generated by local oscillation by a multiplier, the carrier frequency is moved, and the carrier of the signal is converted to move to direct current. In the following, when this method is directly applied to the ultrasonic receiving apparatus, the processing for each received signal will be described with reference to FIG. Let Sn (t-τn) be the received signal obtained when the reflected wave generated from the reflection source at time t = 0 and having the central angular frequency ω reaches the receiving element with the element number n after the propagation time τn. Sn (t-τn) = A (t-τn) [exp {jω (t-τn)} + exp {-jω (t-τn)}] ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ( It can be expressed approximately as 1). Here, A (t) is the envelope shape of the transmission signal. This received signal Sn is used as an input signal of the demodulator of FIG. A sine wave reference signal whose central angular frequencies are ω that are orthogonal to each other by a local oscillator (not shown)
203 and 204 are generated, and the reference signals 203 and 204 and the received signal Sn are multiplied by the multipliers 201 and 202. Here, the phase of the sine wave reference signal 203 is δ at the reflected wave generation time t = 0 at the reflection source, which is common to a plurality of receiving elements having all element numbers. Received signal Sn
Is multiplied by these orthogonal reference signals, resulting in a multiplier 201,
Input Gn of low pass filter 71, 72 cascaded to 202
(T) is expressed by the following equation when the real part multiplied by the reference signal 203 and the imaginary part multiplied by the reference signal 204 are considered together. Gn (t) = Rn (t-τn) exp {-jω (t + δ)} = A (t-τn) [exp {-jω (τn + δ)} + exp {-jω (2t-τn + δ )}] ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (2)

By filtering this signal with the low-pass filters 71 and 72, the signal whose double frequency component has been sufficiently attenuated is Fn.
If (t), then Fn (t) = A (t−τn) exp {−jω (τn + δ)} (3). That is, two items in the equation (2) are sufficiently reduced. Since τn is different for each receiving element, it is necessary to move Fn (t) in equation (3) with time. The sampling period of the received signal processing system is Ts, and the propagation time τn is T
When quantized by s, τn = Pn Ts + Qn (where Pn is an integer, 0 ≤ Qn <Ts) (4), the equation (3) becomes Fn (t) = A (t- (Pn Ts + Qn)) exp {-jω (Pn Ts + Qn + δ)} (5) For example, when the propagation time τn is divided by Ts, 3
Then, when the rest is Qn, the value of τn is 3Ts + Qn. In the discretized signal processing system, it is possible to easily move on the time axis with the sampling period Ts as a unit, and the time t in equation (5) is t + Pn using the delay means 1r and 1i in FIG.
Letting F'n (t) be the delayed one replaced with Ts, F'n (t) = A (t-Qn) exp {-jω (PnTs + Qn + δ)} ... Get (6). As is clear from the equation (6), the phase term Un caused by the propagation time τn is given by the following equation. Un = exp {-jω (Pn Ts + Qn + δ)} ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (7) Since the value of Eq. (7) is different for each receiving element, set it to a predetermined phase. It is necessary to perform a process of integrating the waveforms of all the receiving elements after the alignment. Here, assuming that the sound velocity is constant, τn when the focus of reception is assumed is known, so U'n = exp {jω (PnTs + Qn)} ...・ ・ The processing of multiplying (7a) by equation (6) is performed. If this result is Hn (t), Hn (t) = A (t-Qn) exp {-jω (Pn Ts + Qn + δ)} exp {jω (Pn Ts + Qn)} = A (t-Qn ) exp {-jωδ} (8), it becomes possible to make the phase difference of the carrier waves of the signals of all receiving elements in-phase.

This operation of multiplying by Un 'is realized by the complex multiplier C shown in FIG. Since the complex multiplier C realizes an operation of multiplying a signal having a real part and an imaginary part by a complex constant, the phase value θ is as follows. θ = ω (Pn Ts + Qn) = ωτn (9) Circuits 41 to 44 for holding the sine value and cosine value of this phase θ, multiplier 51 to 54, and adders 61, 62 are required. Adder 6
The real part output Rn and the imaginary part output In of 1,62 are real part outputs (R1, R2, ...
Rn-1, Rn + 1, ...) And imaginary part output (I1, I2, ... In-1, In +
1, ...) are added together to form a pair of real part output and imaginary part output. By connecting the circuit for obtaining the square root of the sum of squares of the pair of outputs after the device portion shown in FIG. 9 (for example, see 81 in FIG. 2), the envelope A (t) obtained by phasing is obtained. . As outputs of the real part output Rn and the imaginary part output In of the adders 61 and 62, a time error Qn remains in the detected envelope A (t-Qn), but generally the time length of the envelope A (t) is Is sufficiently longer than the time quantization error Qn, so that a significant improvement effect can be obtained as compared with the case where the signal has a carrier and is time-shifted in units of sampling time to perform phasing addition.
Note that documents related to this type of device include, for example,
There are specifications of Japanese Patent No. 1333370 and US Patent No. 4140022.

[0006]

In the detection method as described above, immediately after each of the multipliers 51 to 54 which are in charge of the real part and the imaginary part,
A low pass filter for filtering the double frequency signal band generated by multiplication is required. Normally, this filter is required to have strict cutoff characteristics and attenuation characteristics in the stopband, which may cause a large increase in circuit scale in an ultrasonic reception signal processing apparatus that processes about 100 reception signals in parallel in real time. It was difficult to realize in the end. In addition, when the reflection source is close to the receiving element or the spatial width of the array of receiving elements is a large condition, when moving on the time axis, a very long time width There is a problem that a means for holding the signal is needed. An object of the present invention is to solve the conventional problems as described above, to significantly improve the time accuracy of phasing addition, and to reduce the number of low-frequency filters to reduce the cost. An object is to provide a sound wave signal processing device.

[0007]

In order to achieve the above object, an ultrasonic signal processing apparatus according to the present invention comprises: (a) a signal for converting a plurality of reflected ultrasonic waves into electric reception signals and performing phasing addition. In the processing device, means for quantizing the amplitude of the received signal which is a continuous time signal to obtain a discretized received signal at a predetermined sampling time, and means for delaying the discretized received signal in units of sampling time (FIG. 1). 11 to 1 m) and delay means (11 to 1 m)
1m) means for multiplying the discretized received signal delayed by (1m) and two reference signals discretized at the sampling time and orthogonal to each other, and a plurality of two means obtained by the multiplying means (21-2m). Means (31, 32) for adding signals of the system and addition means (3
1,32) means (71, 72) for filtering the high frequency component of the signal obtained, and means (81) for obtaining the amplitude of the signal based on the output of the filtering means (71, 72), at least Be prepared. Further, the ultrasonic signal processing apparatus of the present invention corresponds to (b) the discretized received signal delayed by the delay means (11 to 1 m in FIG. 2) and the discretized received signal at each sampling time. Means for performing parallel multiplication with two sinusoidal reference signals having different phases and mutually orthogonal phases (21a to 2ma)
And a means (31a, 3a) for adding all the components of each of the two orthogonal signals output by the multiplication means (21a to 2ma) of each received signal.
2a) and means (31a, 32a) connected subordinately to remove high frequency components of the signal by filtering (71, 72) and the amplitude of the signal based on the output of the filtering means (71, 72). Means for seeking (81)
And at least.

Further, the ultrasonic signal processing device of the present invention is
(C) One or more delay means groups (1p + 1 to 1p + q in FIG. 3) for delaying the sampling time as a unit by inputting each of the two orthogonal signal components output from the multiplication means of each received signal And a means (91p, 92p) for adding the outputs of the delay means (1p + 1 to 1p + q) to reduce the number of received signals (P1, P2 in FIG. 4).
By connecting at least one pair of two and connecting them sequentially, the means for repeating the sequential delay and addition to form each set of orthogonal signal components (DL
(1,2, ADR1,2) and means for subordinate connection to the adding means (ADR2) to remove high frequency components of the quadrature signal by filtering (71,72)
And a means (81) for obtaining the amplitude of the signal based on the outputs of the filtering means (71, 72). Also,
The ultrasonic signal processing device according to the present invention includes (d) delay means (see FIG. 5).
11-1 m) of the discretized received signal, and a means (21-2n) for parallel multiplication of two different constant values corresponding to each discretized received signal, and a multiplication means (21 To 2n) output means for adding each of the two signals for each received signal (31, 32) and the two signals obtained by the adding means (31, 32) are discretized at the sampling time. Means (Cm) for parallelly multiplying two sinusoidal reference signals which are orthogonal to each other in phase with each other and frequency-moving the signal (Cm), and the adder means (31, 32) in a cascade connection. The means (71, 72) for removing the high-frequency component of each of the two orthogonal signal components output by the filter and the means (81) for obtaining the amplitude of the signal based on the output of the filtering means (71, 72). , At least equipped. Further, the ultrasonic signal processing device of the present invention uses (e) each of the two signals output by the means for performing parallel multiplication with two different constant values corresponding to the discretized received signal as input, Means (2p + 1) for reducing the number of received signals by adding the output of one or more delay means groups (1p + 1 to 1p + q in FIG. 6) for delaying the conversion time as a unit
~ 2p + q) pair means (P1, P2 in FIG. 7) are connected in cascade to form a pair of signal components by sequentially repeating delay and addition (DL1, ADR1), Means (41 to 44, 51 to 54) for performing a frequency shift of the signals in parallel by multiplying each of the pair of signals by two sinusoidal reference signals which are discretized at the sampling time and whose phases are orthogonal to each other. ), And means for removing high frequency components of each of the two orthogonal signal components output by the frequency shifting means by filtering (71, 72) in a cascade connection to the adding means (61, 62), and the output of the filtering means. And at least a means (81) for obtaining the amplitude of the signal.

[0009]

In the present invention, (a) the sampled received signals of the respective receiving elements are subjected to quadrature detection after moving on the time axis. As a result, when the carrier frequency of the received signal and the frequency of the reference wave signal are exactly the same, the received signal becomes a signal having an envelope signal and a carrier of double frequency.
An envelope signal is taken out by a filter (71, 72) that attenuates a signal component having a carrier of double frequency (see FIG. 1). Since the time length of the envelope signal is sufficiently longer than the time quantization error Qn, a significant improvement effect can be obtained as compared with the case where phasing addition is performed with the carrier having the signal. Also, (b)
Multiplying the delayed discretized received signal with two sinusoidal reference signals that are discretized at the sampling time and have phases corresponding to different delay times corresponding to the respective received signals and whose phases are orthogonal to each other Frequency mixing is performed by means (21a to 2ma) for performing the above in parallel. Means for removing all high frequency components of the signal by means of adding (31a, 32a) all of the two orthogonal signal components respectively output by the multiplying means (71,
The input to 72) is reduced to only a pair of quadrature signals, eliminating the need for a filter to attenuate the signal components having a carrier of doubled frequency in each of the plurality of received signals (see FIG. 2).

Further, (c) not only is it unnecessary to provide a filter for attenuating a signal component having a carrier having a doubled frequency for each of the plurality of received signals, but also the plurality of received signals are divided into groups and each group is divided into groups. In order to reduce the difference in the delay time within, the means (71, 72) for realizing the delay can shorten the total length of the received signal to be held. As a result, when the delay means for each received signal is realized by means of the same specifications,
The scale can be reduced (see FIGS. 3 and 4). Also,
(D) a delayed discretized reception signal, and two DC reference signals that are discretized in sampling time and have phases corresponding to different delay times corresponding to the respective reception signals, and the phases are orthogonal to each other, That is, means for performing multiplication with a pair of constants in parallel
By (21 to 2n), the phase difference between the reference wave and the carrier wave of the received signal at the time of frequency mixing is corrected in advance. Multiplication means (21
~ 2n) means for adding all the respective components of the two orthogonal correction signals output by (31, 32), means for frequency mixing operation of the received signal and the reference wave signal, and means for removing subsequent high frequency components by filtering The input to (71, 72) is reduced to only a pair of quadrature signals, eliminating the need for a filter to attenuate the signal component having a carrier of double frequency in each of the plurality of received signals. Since the phase difference with the carrier wave is corrected in advance, it is not necessary to form sinusoidal reference signals having different phases corresponding to each of a plurality of received signals as compared with the above (b) and (c). Can be reduced (see Fig. 5). Furthermore, (e) above (d)
In the same way as the above, it is not only necessary to provide a sinusoidal reference signal having a different phase from a filter that attenuates a signal component having a carrier of a double frequency in each of a plurality of received signals, A means to realize delay in order to reduce the difference in delay time within each group by dividing (DL1, 2)
In, the total length of the received signal to be held can be shortened (see FIGS. 6 and 7). As a result, when the delay means (DL1, 2) for each received signal are realized by means having the same specifications, the scale can be reduced.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of essential parts of an ultrasonic signal processing apparatus showing a first embodiment (corresponding to claim 1) of the present invention. By radiating from the ultrasonic radiating element toward the subject, the reflected wave generated from the reflection source at time t = 0 and having the central angular frequency ω reaches the receiving element with the element number n after the propagation time τn. In that case, the received signal Sn (t-τn) obtained by the receiving element is approximately represented by the following equation (10). Sn (t-τn) = A (t-τn) [exp {jω (t-τn)} + exp {-jω (t-τn)}] (10) where A (t) is the envelope of the transmission signal. The received signal Sn is used as each input of the processing device of FIG. However, 1 ≦ n
≦ m. The sampling period of the received signal processing system is Ts,
When the propagation time τn is quantized by Ts, τn = PnTs + Qn (Pn is an integer, 0 ≦ Qn <Ts) (11). As a result, the previous equation (10) becomes Sn (t) = A (t- (Pn Ts + Qn)) [exp {jω (t-Pn Ts-Qn)} + exp {-jω (t-Pn Ts-Qn) }] ... ・ (12). If the delay means 11 to 1m move on the time axis in units of the sampling period Ts, the time t in the equation (12) is t + Pn.
Corresponding to the replacement with Ts, and letting this be dn (t), the following equation (13) is obtained. dn (t) = A (t-Qn) [exp {jω (t-Qn)} + exp {-jω (t-Qn)}] = A (t-Qn) [exp {jωt} exp {-jωQn} + exp {-jωt} exp {jωQn}] ·········· (13) As is clear from the previous equation (13), the phase term exp due to the propagation time τn Since {± jωQn} is different for each receiving element, it is necessary to perform processing to integrate the waveforms of all the receiving elements at least after aligning the phases of these carrier waves. Therefore, by using the complex multipliers 21 to 2m, it is necessary to perform a process of correcting the carrier wave phase term. This is the same as the processing of the complex multiplier C in FIG. The signals referred to by the complex multipliers 21 to 2m include a value consisting of a phase term α (t) that is common to the phase difference −ωQn that differs for each received signal, that is, a term of the following expression (14). φn = α (t) − ωQn ······················· (14) A pair of sinusoidal signals that include the term of the above equation (14) and whose phases are orthogonal to each other Are mixed as.

Hereinafter, the reference wave signal is represented by the following expression (15), and the negative sign of the compound sign is taken. ref (t) = exp {± jφn} = exp {± j (α (t) −ωQn)} ··· (15) The delayed received signal dn (t) is mixed by the multipliers 21 to 2m. The resulting signal Mn (t) is as follows. Mn (t) = dn (t) ref (t) = A (t-Qn) [exp {jωt} exp {-jωQn} + exp {-jωt} exp {jωQn}] × exp {-j (α (t) −ωQn)} = A (t-Qn) [exp {j (ωt-α (t))} + exp {-j (ωt + α (t))} exp {2jωQn}] = A (t-Qn) β (t) + A (t-Qn) γn (t) (16) However, β (t) and γ (t) are represented by the following equations, respectively. β (t) = exp {j (ωt−α (t))} ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (17) γn (t) = exp {-j (ωt + α (t))} exp {2jω Qn} ... (18) In the above equation (16), the term A (t−Qn) γn (t) in which the two signal components include the time quantization error Qn in the carrier. And the term A (t−Qn) β (t) that does not include is separated. If Mn (t) corresponding to each received signal is added by the adders 31 and 32, it is added in each of two different types of signal bands. Then, according to a filter (not shown) connected subordinately after the adders 31 and 32 and attenuating the signal band of the term A (t−Qn) γn (t) including the time quantization error Qn in the carrier wave, Accurate phasing addition is realized. That is, as shown in FIG. 2, which will be described later, the adders 31 and 32 may be followed by the filters 71 and 72 and the square sum square root calculator 81.

FIG. 2 shows a second embodiment of the present invention (claim 2).
Is a block diagram of an ultrasonic signal processing device. In the configuration of FIG. 1, the complex multipliers 21 to 2m perform only the correction of the different phase for each received signal, but in the configuration of FIG. 2, the complex multipliers 21a to 2m are used to correct the different phase of each received signal. A process that combines both correction and frequency shift is performed at the same time. The received signal obtained when the reflected wave generated from the reflection source at time t = 0 and having the central angular frequency ω reaches the receiving element with the element number n after the propagation time τn is, as described above, the sampling period. Movement on the time axis in units of Ts delay means 11 to 1 m
When the above is performed, it is represented by dn in the previous equation (13). Complex multiplier 21a
When determining the phase of the signal to be referenced with ~ 2 ma, use the previous equation (14)
In the above, if α (t) = ωt + δ (δ is a constant term) ... (19a), a different phase is obtained for each received signal as shown in the following equation (14a). φn = ωt + δ−ωQn ・ ・ ・ ・ ・ ・ (14a) Frequency mixing using a pair of sinusoidal signals of this phase and the phase orthogonal to this as a reference wave. Is. Hereinafter, the reference wave signal is expressed by the following equation (15a) and the negative sign of the compound sign is taken. ref (t) = exp {± jφn} = exp {± j (ωt + δ−ωQn)} ... (15a) The delayed received signal dn (t) is multiplied by the multipliers 21a to 2ma. The signal Mn (t) resulting from the frequency mixing is expressed by the following equation (16a). Mn (t) = dn (t) ref (t) = A (t−Qn) [exp {jωt} exp {−jωQn} + exp {−jωt} exp {jωQn}] exp {−j (ωt + δ−ωQn )} = A (t-Qn) [exp {-jδ} + exp {-jω (2t + δ + 2Qn)}] (16a) In the above equation (16a), An envelope component A (t-Qn) exp {-jδ} in which two signal components are detected and a term A (t-Qn) exp {-jω (2t + δ + 2Q including the time quantization error Qn in the carrier.
n)}. If Mn (t) corresponding to each received signal is added by the adders 31 and 32, it is added in each of two different types of signal bands. The low-frequency pass filters 71 and 72, which are configured as subordinates to the adders 31 and 32 and thereafter, attenuate the signal band of the term including the time quantization error Qn in the carrier wave, and have the purpose that the envelope signal band exists. The low frequency component is enhanced by the integration effect. The complex signal B (t) obtained as the outputs of the filters 71 and 72 is expressed by the following equation (17). B (t) = A '(t) exp {-jδ} ... (17) where A' (t) is the envelope A (t) of the original signal. It is approximated accurately by a constant multiple of. Also, the phase term exp {−jδ} in Eq. (17)
Therefore, the detection is completed after the arithmetic unit 81 for calculating the absolute value of the amplitude converts it into a real number envelope.

FIGS. 3, 4 and 10 show a third embodiment of the present invention.
FIG. 4 is a block diagram of an ultrasonic signal processing apparatus showing an embodiment (corresponding to claim 3) of FIG. In FIG.
It represents the concept of phasing the time-quantized received signal group by time shift. Here, the horizontal axis of the lattice is the sampling time T
The time in units of S, the vertical axis is the number of the received signal in the spatial arrangement order of the receiving elements. The two arcs F1 and F2 drawn on the grid conceptually illustrate the position on the time axis of each signal to be phased and added with respect to two different focal points. The sampling signal corresponding to the curve F2 determined in accordance with a predetermined focus is phased and added to all the lattice points indicated by black circles in the figure, and therefore the operation of moving on the time axis in units of sampling time is performed. is necessary. For all of the signals S1 to Sm, movement on the time axis is sampled at the sampling point V by the delay circuits of the same scale and the same configuration
In order to carry out all of the sampling signal values during the time T1, a circuit for holding the signal values corresponding to all the sampled signal values is required. on the other hand,
It is also possible to divide this time axis movement into a plurality of times. For example, as shown in FIG. 10, the received signal group is divided into divided groups N1 to N3.
It is conceivable to perform a phasing addition in each divided group, further move the added ones in time, and finally add them to one. By doing so, the received signal groups belonging to N1 and N3 can be processed in the time axis movement width T2, and the signal groups belonging to N2 can be processed in the time axis movement width T3. By performing the phasing addition in the group, the scale of the signal value holding circuit necessary for the second and subsequent movements on the time axis is reduced. Such division of the delay operation may be realized in any number of stages. A third embodiment (claim 3) discloses a case where the principle of reducing the scale of the delay circuit is applied to the configuration of the second embodiment (claim 2) of the present invention. The case where the division of the delay operation is realized in three stages will be described in more detail with reference to FIGS. 3 and 4.

FIG. 3 basically shows the configuration of the same principle as the portion from the input to the outputs of the adders 31a and 32a in the apparatus of FIG. In addition, the configuration of FIG.
Since a desired delay time distribution is applied to the receiving element numbers p + 1 to p + q out of m to perform phasing, the delay circuit 1
The time length of the received signal value held by p + 1 to 1p + q decreases. Signal values dp + 1 to dp + q delayed in sampling time units by the delay circuits 1p + 1 to 1p + q and its control circuit (not shown).
Is subjected to frequency mixing with the reference wave signal in which the delay time corresponding to each received signal is added to the phase by the complex multipliers 2p + 1 to 2p + q. The structure of this complex multiplier is shown in FIG. The real part Rp + 1 to Rp + q and the imaginary part Ip + 1 of the output of the complex multiplier
~ Ip + q are added by adders 91p and 92p, respectively, and are combined into a pair of outputs Ap1 and Ap2. As described above, a plurality of circuits in which frequency mixing and addition are partially performed in parallel are equivalent to P1 to Pu in FIG. P1 to Pu collectively process the received signal groups N1 to Nu, respectively. The addition outputs of the real part and the imaginary part of P1 to Pu are independently delayed by the delay circuit group DL1 whose sampling time is a delay time unit, and added by the adder group ADR1 to reduce the total number of signals. . These are again delayed and added by the delay circuit group DL2 and the adder group ADR2, and become a pair of inputs to the low-pass filters 71 and 72. Low pass filter 71,
In No. 72, the carrier wave generated by the frequency mixing attenuates the signal band of the double frequency, and enhances the target low frequency component by the integration effect. The outputs of the low-pass filters 71 and 72 are the real part and the imaginary part of the envelope signal of a predetermined phase,
An arithmetic circuit 81 which takes the square root of the square sum obtains a real envelope signal. As described above, the operation of sequentially performing the delay operation and the partial addition operation in a small time width by dividing them into a plurality of stages is shown in FIG.
As described above, the present invention is not limited to the case of performing the operation in three steps, and it is needless to say that the operation can be performed in any number of steps of two or more.

FIG. 5 shows a fourth embodiment of the present invention (claim 4).
Is a block diagram of an ultrasonic signal processing device. The configuration of FIG. 5 is similar to the configuration of FIG.
The configuration is such that the phase different for each received signal is preferentially corrected using 2 m. That is, the multipliers 201 and 202 in FIG.
5 is performed by the multiplier Cm in FIG. 5, and the multiplication of the multiplier C in FIG. 9 is performed by the multipliers 21 to 2n in FIG.
The delay circuits 1r and 1i in FIG. 9 have been moved to the delay circuits 11 to 1m in FIG. The reception signal obtained when the reflection wave generated from the reflection source at time t = 0 and having the central angular frequency ω reaches the reception element with the element number n after the propagation time τn has the sampling period Ts as a unit. When the movement on the time axis is performed by the delay circuits 11 to 1m, it is represented by dn in the previous equation (13). When determining the phase of the signal to be referred to by the complex multipliers 21 to 2m, in the above equation (14), if α (t) = 0 ... The phase φn = −ωQn, which is different for each received signal, is obtained (14b). Phase correction is performed using a pair of sinusoidal signal values of this phase and a phase orthogonal to this phase as coefficients. Hereinafter, the phase correction coefficient is defined as shown in the following expression (15b), and the negative sign of the compound sign is used. cor (t) = exp {± jφn} = exp {± j (-ωQn)} ... (15b) The result of phase correction of the delayed received signal dn (t) by the multipliers 21 to 2m The signal Kn (t) is given by the following expression (16b). Kn (t) = dn (t) cor (t) = A (t−Qn) [exp {jωt} exp {−jωQn} + exp {−jωt} exp {jωQn}] exp {jωQn} = A ( t−Qn) [exp {jωt} + exp {−jω (t−2Qn)}] (16b) The multiplier in this case is as shown in FIG. It is the configuration shown in (b),
It has two outputs of a real part and an imaginary part for one real number input. In the above equation (16b), the two signal components are separated into a term including the time quantization error Qn in the carrier and a term not including the time quantization error Qn. If Kn (t) corresponding to each received signal is added by the adders 31 and 32, it is added in each of two different signal bands.

The signal L (t) obtained by the adders 31 and 32
Can be approximated as follows. L (t) = A '(t) exp {jωt} + D (t) exp {-jω (t-ε)} (20) where A' (t) is the envelope of the original signal. The line A (t) is multiplied by a constant and is approximated with high precision. The second term of L (t) D (t) exp {−jω
(t−ε)} is added with the time quantization error Qn included in both the envelope and the carrier, and the envelope D
The degree to which (t) approximates the envelope A (t) of the original signal is A ′
Remarkably worse than the case of (t). Further, ε is a constant determined by addition. The complex multiplier Cm, which is configured as a subordinate of the adders 31 and 32 and thereafter, shifts the frequency of the complex signal L (t) by using a quadrature sine wave signal, and is a carrier wave of the first term component of L (t). To DC and double the carrier frequency of the second term component. Reference signal ref that is input to the multiplier Cm
(t) is represented by the following equation (15a). ref (t) = exp {-j (ωt + δ)} ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (15a) The output signals L (t) of the adders 31 and 32 are multiplied by the reference signal ref (t). Output M '(t) obtained as a result of frequency mixing in the devices 51 to 54
Becomes the following formula (21). M '(t) = B (t) ref (t) = [A' (t) exp {jωt} + D (t) exp {-jω (t-ε)}] × exp {-j (ωt + δ) } = A '(t) exp {-jδ} + D (t) exp {-jω (2t-ε + δ)}] ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (21) Low-frequency pass filter 71 and 72 attenuate the signal band of the second term of M '(t) and preserve the signal band of the first term. The complex signal B (t) obtained as the outputs of the filters 71 and 72 is expressed by the following equation (17b). B (t) = A '(t) exp {−jδ} ... (17b) Since the phase term exp {−jδ} of (17b) remains, The arithmetic circuit 81 for calculating the absolute value of the amplitude completes the detection after converting it into the real number envelope.

6 and 7 are block diagrams of an ultrasonic signal processing apparatus showing a fifth embodiment (corresponding to claim 5) of the present invention. In the third embodiment (Claim 3), the principle is shown in FIG. 10 for explaining the principle, but in the fifth embodiment (Claim 5), the delay using the principle of FIG. 10 is also used. The required scale of the signal value holding circuit can be reduced by dividing the time axis movement by the circuit into a plurality of times. This will be described in more detail with reference to FIGS. 6 and 7. FIG. 6 basically has a configuration of the same principle as the part from the input of FIG. 5 to the outputs of the adders 31 and 32. That is, in the configuration of FIG. 6, since a desired delay time distribution is applied to the reception element numbers p + 1 to p + q out of the total number m of reception signals to perform phasing, the delay circuits 1p + 1 to 1p + q. The time length of the received signal value held by is reduced. The signal values dp + 1 delayed by the sampling time unit by the delay circuits 1p + 1 to 1p + q and its control circuit (not shown).
.About.dp + q are phase-corrected by the complex multipliers 2p + 1 to 2p + q based on the delay time corresponding to each received signal. The structure of this complex multiplier is shown in FIG. Complex multiplier 2
Real parts Rp + 1 to Rp + q and imaginary parts Ip + 1 to Ip + of outputs of p + 1 to 2p + q
The q's are respectively added by adders 91p, 92p, and are combined into a pair of outputs Ap1, Ap2. As described above, a plurality of parallel circuits, each of which is partially phase-corrected, correspond to P1 to Pm in FIG. P1 to Pm are for grouping the received signal groups N1 to Nm, respectively, and performing the processing. P1 ~ Pm
The addition outputs of the real part and the imaginary part are delayed by the delay circuit group DL1 in which the sampling time is a delay time unit independently and added by the adder group ADR1 to reduce the total number of signals. These are again added to the delay circuit group DL2 and the adder group ADR2.
By delaying and adding at, it becomes an input of the multiplier groups 51 to 54 for frequency shifting. The multiplication for frequency shifting is
Since this is a multiplication process between complex signals, four multipliers are required to have adders 61 and 62 for obtaining the sum and difference of the addition of outputs. This adder output pair is a pair of low pass filters 71 and 72.
Will be input to. The low-pass filters 71 and 72 attenuate the signal band in which the carrier wave generated by frequency mixing has a double frequency. Since the low-pass filters 71 and 72 are the real part and the imaginary part of the envelope signal of a predetermined phase, the arithmetic unit 81 that takes the square sum of squares
To obtain a real envelope signal.

In the configuration shown in FIGS. 1 to 7, the delay circuits 11 to
1m and 1p + 1 to 1p + q are RAM (Random Access Memory) and FIFO
(Fast In-Fast Out) memory or the like, and the complex multipliers 21 to 2m, 2p + 1 to 2p + q are shown in FIG.
This can be realized by a pair of multipliers 201 and 202 that generate new real part and imaginary part signal outputs for one real number input as shown in (b). The reference signals 203 to 206 input to the multipliers 201 and 202 are
A sine wave signal whose phases are orthogonal to each other, such as RAM
A memory circuit such as a ROM or a read only memory (ROM) that is sequentially read at each sampling time may be used. In the configurations of the second and third embodiments (claims 2 and 3) which are the configurations for performing the multiplication in FIG. 8A, the reference signal generation may be provided with arithmetic processing. That is, although the phase value used for multiplication of each reception element is shown by (14a), a circuit (not shown) that generates a carrier component ωt + δ common to each reception signal and a phase correction component ωQn unique to each reception signal are generated. A circuit (not shown) and a circuit (not shown) for adding them may be separately provided and generated. Thereby, there is an advantage that a desired frequency shift can be achieved regardless of the value of the phase δ of the carrier wave component. The adders 31 and 32 add signals input in parallel to a cumulative expression or a tournament expression. The low-frequency pass filters 71 and 72 may have many configurations, but a FIR (finite impulse response) filter is preferable in that the delay characteristic at the time of filtering has a linear phase characteristic. FIG. 11 is a configuration diagram showing an example in which the low frequency pass filters 71 and 72 are configured by FIR filters. The filter is a transversal filter, and the adder 703 obtains the total sum of five consecutive signal values divided by the unit delay 701 and multiplied by multipliers 7021 to 7025 having variable coefficients.
With this configuration, signal value integration is performed, and the signal S / N
Is improved. For example, when the coefficients a1 to a5 are all 1, the frequency characteristic has a sampling frequency fs = 1 / Ts and a function (sin
x) / x is a folded property. The zero of the function (sinx) / x is fs
It exists every / 5 and it sees from the direct current of zero frequency, and it is made to contain most of the power of the envelope signal by the frequency of the first zero point. Although FIG. 11 shows the configuration with five taps, the number of taps can be arbitrarily configured, and the coefficient values may be fixed instead of being variable.

[0020]

As described above, according to the present invention,
By moving an ultrasonic signal having a high center frequency to a low frequency by digital processing and performing a phasing process, it is possible to greatly improve the time accuracy of phasing addition. In other words, a significant improvement effect can be obtained as compared with the case where the signal has a carrier wave and is time-shifted in units of sampling time to perform phasing addition. Further, the number of low-pass filters required after the frequency mixing operation for frequency shifting can be reduced to two, so that the cost can be reduced. Further, the scale of the signal value holding circuit required to realize the delay circuit can be reduced, so that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of an ultrasonic signal processing apparatus showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an ultrasonic signal processing apparatus showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a partial frequency mixing / phase correction unit showing a third embodiment of the present invention.

4 is a third embodiment of the present invention configured to include the main circuit of FIG. 3;
FIG. 3 is a configuration diagram of the entire ultrasonic signal processing apparatus showing the embodiment of FIG.

FIG. 5 is a configuration diagram of an ultrasonic signal processing apparatus showing a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a partial phase correction unit showing a fifth embodiment of the present invention.

7 is a fifth embodiment of the present invention configured to include the main circuit of FIG. 6;
FIG. 3 is a configuration diagram of the entire ultrasonic signal processing apparatus showing the embodiment of FIG.

FIG. 8 is a configuration diagram of a complex multiplication unit used in the ultrasonic signal processing device of the present invention.

FIG. 9 is a configuration diagram when a conventional digital demodulation processing configuration is applied to ultrasonic signal processing.

FIG. 10 is a characteristic diagram showing division of a delay operation according to the embodiment of the present invention.

FIG. 11 is a diagram showing a configuration example of a low-frequency pass filter used in the present invention.

[Explanation of symbols]

 S1 to Sm, Sp + 1 to Sp + q Discretized reception signals R1 to Rm, Rp + 1 to Rp + q Complex signal real part I1 to Im, Ip + 1 to Ip + q Complex signal real part 11 to 1m, 1p +1 to 1p + q, 1r, 1i, 701 Delay circuit 21 to 2m, 2p + 1 to 2p + q Complex multiplier 31,32,61,62,91,92,91p, 92p, 703 Adder 51 to 54 , 7021 to 7025 Multiplier 41 to 44 Reference signal 71, 72 Low pass filter 81 Square sum square root calculator or generator DL1, DL2 Delay circuit group ADR1, ADR2 Adder group P1 to Pu Complex multiplier and adder

Front page continuation (72) Inventor Kageyoshi Katayoshi 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. An ultrasonic signal processing apparatus for converting a plurality of reflected ultrasonic waves into electrical reception signals and then performing phasing addition, quantizing the amplitude of the reception signals which are continuous time signals and performing predetermined sampling. Discretizing means for making the discretized received signal in time, delay means for delaying the discretized received signal in units of the sampling time, discretized received signal delayed by the delay means, and discrete for the sampling time Means for multiplying the converted reference signals whose phases are orthogonal to each other, adding means for adding the signals of the two systems obtained by the multiplying means, and filtering the high frequency components of the signals obtained by the adding means. An ultrasonic signal processing apparatus comprising at least a filtering means for attenuating and attenuating means, and a computing means for obtaining an amplitude of a signal based on an output of the filtering means. 2. The ultrasonic signal processing device according to claim 1, wherein the discretized reception signal delayed by the delay means,
Multiplying means for performing parallel multiplication with two sine wave reference signals which are discretized at the sampling time and have different phases corresponding to the respective received signals and whose phases are orthogonal to each other, and the respective received signals. The addition means for adding all of the two orthogonal signal components output from the multiplication means, the filtering means for attenuating the high frequency components of the signal obtained by the addition means by filtering, and the output of the filtering means. An ultrasonic signal processing device comprising at least an arithmetic means for obtaining a signal amplitude. 3. The ultrasonic signal processing device according to claim 2, wherein each of the two orthogonal signal components output by the multiplication means of each received signal is input, and one or more delay units are provided to delay the sampling time as a unit. At least one pair of combination means, which is a pair of delay means group and addition means for adding the outputs of the delay means to reduce the number of received signals, are connected in cascade, thereby sequentially delaying and adding and repeating a set of orthogonal signals. At least a means for making each component, a filtering means for attenuating a high frequency component of the quadrature signal by filtering, and an arithmetic means for obtaining the amplitude of the signal based on the output of the filtering means are provided. Sound wave signal processing device. 4. The ultrasonic signal processing device according to claim 1, wherein the discretized reception signal delayed by the delay means,
Multiplying means for performing parallel multiplication with two different constant values corresponding to the respective discretized received signals, and adding means for adding all of the two signals output by the multiplying means for each received signal, Frequency shifting means for shifting the frequency of the signals in parallel by multiplying each of the two signals obtained by the adding means with two sinusoidal reference signals that are discretized at the sampling time and have mutually orthogonal phases. And at least a filtering means for attenuating a high frequency component of each of the two quadrature signal components output by the frequency shifting means by filtering, and a computing means for obtaining the amplitude of the signal based on the output of the filtering means. Characteristic ultrasonic signal processing device. 5. The ultrasonic signal processing apparatus according to claim 4, wherein each of the two signals output by the multiplication means that performs multiplication with two different constant values corresponding to the discretized reception signal in parallel is input. , At least one pair of means for pairing one or more delay means groups for delaying the sampling time by a unit and addition means for adding the outputs of the delay means to reduce the number of received signals are connected in cascade. Means for sequentially repeating delay and addition to form a set of signal components, and multiplying each of the set of signals by two sinusoidal reference signals that are discretized at the sampling time and have mutually orthogonal phases. Frequency shifting means for shifting the frequency of the signal in parallel,
At least a filtering means for attenuating a high frequency component of each component of the two quadrature signals output by the frequency shifting means by filtering, and a computing means for obtaining the amplitude of the signal based on the output of the filtering means are provided. Ultrasonic signal processing device.