JPH07123252B2 - Network switching system - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to non-buffered multi-stage switching networks, and more particularly to enabling broadcast and multicast functions to be sent over the same single network used for normal message transmission. The present invention relates to a byte-width parallel hardware using a parallel crossbar switch for a byte-parallel multi-size interface switch for broadcasting and multicasting through a multi-stage switching network using a special priority execution method.

[0002]

There are many patents relating to broadcast mechanisms. Some broadcast mechanisms are not implemented in hardware. For example, U.S. Pat. No. 4,818,984 shows a software implemented broadcast mechanism.

Switching networks are different from buses and local area networks (LANs). For example,
U.S. Pat. No. 4,926,375 discloses a broadcast mechanism that operates over a branch bus. Also U.S. Pat.
No. 6,080 is US Pat. No. 4,855,899 and TECHNICAL DISCLOSURE BULLETIN, IBMTDB issued by IBM Corporation.
Vol.30, No.1,6 / 87, pg 72-78, “POLL ACTUATED MULTI
PLE ACCESS TECHNIQUE FOR BROADGATHERING SYSTEMS ”
As in, a broadcast mechanism is shown over several branch buses.

There are several patents showing broadcast mechanisms for LANs. U.S. Pat. No. 4,754,395 discloses a broadcast mechanism that operates over a LAN in a serial loop connection. U.S. Pat. No. 4,835,674 discloses a broadcast mechanism via a multiple loop bus coupled to a LAN and broadcast over the entire setup.

One broadcast mechanism is US Pat. No. 4,897,834.
No. 4,766,592, which is designed for a synchronized multi-time slot bit type network as typified by U.S. Pat. A telecom mechanism is disclosed. IBM TDB Vol.22, No.12,5 / 80, pg 5450−52
"DISTRIBUTED STAR NETWORK WITH UNROOTED TREE TOPO
LOGY "indicates a broadcast mechanism that operates over an unrooted tree network using synchronous transmission and packet switching.

Another mechanism is designed for transmission lines. U.S. Pat. No. 4,935,866 discloses a broadcast mechanism that operates over a synchronous transmission line communication link. U.S. Pat. No. 4,941,084 discloses a broadcast mechanism that operates via a transmission line loop interconnection arrangement. U.S. Pat. No. 4,815,105 discloses a broadcast mechanism that operates via a transmission line telephone linear interconnection mechanism. Telephone exchanges use crossbar switches, but generally they do not use parallel-connected crossbar switches.

Several techniques have also been developed for multi-stage switching networks. U.S. Pat.No. 4,956,772
The specification discloses a buffered packet synchronous switch.
The disclosed complex single serial interface line switch requires data recovery capability. This requires complex prioritization built into each switch stage, and the broadcast command bits are put into that switch serially. Another packet switch for multi-stage switching networks is disclosed in U.S. Pat. No. 4,701,906. This is also a buffer sync packet switch and provides the initial connection interface. This puts a broadcast command bit in series with the switch, and this complex switch also requires data recovery capability. It is a single serial interface and does not take into account the need for an asynchronous byte wide parallel interface for broadcast operations.

Broadcasting a message from one device to N devices over a multi-stage network containing buffer switching devices is a relatively simple task,
At each switch the message is distributed to all switch outputs by putting it in a queue (ordered buffer) associated with each output. The sender of this broadcast message does not have to associate itself with contention at each switch output (ie, the output of a busy message that was previously initiated). If the output is busy, the broadcast message goes into the message queue, and if the output is available for use, the broadcast message will slowly propagate through the network. However,
There are three drawbacks to using a buffer network. That is, they are generally relatively slow, there is the problem of not being able to know when broadcasts come in, and when various receivers come in at very different times, and buffer networks generally have There is a need to synchronize between all transmitting and receiving devices and network switches. In synchronous systems, it is becoming increasingly difficult to meet the ever-increasing communication demands of modern parallel processing systems. These systems are not fast enough to keep pace with the rapidly increasing computer clock speeds, which is becoming a very risky problem.

[0009]

Non-buffered synchronous networks, on the other hand, can provide significantly improved speed with significantly lower complexity, risk and cost. However, one of the problems typically associated with unbuffered networks is the ability to broadcast multiple messages (ie, sending a message from one device to all devices connected to that network over a switching network). It is not.

Accordingly, the present invention provides a switching network that is capable of performing both broadcast and multicast transmissions through the network earlier, faster, in addition to the single transmission normally supported by the switching network. The purpose is to provide a system.

The present invention has a plurality of input ports and a plurality of output ports and is capable of operating in both a low priority mode having a low priority level and a high priority mode having a high priority level. In order to solve the conflict between the switch means capable of simultaneously forming a transmission path from any one of the plurality of output ports to one or more of the plurality of output ports and the switch means in the broadcast communication or the multicast, A switching system for a network comprising broadcast multicast means for giving different priority levels to input messages to each input port when operating in the priority mode.

In particular, the invention applies to byte-wide parallel hardware that uses parallel crossbar switches for byte-parallel multi-size interface switches for communication over multi-stage switching networks.

[0013]

This solution provides the usual advantages of broadcasting and multicasting over non-buffered networks, as well as comparing buffered networks so that the broadcast message is immediately propagated to all receivers. It gives a very advantageous broadcast communication capability of simultaneously entering. Further, the present invention allows a multicast priority to be queued at a switching device, thereby allowing one broadcast to follow another as soon as possible and at the maximum possible rate. Solving that broadcast line contention problem. Further, the present invention allows multiple multicast operations to occur simultaneously within the network.

US Patent Application No. 07 / 748,316 (filing date 1991
August 21, 2012 and No. 07 / 748,302 (filed on August 1, 1991)
21 March) The technology presented in the specification uses parallel connection crossbar switches for circuit switching networks for asynchronous, dedicated paths (no time slots), byte-width parallel direct connection switching, applicable to multi-stage networks It meets the need for improved switching network methods (non-loop or transmission line methods). This method of performing broadcast / multicast transfer over an unbuffered, asynchronous switching network is a non-buffered multi-stage network that supports only one broadcast at a time in the network and is able to use all of its functions. It solves the problem of simple low priority broadcasts in. This concept meets the needs of many low-end systems and provides an inexpensive and easy solution that does not require any clock signal to execute.

The present invention describes in more detail the simple asynchronous broadcast of conventional devices, and is more complex, faster and more output, which performs synchronous operation and requires a clock control signal for execution. Gives great broadcast and multicast capabilities. The present invention allows multiple broadcasts to be queued in a switching device and allows one broadcast to follow another as soon as possible and as fast as possible. Resolve broadcast conflicts in rank order. Further, the present invention allows multiple multicast operations to occur simultaneously in the network. This is becoming a feature of increasing importance for future parallel processors with many nodes that can be subdivided into many tasks.
In this type of environment, multicast becomes an even more important function than broadcast because not all processors need to communicate via broadcast. Rather, these needs are that subnodes designated for the same task communicate only with other nodes in the group. Multicast provides a solution for this type of communication. The present invention provides a network which can provide a very effective tool for future parallel applications by maintaining multiple multicasts simultaneously. The broadcast method of the present invention discloses U.S. patent application Ser. No. 07 / 800,652 (filing date 1991) which discloses a method for giving higher priority to the operation of a particular network than others.
27 November). This, on the other hand, is related to US patent application Ser. No. 07 / 677,543 (filed Mar. 29, 1991), which provides basic point-to-point transfer over the network. The present invention uses a high priority forwarding mode to achieve better implementation of broadcast and multicast functions, as well as a more capable mode, showing non-locking, non-buffering, asynchronous switching devices.

According to these objects of the invention, the functionality, interface lines and hardware are described in the above application No. 07.
In addition to the ALL-NODE switch shown in / 677,543, it further extends the priority broadcast and multicast functions from any element connected to the network.

According to the preferred embodiment, US Patent Application No. 07
The dual priority switching device shown in / 800,652 provides an unbuffered multi-stage network for interconnecting multiple system elements. The apparatus of the present invention with hardware added thereto provides a means for providing a priority broadcast or multicast function between these elements according to this embodiment.

It is a feature of this embodiment that a unique interface line for each element is provided to specify the operation of the priority broadcast or multicast mode. The system has the ability to handle one broadcast or multiple multicast operations at a time. Furthermore, this should normally be pending without refusing only the next attempt at broadcast or multicast when there is a conflict or blockade, and should be performed on a priority basis early after the conflict has subsided. ..

The present invention provides hardware circuits for common priority broadcast / multicast design functions that function equally at any stage of the network.

The present invention provides a hardware circuit for detecting and correcting deadlock conditions in a multi-stage network. Deadlock conditions are not expected to be normal conditions in a network, but can occur due to multiple simultaneous broadcasts or multicasts competing in the network in an unsolvable manner. This hardware circuit automatically detects all forms of deadlock conditions and issues a reject or retry indication on the network path. Network deadlock is thereby eliminated, and the two broadcasts or multicasts continue their operation with a reconstructed sequence that does not result in deadlock.

In addition, the device of the present invention has the ability to provide a positive feedback acknowledgment that connects to all commanded paths.
It is unique to each stage of the network.

[0022]

1 which illustrates a preferred switching device in detail, the switching device is a 4.times.4 crossbar switching device, from any of the four input ports to the four output ports. Operates to asynchronously send 4-bit data to anything in parallel. The switching device shown in FIG. 1 can cover up to four simultaneous connections at any given time. The switch can operate in either of two modes, a low priority mode and a high priority mode. The individual modes are described below.

1 to 4 show the aforementioned US patent application Ser. No. 07 / 677,5
It is the same as that used in No. 43, and the present invention is shown in FIG.
The logic and timing of the control signals as shown in FIGS.

As shown in FIG. 1, the switching device has a node having a plurality of input ports and output ports, including a connection control circuit for each input port and a multiplexer control circuit for each output port. There is. Given that I and Z are two or more unique values, any of the I inputs are connected to any of the Z outputs.

However, in accordance with the present invention, a dual priority or dual priority switch is provided to perform consistent operation in a multi-tier network. This switch allows two priorities and assigns different priority levels to each function so that each function can transmit over the same network path.

This embodiment is a 4 × 4 crossbar switching device, and the function of the present invention is to make any of the four input ports mutually exclusive and of any of the four unused output ports. It provides a means to connect things in order of priority.

In FIG. 1, a 4 × 4 crossbar switching device can cover up to four simultaneous connections at any given time. For example, input port 1 to output port 3, input port 2 to output port 4, input port 3
To output port 2 and input port 4 to output port 1
Can be connected to.

The switching device 10 is unidirectional, and data flows in only one direction from the input end to the output end of the switching device 10. This switching device 1
0 is unidirectional, but as shown in Figure 1, 4x4 ALL-
By connecting the NODE switching device 10, bidirectional communication between the four nodes 20, 22, 24, 26 is covered. Each node 20, 22, 24, 26 has two sets of unidirectional interconnect wiring, one set extending to switching device 10 and the other set extending from switching device 10. The dashed line inside the block of switching device 10 indicates that the functioning of this switching device can connect an input port, such as input port 1, to one of four output ports. The switching device 10 provides each input port with exactly the same function so that it can be connected to any unused output port. As shown in FIG. 2, the switch 12 has four data bit inputs and four control inputs. A new high priority (HI-PRI) interface control line is added to the basic ALL NODE switch to perform the new dual priority function. Furthermore, VA
There are LID control signal, REJECT control signal and ACCEPT line, and ACCEPT line becomes a mandatory line.

In FIG. 2, block 12 is an enlarged view of the switching device 10 and shows in detail the interface line connected to the switching device 10. The lines 31, 32, 33, 34 extending to the switching device 12 at each input port are
It is the same as the lines 41, 42, 43, 44 of each output port. These interface lines to each input and output port contain eight unique signals.
That is, four data lines and four control lines (VALI
D, REJECT, ACCEPT and HI-PRI), which are distinguished by a number indicating the direction and the order (X) following its associated input port (IN) or output port (OUT). The four data lines, the VALID line and the HI-PRI line have a signal flow in the direction from the input end to the output end through the switching device 12, and the REJECT control line and the ACCEPT control line have a signal flow in the opposite direction. Have.

Input port interface line 31,
Reference numerals 32, 33 and 34 transfer control information to the switching device 12 for the purpose of connecting a command and an input port to an output port therein. In addition, these port interface lines also carry data information to be transferred through the switching device 12 from the input port to the output port. Interface lines 31, 32, 3
The four data interface lines included in 3, 34 do not limit the data transfer through the switching device 12 to 4-bit information, and each of these four data lines transfers data of any size. It may contain a serial data string that enables it. For example, if all four data lines are transmitting serial data at 40 MHz, the data can be transferred at 160 Mbit / sec as a whole.

The switch interface sends dual priority data over this network as shown in FIG. 3 and requires only eight signals for control, which data transfer width is 1/2 byte ( 4 bits). These required signals are:

DATA: 4 parallel signals used to command switch connections and send data messages.

VALID: Indicates that one message is in the sending process when active. RESET when inactive
Show command and IDLE all switches
Reset to the state. All switch functions are reset except for high priority latches.

HI-PRI: When active, indicates that the message being processed is in high priority mode.

When inactive, issue the TERMINATE high priority command to reset all associated high priority latches. This line must be active during priority broadcast and multicast operations.

REJECT: This signal is a bidirectional interface signal only. The signal flow is in the opposite direction to the other six low priority transfer signals. When active for low priority transfers, this indicates that a REJECT condition has been detected.

When performing a broadcast or multicast operation for high priority operation, the signal flow is in the same direction as the data flow through this switch, and this signal occurs between different stages in this switching network. Used to correct deadlock conditions (deadlock type 2 condition).

ACCEPT: The signal flow is always the opposite of the other six signals. When in the zero state, a WAIT condition is detected, which indicates that a high priority connection cannot be made at this time. When high, indicates that the WAIT condition has ended and a commanded high priority connection has been made.

In FIG. 3, blocks 52 and 54 represent the general method of generating serial data in the form of messages that can be sent to and through the switching device 14. This is a partial view of the switching device 12. Serial data generation logic similar to that provided by blocks 52, 54 can be used at each of the other input ports to switching device 12. Each input data line group has the same clock signal (4 in FIG. 3).
4 synchronized data lines 3 controlled at 0 MHz)
The serial data is provided to one given input port which is synchronized to the same clock as it by the four shift registers 54 which produce serial data by shifting one. However, the four different input port sources 31, 32, 33, 34 to the switching device 14 may be asynchronous based on different unsynchronized 40 MHz clock signals.

The process of sending a serial message through the switching device 14 is a first in first out buffer (FIFO) 5
This FIFO 56 contains the data messages to be sent. The next message to be sent is sent to buffer 52. This message stored in the buffer 52 is sent to the shift register 54 in preparation for transmission, and the data is data bit 0 to the first bit of shift register 1 and data bit 1 to the first bit of shift register 2.
Bit, data bit 2 to the first bit of shift register 3, data bit 3 to the first bit of shift register 4, and data bit 4 to the second bit of shift register 1.
Bits are distributed through the four shift registers 54 by shifting in the same manner thereafter. The shift register 54 then begins sending serial data to the switching device 14 over four synchronized data lines in a continuous stream of data until the entire message has been sent. The switching device 14 uses the first 8 bits transmitted (from the serial register 54 to the switching device 14 during the first two clock cycles of serial data via the interface 31) to select the connection path through the switching device 14. The broken line in FIG. 3 temporarily connects the input port 1 (31) and the output port 2 (42) so that each of the seven lines in the interface 31 is unique to each of the corresponding lines of the interface 42. It also shows a switching device that allows direct connection.

FIG. 4 shows a method of increasing the number of nodes in one system by cascade-connecting blocks of eight switching devices 10. These eight switches 10A to 10H are the same as the switching device 10, respectively, and differ only in the connection of their input ports and output ports. It can be seen that any of the 16 nodes can communicate with any other node, with a connection through exactly two switch device blocks. For example, node 5 is node 1 via switches 10B and 10H.
You can send a message to 5. All connections are 2
A network having eight blocks of the switching device 10 is called a two-stage switching network because it is performed through the blocks of the switching device 10.
By using other multi-stage networks in the same manner with three or four stages, these switching device 10 blocks can be formed. The number of nodes that can be interconnected with this type of network can be very large, but for convenience of explanation, the network of FIG. 4 is the basis for the characteristics of the larger network, so This will be explained here.

In low priority mode, the switch can receive commands from each input port, commands coming in asynchronously, and connection requests to specific output ports. If the requested output port is available (NOT BUSY; ie, it is not used to support the connection by the previous command), that command is executed and the connection is made. If the output port is BUSY, the command is rejected and the input port returns to the IDLE state (that is, ready to accept the next incoming command). This connection refusal in the low priority mode is called a KILL operation. The reason is that if any part of a path were not created, all paths in this network would be broken, or "KILLED".

4 × 4 covered by individual switches
The switches can be cascaded to create a larger network than the interconnect configuration. FIG. 4 shows how to do this by connecting the output port from one switch to the input port of the second switch. In this large network, the first switch could make a VALID connection and the next switch could be BUSY, issuing REJECT. The REJECT indication is returned to the output port of the previous switch that already has a valid connection. In this case, the switch indicates its action by breaking its active connection and sending a REJECT signal to the previously connected input port. On the other hand,
The input port issues a REJECT to the source and returns to the IDLE state. This method is called KILL. The reason is that the REJECT sequence destroys all previously created connections,
Or because it becomes KILLED and everything in the KILL path is put back in an idle state. In addition, any part of the message that has started to be transmitted is completely lost or is made KILLED, and the message must be retransmitted from the beginning.

When two or more input ports simultaneously receive commands and compete for connection to the same NOT BUSY output port, the lower numbered input port wins,
Make the desired connections, the other input ports are rejected and their connections become KILLED. Therefore, the low priority path through this simple network is
It turns out that the function is used. If a rejection occurs anywhere in this path, the entire path is immediately destroyed and the message must be retransmitted from the beginning.

Messages to one destination, priority broadcasts and priority multicasts can all be transmitted by high priority paths through this network. This high-priority mode prohibits issuing a REJECT in response to a blocked connection, but instead, the connection (multiple broadcasts or multicasts may have more than one connection until the connection becomes available). I need)
Differs from the low priority mode in that it sets a special high priority hold latch that is now held by the switch. Then it immediately makes a pending connection and gives a positive feedback to the requester. This pending connection cannot be lost or lose its priority unless it is terminated by the message source or reordered by the deadlock fixer.

Instead of the REJECT response, this high priority mode issues a WAIT response when one connection cannot be made. This WAIT
The response involves zeroing the ACCEPT signal and maintaining its state for the duration of the WAIT condition. When a hold connection is made, ACCE
This is a positive indication that the PT signal has been driven to logic 1 and the WAIT state has ended. When the node requesting the connection detects a WAIT response, it temporarily stops sending the message, and when the WAIT condition goes away, it continues sending from where it left off. Thus, in high priority mode, the sending node will abort and continue when the ACCEPT signal occurs, rather than resending the blocked message from the beginning as in low priority mode. The timing is ACCEPT that the sending node will continue as soon as possible.
The indication is made to allow the high priority message to be sent at that time. Moreover, all stages before the blockage (winning the contention for the connection) are held for this WAIT period, without having to recreate it for an ongoing high priority message, broadcast or multicast. Thus, it guarantees the transfer of high priority destination messages and the transfer of broadcast or multicast messages at the earliest points.

If two or more high priority messages are waiting for the same output port to become available, the messages associated with the lower numbered input ports are connected first, while the others are in the snapshot register. Continue WAIT. After all requests waiting in the snapshot register have been processed, that register is made available to load higher priority requests again, if any. This snapshot register gives all requesters an equal chance of connecting to an output port before a given requester can be serviced a second time. Thus, it provides a way to prevent a requestor, given by a high-priority path through a network, from being completely blocked from that network, and also not to experience starvation. is there.

For large networks, the first switch makes a valid connection while the next switch is the WA
May detect IT conditions. In this case, the WAIT indication is sent in the reverse direction to the switch that did not disconnect the connection and simply forwards the WAIT condition in the reverse direction. This happens on all previously connected switches until the WAIT is completely returned to the message source.

All high priority paths can be reset for the source at any time by returning the HI-PRI signal to the zero state. This source has no ultimate control over this network.

FIG. 5 shows an example of a two stage network consisting of dual priority switches 10 supporting broadcast connections from node 3 to all 16 nodes. The first stage switching device 10A of this network forms a connection from an input port added to node 3 to four output ports. The fixed (non-switchable) wiring provides a connection path between the first and second stage switching devices 10. Second-stage switches 10E, 10F, 10G, 10
Each H connects its input port 1 to all its four output ports. In this way, the broadcast connection is established from the node 3 to all the nodes. Similarly, any input node to the first stage of the network may be connected for broadcast to all nodes. The switching device 10 provides a service for one broadcast connection at a time, although the high priority function allows another broadcast command to be sent to the switch. They are said to be switch pending and the next broadcast connection is made at the earliest point as soon as the previous connection is abandoned.

FIG. 6 shows an example of a typical priority multicast, showing how two different multicasts can exist in the same network. A multicast from node 7 to nodes 2, 4, 10 and 12 via a two-stage dual priority switch is shown at the same time as a second multicast from node 1 to nodes 5, 6, 13 and 14. The switching device 10B at the first stage of this network is the node 7
To form a connection from its input port to its first and third output ports. The fixed (non-switchable) wiring provides a connection path between the first and second stage switches 10. The second stage switches 10E and 10G connect their respective input ports 2 to their second and fourth output ports. In this way the desired multicast connection is created. Similarly, the input node 1 to the first stage of this network makes a connection to the output ports 2 and 4 and is then connected to the second stage nodes 5, 6, 13 and 14 for simultaneous multicast from node 7. , Or redundantly, the second multicast operation is performed. In general, multiple multicasts can be done simultaneously between different multicast operations unless there is a shared connection path. For example, the multicast of node 1 does not exist at the same time if it wants to multicast to node 5. That is, the node 5 is connected to the multicast of the node 7, and the connection cannot be shared simultaneously for two different operations. If there is a shared path, the high-priority mode is a priority type and resolves the conflict, and when the path becomes available, a new connection is immediately made to the shared path.

7 to 11 show the detailed logic of a part of the dual priority switching device 10. This portion creates one low priority or high priority data transfer connection between one input port (eg input port 1) and one output port (eg output port 1) of the 4 × 4 dual priority switching device 10. This is a typical circuit required for. Latches 70, 72, 7
No. 4,764 controls a normal low priority path, and their operation is how to make a low priority path and how to switch to KILLED when the connection of the switch becomes REJECT. No. 07 / 677,543.

This high priority path used for priority broadcast and multicast is added to the basic ALL NODE switch logic. High priority logic is latch 17
2, 174, block 140, and delay block 85
And gates 178, 182, 178, 95, 115,
The new interface control signals on all ports, such as IN1-HI-PRI on input port 1 and OUT1-HI-PRI on output port 1 as shown in FIGS. In addition, new circuitry has been added here that is specifically required to perform priority broadcast and multicast operations. They are gates 542 and 544 and logic function 54.
6 and 548. The functional behavior of all high priority logic elements, including priority broadcast and multicast operations, will now be detailed.

FIG. 12 shows the timing sequence generated at the node attached to input port 1 to send a priority broadcast operation. Figure 12 shows output port 1
5 shows the signal sequence used by input port 1 to command a priority broadcast connection of input port 1 via a dual priority switching device to ~ 4. In this operation, input port 1 is IN1-HI-PRI and IN1-VA
Start by bringing the LID interface control lines to logic 1 at the same time. This IN1-HI-PRI signal is shown in Fig. 7.
-11 high priority logic paths are turned on and their activation to a logic one causes resets of latches 172 and 174 to be released and operational. Gates 542 and 544 are used to completely turn off the low priority paths during priority broadcast and multicast operations. This occurs when the IN1-HI-PRI interface signal is activated to command execution of a high priority mode transfer. This IN1-HI-PRI signal is inverted by the gate 544, 0 is sent to the AND gate 542, and the AND gate 542 becomes 0, so the latches 74 and 7
Reset 6

As shown in FIG. 12, four command pulses 81A, 81B, 81C and 81D are generated next, which are IN1-DATA 1, IN1-DATA 2, IN1-DATA 3 and IN1-DATA, respectively.
4 Sent to input port 1 of interface line.
These four pulses are input port 1 to output ports 1 to 4
Command to make a high priority connection to. This command is active to identify that it is a high priority connection IN1-HI-PRI, IN1-DATA Pulse 81 that specifies that the connection on line 1 should be to output port 1
A, pulse on IN1-DATA 2 line 81B, IN1-DATA 3 specifying that the connection should be to output port 2
Identified by a pulse 81C specifying that the connection should be to output port 3 and a pulse 81D specifying that the connection should be to output port 4 on the IN1-DATA 4 line. It Broadcast communication is the maximum connection mode specified by these four pulses 81.
4 pulses 81 for single destination and multicast connections
, But not 1, 2, or 3 of the pulses 81 as a means of identifying a sub-portion of the maximum broadcast topology.

A representative example of the logical interpretation of the pulse 81 by this switch is set in the latch 172 at the rising edge of the pulse 81A in FIGS.
Pulse 8 on IN1-DATA 1 when set at the falling edge of A
It shows about 1A. When latch 174 is set, the dual priority switch will
Latches the receipt of a command to make a high priority (HI-PRI) connection from input port 1 to output port 1 specified by the M HI-PRI 11 signal. When the latch 172 is set, the PREHI-PRI 11 signal is activated, which activates the AND gate 95 to produce the WAIT 11 signal. Similar logic as shown in FIGS. 7-11 for output port 1 is used to create similar functions and signals for each of the other three output ports. These other 3
Typical timing for the WAIT signal from each of the groups of logic (not shown) is shown in FIG. These four
The WAIT signal generates pulses 401 to 404 based on the generation of the pulses 81A to 81D, respectively. These four WAIT signals are sent through NOR gate 115 where they are ORed and the result is inverted. The function of the gate 115 is that one of those four WAIT signals is a logic 1 to the gate 115.
Is to maintain the priority broadcast communication in the WAIT state. This composite WAIT signal (NOT IN from gate 115
1-WAIT) enters AND gate 182, where IN1-ACCE
Returned to node 1 via the PT line to produce pulse 71 as shown in FIG.

Pulse 71 provides an acknowledgment to input port 1 indicating when the commanded connection has been made. If any one of the four WAIT signals is active, the dual priority switch is waiting to make a connection, ie it has not yet succeeded in making a connection to all four output ports. If this connection is made to four ports, the four WAIT signals will be inactive, activating gate 115 and passing a logic 1 through gate 182, IN
It causes the 1-ACCEPT signal to rise, thus completing pulse 71 and providing positive feedback to input port 1 that the connection was made. Pulse 71 is pulses 81 and 71
Shows the fastest connection time when the connection is made at a high speed (within the width of the pulse 81) such that the pulse has the same width as the pulse 71 delayed by the path passing through the logic shown in FIGS. To get this fastest response, all four output ports must be available, and the very short WAIT as shown by the pulses 401-404 occurring at the same time.
It must accept this newly commanded broadcast connection immediately on a periodic basis.

COM HI-PRI 11 signal is also NOR gate 182
, Where other similar signals from other input ports are NOR'd, any of which pass through gate 180 and delay block 85 to make output port 1 BUSY.
Similarly, all other output ports are immediately busy during the broadcast operation. This causes all subsequent low priority requests to be denied during this broadcast.

The high priority connection to output port 1 is controlled by logic block 140. This block receives commands from latch 174 and similar latches associated with other input ports and determines the priority in which those connections should be. If it is determined to be the highest priority requester for input 1 or output 1, block 140 activates the "Enable HI-PRI 11" signal and notifies the dual priority switch to make a connection at this point. Details of the operation of the block 140 will be described with reference to FIGS. “Enable HI-PRI” activated as indicated by 207
The 11 "signal enters the AND gate 178 and the NOR gate 8
When a low priority connection to output port 1 is detected by a latch, such as latch 74 active through 0, further propagation is prohibited. However,
Normally NOR gate 80 is gate 178 with "Enable HI-
It does not block the PRI 11 ”signal and allows it to activate the“ HI-PRI 11 ”signal as soon as its low priority connection is broken. It does not allow priority connections, however, high priority operations do not destroy previously created low priority connections, pending high priority operations until a low priority operation releases the connection. The "PRI 11" signal is ORed with the low priority signal (LCONNECT 11) at gate 190 to generate a combined signal CONNECT 11 which causes the dual priority switch to make a high priority connection of input port 1 to output port 1. CONNECT 11 The signal is inverted at gate 192 and enters gate 95, deactivating the WAIT 11 signal once the connection is made.

The CONNECT 11 signal is also used to make a direct connection of the six interface lines between input port 1 and output port 1. The four data lines of input port 1 are connected to the four data lines of output port 1. Details of typical connections are shown by AND gate 122 and OR gate 130. With the CONNECT 11 signal active to AND gate 122, the output of AND gate 122 directly follows the value on IN1-DATA 1, which is O.
It is gated to OUT1-DATA 1 through R gate 130.
Another AND gate 12 providing the input of the OR gate 130
4, 126 and 128 are all set to logic 0 and the gate 13
0 has no effect. This is because normally one can be activated at the time a CONNECT signal is applied, thus allowing one connection to one particular output port. Therefore, CONNECT 11 is gate 122
CONNECT 21, CONNECT 31, and CONNECT 41 for gates 124, 126, and 128 must be inactive, respectively. Similarly, IN1-HI-PRI and IN1-
Input port 1 based on CONNECT 11 signal on VALID line
Is connected to the output port 1. A typical connection is shown for the IN1-HI-PRI line via gates 154 and 162. As a result, all six input signals at input port 1 are directly connected to the same signal at output port 1 and pass directly through the dual priority switch through only two gates, such as 154 and 162, and input port 1 The above pulse waveform is immediately generated on output port 1,
It is unbuffered to undergo the slight delay caused by the two gates (eg 154 and 162) passed through. Figure 1
There is one exception where the input port 1 of 2 differs from the output waveform. That is, pulse 81A is removed from the input waveform and stored in latch 174 and does not pass to output port 1. There are two reasons for this. Ie 1) by the time the CONNECT 11 signal becomes active, pulse 81A has already left and cannot pass to output port 1, and 2) pulse 81A identifies the first stage switch connection to be made, and This is because it has no other meaning and is therefore not desirable to pass pulse 81A further into the network.

In the priority broadcast communication operation, similar CONNECT signals (CONNECT 12, CONNECT 13, CONNECT 14) have the same input port interface signals (IN1-VALID, IN1-HI-PR).
I, IN1-DATA 1 to 4) are connected to the output ports 2, 3 and 4 as soon as they are available, and the input port 1 is broadcast to all four output ports via the dual priority switch. Used to make a communication connection.

2 from 4 output ports to input port 1
The feedback signals also have a connection made when the CONNECT 11 signal becomes active. AND gate 94, through NOR gate 92 and OR gate 90, shows CONNECT 11 selecting OUT1-REJECT as the source of the IN1-REJECT signal. ACCEPT signal from all four output ports is gate 1 respectively
04, 106, 108, 110 are entered and ANDed by the gate 102. An individual monitor of the four OUTX-ACCEPT signals generally enters the gate 104 with the corresponding CONNECT indicated by gate 192 which produces a NOT CONNECT 11 signal.
This is made possible by the inversion of the signal. Similarly, the REJECT signals from each output port are combined in gate 90 to provide one combined IN1-REJECT signal to input port 1.

In the multistage network, pulse 7 which is the output
1 indicates that the first stage in the network has made its broadcast connection. The next step is to connect the broadcast connection to the second-stage network switch IN1- as shown in Figs.
Commanding by issuing pulses 73A-73D to DATA1. This example assumes that in the two-stage network of FIG. 4, the second-stage switch logic is the same as the first-stage switch logic and the logic of FIGS. This second stage is commanded to make the same high priority connection of input port 1 to all four output ports as the first stage due to the presence of pulse 73 on all four IN1-DATA lines. The second stage switch does not receive the pulse 81 picked up by the first stage switch.

The events that occur in the second stage are similar to the events that previously occurred in the first stage switch. This operation is the second
Input port 1 is IN1-HI-PRI and IN1-VALID in the stage
Start by activating the interface control lines to logic 1 at the same time when they are connected via stage 1. This IN1-HI-PRI signal controls the high priority logic paths and also disables the low priority paths as was done in the first stage. Similarly, IN1- in the second stage
Activating HI-PRI to a logic one releases the reset of latches 172 and 174 and enables them.

Next, as shown in FIG. 12, a command pulse 73A occurs on the IN1-DATA 1 interface line, which commands input port 1 to make a high priority connection to output port 1. The pulse 73A on IN1-DATA 1 sets the latch 172 of the second stage switch on the rising edge of the pulse 73A and the latch 174 on its falling edge. With the latch 174 set, the dual priority switch will have COM HI-PRI 1
1 Latches receipt of a command for a high priority connection from input port 1 to output port 1 as defined by the signal. PR by the set latch 172
The EHI-PRI signal is activated, which activates the AND gate 95 to generate the WAIT 11 signal. Logic similar to that shown in FIGS. 7-11 for output port 1 is used to generate similar functions and signals for each of the other three output ports. FIG. 12 shows typical timings of the WAIT signal from each of these other three logic groups (not shown). 4 WAIT signals are pulses 73A-73
Pulses 405 to 408 are generated based on the generation of D, respectively. The different width pulses 405-408 represent an example of different length WAIT periods for making connections to each of the four output ports. That is, some of these output pulses are unresponsive in stage 1 as shown by pulses 401-404 at the earliest point in time and the previous connection is made so that the connection must wait until it is available. It is assumed that The four WAIT signals are passed through the NOR gate 115,
There it is ORed and the result is inverted. The function of the gate 115 is to keep priority broadcast communications in the WAIT state if any one of the four WAIT signals is a logic one for the gate 115. Synthesis from gate 115
The WAIT signal (NOT IN1-WAIT) is input to IN1- by AND gate 182.
It is returned to node 1 via the ACCEPT line to produce pulse 75 as shown in FIG. WA for Tier 2
IT 11 signal (pulse 405) is the last WAIT signal,
This is WAIT 1 even if the other 3 connections are created soon
The composite IN1-ACCEPT signal pulse 75 is delayed until 1 becomes 0.

At the time of pulse 209, "Enable HI-PRI 1
The 1 "signal is issued at block 140, which specifies the next connection from input port 1 to output port 1. The activated" Enable HI-PRI 11 "signal enters AND gate 178 and gate 190 has a low priority. Signal (LCONNECT 11) and OR
The combined signal CONNECT 11 is generated and causes the dual priority switch to make a connection from input port 1 to output port 1. CONNECT 11 signal is gate 1
It is inverted at 92 and enters gate 95 where it deactivates the WAIT11 signal (as shown at the end of pulse 405).

From FIG. 5, in order to make one broadcast connection for all 16 nodes, four stage 2 switches must be created that are similar to the switch in stage 2 above. Note that there are 10E-10H. All four stage 2 switches have the same function as the stage 2 switches described above, and receive the exact same interface signals as when spread in broadcast mode by the first stage switch. However, four second stage switches 10
Each of E-10H may have a different WAIT time for making their broadcast connection. Individual waiting time is signal
OUT1-ACCEPT, OUT2-ACCEPT, OUT3-ACCEPT, OUT4-ACC
The EPTs are returned to the first stage switch via individual ACCEPT lines, one for each output port, as shown in FIG. Each OUTX-ACCEPT signal from the first stage is connected to a different IN1-ACCEPT signal from the second stage switches 10E-10H. The four second stage switches pass this ACCEPT indication to the first stage switch 10A, which
IN1-ACCEPT signal indication immediately on node 1
Send to. The switch 10A has individual OR gates 104,1.
After passing through 06, 108 and 110, all ACCEPT signals received at its four output ports are logically "ANDed" as shown by AND gate 102 in FIG. Gates 104-110 are used in connection with one destination or multicast operation to ensure that the transfer-insensitive second stage switch does not affect the composite ACCEPT signal generated by gate 102. However,
Regarding the broadcast communication operation, gates 104, 106, 10
8,110 all gate 4 ACCEPT signals
Is preconditioned to pass directly through. In this way, the gate 102 collects all the WAIT signals from the four second-stage switches and performs an AND logic operation (ANDS) thereof. The wait time in this switch is indicated by the WAIT signal of logic 1, which is 0. Interface line INX-ACCE
Standby via PT to show outside of this switch, 1 WA
The IT signal indicates that all connections have been made. Gate 102 of stage 1 forms a composite ACCEPT signal based on the values of the four OUTX-ACCEPT signals received (these are directly connected to the INX-ACCEPT signals from the four second stage switches). As a result, the gates 102 cannot be activated until they report that the four second stage switches have made connections to all four of their associated output ports. If any one of the four inputs of gate 102 is 0 (indicating a wait), the output of gate 102 is 0.
Node 1 via the IN1-ACCEPT line from tier 1
Return 0 to. At this time, the pulse 75 remains in the 0 state. However, when the four inputs of gate 102 return to the 1 state, indicating that 16 broadcast connections have been made, the output of gate 102 goes to 1 to set IN1-ACCEPT to 1 and pulse 75 ends. Let Pulse 75 gives an acknowledgment that all 16 connections of the second stage were made. One activation for AND processing of ACCEPT signal
The ACCEPT signal must be sent from all receiving nodes attached to the output port of each broadcast / switch stage before the ACCEPT signal is sent to the previous broadcast / switch stage or node 3. Node 3, knowing that the ACCEPT signal is active, will get positive feedback indicating an indication that all 16 node transfers have been completed. Node 3 then broadcasts its IN3-BRDCAS to switch 10A.
T, IN3-VALID, 4 IN3-DATA lines are reset to 0, the broadcast communication is terminated and the interface is ID
Return to LE state. IN3-BR becomes 0 at clock point n + 3
The DCAST and IN3-VALID input lines cause input port 3 of broadcast switch 10A to disconnect to its four output ports and put them in the IDLE state. Immediately thereafter, the broadcast switches 10E, 10F, 10G, and 10H learn that their IN1-BRDCAST and IN1-VALID input lines have become 0, cut off their connections to their four output ports, and switch them to IDLE. Return to the state. In this way, these connections can be broken and the broadcast / switch can be returned to IDLE within one clock time. If node 3 has another broadcast or non-broadcast message to transmit, it will send it to buffer 52 and shift register 54.
(FIGS. 7 to 11), transmission is started at clock time point n + 4. The only condition is that the VALID signal generated at node 3 must return to 0 for a minimum of one clock time (time point n + 3) before the start of another transmission to indicate the end of the previous transmission.

This completes the high priority broadcast connection via both stages of the two stage network. These path connections are made here as shown in FIG. 12 so that MESSAGE DATA can be broadcast to all of nodes 1-16 at the same time. As a result, the high priority command is stored in the associated switch stage and is built up in priority order as soon as the required output ports are available, thus creating a high priority path at maximum speed. In addition, the completion of the connection provides positive feedback to the node making the connection immediately, and therefore at the earliest point.

After the MESSAGE DATA has been broadcast to all nodes, all receiving nodes can check the accuracy in their messages using the selected error detection method (parity method, CRC method, etc.). I can. If this message is received correctly, each receiving node
Responding to the second stage switches 10E to 10H in the network shown in FIG. 5 by activating the ACCEPT signal. The second stage switch returns this ACCEPT indication to the first stage switch 10A, which immediately returns it to node 1. Each switch 10A and 10E-10
H logically "ANDS" s all of the ACCEPT signals received from its four output ports as shown by AND gate 102 in FIGS. This ANDing of the ACCEPT signal must send the active ACCEPT signal to all receiving nodes attached to the output port of each switch 10E-10H before sending it to the first switch stage 10A or node 1. In order for this ACCEPT function to work correctly in multicast mode, the switch should make the ACCEPT interface lines from all output ports that are not associated with transmission (NOT) logical 1 and correct from the associated node.
It shall not prevent the transmission of ACCEPT indications. This is done internally to switch 10 by respective gates 104, 106, 108, 110 for output ports 1-4. Thus, the AND gate 102 in each switch 10 (10A and 10E-10H) may be of any type of command, i.e., broadcast,
Properly pass ACCEPT feedback indication for multicast or single destination. AC
When node 1 knows that the CEPT signal is active (the end of pulse 79), it gets positive feedback that the transfer to all selected nodes is complete. Node 1 then resets IN1-HI-PRI, IN1-VALID and the four IN1-DATA lines to its switch 10A to 0, terminates the broadcast and returns the interface to the IDLE state.

According to the present invention, in this network 2
Two new functional blocks are shown in FIGS. 7-11 to handle two different types of deadlock conditions (type 1 and type 2) that can occur when attempting to perform the above priority broadcast or multicast operations simultaneously. 546 and 54
8 is added. Details of blocks 546 and 548 are described below with respect to FIGS.

High priority execution of broadcast and multicast operations and their prioritization are functions provided by block 140 shown in FIGS. 13 and 14. Representative logic is shown for making a high priority connection from input port 1 to output port 1 by means of latches 252 and 254 in association with gates 250 and 258 and delay block 257. The same logic is shown to make a high priority connection from input port 2 to output port 1 by means of latches 262, 264 associated with gates 260, 266, 268 and delay block 267. Gates 270,2
76, 278 and delay block 277 associated with latches 272, 274 from input port 3 to output port 1
The same logic for making a high priority connection to is shown.
The same logic is shown to make a high priority connection from input port 4 to output port 1 by means of latches 282, 284 associated with gates 280, 286, 288 and delay block 287.

Block 140 requires sequential logic operations and decisions that require a clock signal. This is the first clock in need of this ALL NODE switch concept. The clock used in FIGS. 13 and 14 is 40 MHz as an example, but the clock frequency is generally determined by the implementation technique.

To use the example of input port 1 commanding the high priority connection to output port 1 described above for the functions shown in FIGS. 13 and 14 performed in block 140, and to show it the priority function. A simultaneous request from the input port 2 for commanding a high priority connection to the output port 1 will be described. “COM HI-PRI 11” signal and “COM HI-P”
The RI 21 "signal provides this information to block 140 by activating this information to latch 252, where it is 40
Resynchronized to MHz. Latch 252 is enabled by the IN1-HI-PRI signal on its reset line and functions when input port 1 is operating in the high priority mode. The rat 252 is set to IN1-HI-PE when the "COM HI-PRI 11" signal becomes active in synchronization with the rising edge of the 40 MHz clock signal as shown in the timing chart of FIG.
Generate the NDING signal. Latch 252 set indicates that input port 1 has a pending high priority connection to output port 1. The purpose of the logic of block 140 is to record this pending command and make its desired connection based on priority at the earliest time. The Q output of the latch 252 is its S
After being set for the first time after being fed back to the ET input, the IN1-HI-PRI signal maintains its set state until it becomes inactive at the reset input of the latch, causing it to reset.

Latches 254, 264, 274 and 284 are 4-bit snapshot registers (SNAP SHOT REGIST).
ER), which allows all pending connections to be made based on rotation priority, and prevents individual users from monopolizing one output port connection, and other users who cannot make the desired connection. It is intended to prevent the detour. The snapshot register can only "snapshot" at specific intervals to determine which connection is pending. This “snapshot” interval is defined by AND gate 300. This gate is connected to the snapshot register as registers 252, 262, 272, 2
A clock signal is provided which causes the pending connection request from 82 to be sampled. This clocking of the snapshot register does not set any bit in the snapshot register and output port 1 gates 32
Occurs as defined by gate 300 at 40 MHz when marked OUT1-NOT CONNECTED from 0 as not in use. Basically the snapshot register is 40 unless output port 1 has a current connection to it and there is no active bit in the snapshot register.
Clocked in MHz.

FIG. 15 shows the timing of the snapshot register when input ports 1 and 2 issue a pending high priority command for connection to output port 1; output port 1 is 0 OUT1-NOT CONNECTED The signal 302 is occupied by the previous low priority connection. Figure 1
5 is IN1-HI PENDING and IN2-HI PENDING in this case
Latches 254 and 264 are set to indicate that output port 1 is waiting for it to become available. Pulse time 30
At 1, output port 1 terminates its previous connection and is ready for use. Assuming the snapshot register does not have the preset bit set, the CLOCK snap shot register
The signal becomes active and the next 40 MH after pulse 301
The pulse 303 is generated during the period corresponding to the z clock signal. Pulse 303 enters all of the bits of the snapshot register and latches them into latches 252, 262, respectively.
The states corresponding to the states 272 and 282 are set. In this example, both snap shot register latches 254 and 264 are set at this time. This will enable "Enable HI-PRI
11 ”signal is 10ns due to block 275 and gate 258
Becomes active after a delay of. This issues pulse 305 to select input port 1 to connect to output port 1 next. Even if the rat 264 sets with pulse 303,
The able HI-PRI 21 "signal is not active at the same time as pulse 305. That is, gate 266 prevents this from happening because the" NOT Enable HI-PRI 11 "signal is now 0.

After input port 1 sends its message to output port 1, input port 1 makes its connection to output port 1 by deactivating the IN1-HI-PRI signal as shown in FIG. Disconnect that connection. This is the other COM HI-P
Resets RI 11, IN1-HI PENDING, and ENABLE HI-PRI11 (1 bit of snapshot register).
At this point, only latch 264 remains set in the snapshot register, and gate 266 provides delay block 267 with "ENABLE HI-PRI21" signal 268.
After ns, the pulse 307 of FIG. 15 is made active and is then enabled to pass an indication that causes input port 2 to be selected to be connected to output port 1. After the input port 2 sends the message to the output port 1, the input port 2 receives its IN2-HI-PR as shown in FIG.
Deactivating the I signal disconnects its output port 1. On the other hand, this is COM HI-PRI21, IN2-HI P
Reset ENDING and ENABLE HI-PRI21 (by resetting one bit in the snapshot register). Output port 1 then services all of its pending connections, causing the CLOCK snap shot register signal 300 to pulse such as 309 and 311 for snap shots.
Restart the clock operation of the register latch, and this continues until output port 1 is reconnected or another high priority operation is latched in the snapshot register.

Delay blocks 257, 267, 277, 2
The purpose of 87 is to prevent one connection from immediately following another so that no errors occur before the interface signals settle.

The gates 250, 260, 270 and 280 are not reset by the rat in the snapshot register.
IN1-HI-PRI, NOT RESET IN2-HI-PRI, NOT RESET IN
3-HI-PRI, NOT RESET IN 4-Enables individual reset by HI-PRI signal. These signals are unique to broadcast and multicast operations and are used to correct deadlock conditions. Deadlock is Figure 1
It can occur in the network in two different environment types, as shown in FIG.

The first deadlock condition called type 1 occurs within one switch as shown inside switch 10A in FIG. An example of deadlock type 1 is shown, which assumes that nodes 1 and 4 are attempting multicast at the same time. Node 1 is a multicast to the output ports 2, 3 and 4 of switch 10A, with immediate success on output ports 2 and 4 as shown by the connecting line from input port 1 to the interior of switch 10A. However, node 1 cannot complete the multicast connection because it cannot get it to output port 3. The node 4 is the output port 1, 2, 3 of the switch 10A.
Multicast to input port 4 to switch 1
Output ports 1 and 3 can be connected immediately, as indicated by the connection line to the interior of 0A. However node 4
Cannot complete its multicast connection because it cannot connect to output port 2. Nodes 1 and 4 deadlock in this example and cannot solve this problem by themselves. Node 1 has a connection to output port 2,
It does not release it until a connection to output port 3 is available. However, node 4 has a connection to output port 3, which does not release it until it gets a connection to output port 2. This problem is due to a race condition between two multicast operations coming from different nodes at about the same time. This causes the two sets of snap shot registers (FIG. 9) associated with input ports 4 and 1 to be out of sync with each other and to prioritize which input port gets output ports 2 and 3. It will not match. That is, the node 1 is given the highest priority for the connection to the output port 2, and the node 4 is given the highest priority for the connection to the output port 3. If these decisions are consistent,
For example, if the highest priority for both output ports 2 and 3 is given to the node first, then there is no problem. That is, the deadlock is avoided because node 1 is first and node 4 is second. Therefore, to solve this problem it is necessary to detect deadlock conditions and re-prioritize them to match the relevant snapshot registers.
The operation at this time flows sequentially without causing deadlock. This modification involves removing the mismatched priorities from the snapshot registers and recalculating the priorities to match across the various snapshot registers. In this way, the gates 250, 260, 27
0, 280 are used in FIG. 9 to reset the respective latches 254, 264, 274, 284 in the snapshot register based on the respective resets from the deadlock detection and correction logic. This decision is based on the priority decision that a match was detected and caused by a deadlock. This mismatch priority determination is individually reset from one latch in the snapshot register. This reset is done by latches 252, 262, 27.
2, 282 will not be entered, and these latches will not be reset and will continue to hold the pending connections at that switch. The priority is changed only by resetting one bit in the snapshot register, this behavior is not lost or affected otherwise. For example, in this example, the first highest priority for connecting to output port 3 is input port 4. Latch 2 that gives the highest priority to the input port when deadlock is detected
84 is reset. Then the priority to output port 3 is recalculated and input port 1 gets a connection to output port 3. This allows the input port to make all of its multicast connections, and this operation proceeds to completion. After the multicast on input port 1 is complete, input port 4 gets its required connection and completes its operation.

Deadlock type 1 cannot occur for single destination high priority connections. However, in broadcast or multicast operation this can occur because one input port must get a connection to 2, 3 or 4 output ports in the same switch. With two-destination multicasts, deadlocks can only occur when two other multicasts point to exactly the same two output ports, one of which gets one of the ports and the other gets the other. The example of switch 10A in FIG. 16 shows how deadlock can occur with simultaneous multicast to three or four output ports in a given switch. In the case of type 1, deadlock can be detected immediately and corrected immediately without significant delay in transmission.

The logic required to detect and correct type 1 deadlock conditions is shown in FIG. AND gate 600 represents the combinatorial logic for detecting the deadlock example shown in switch 10A of FIG. This detection is a signal ENABLE H that limits the created multicast connection.
A WA that limits the output of snapshot registers such as I-PRI12 etc. and the multicast connection you are trying to make
Based on IT signal. In this case, the gate 600 connects the input port 1 to the output ports 2 and 4 and the input port 4
Indicates that a connection has been made to output ports 1 and 3 from, but not waiting to make a deadlock connection from 1 to 3 and from 4 to 2.
The combinational logic at block 604 is input ports 1 and 4
It consists of a gate similar to gate 600 which detects other combinations of multicasts that require 2, 3 and 4 connections which may result in similar deadlock conditions during. O
R-gate 602 performs a logical OR of all possible type 1 deadlock conditions and indicates that a type 1 deadlog has been detected between input ports 1 and 4.
Generates IN1 & 4 signals. Gates 600,602,60
Logic similar to 4 has 2 of 1 out of 4 input ports
It is used to detect deadlock conditions between individual combinations. NOR at those gates whose results combine all resets to the snapshot register associated with one given port, such as gates 606 and 608.
It is processed. For example, gate 606 incorporates those resets into all snapshot registers associated with input port 4. That is, it controls the deadlock reset between input ports 1 and 4, between 2 and 4, and between 3 and 4. One additional input to gate 606 (IN4-
REJECT) is included. This input is a modified reset for Type 2 deadlock conditions. Thus, the type 2 deadlock condition provides the exact same correction algorithm used for the type 1 deadlock condition. Output of gate 606 (NOT RESET IN4-HI
-PRI) enters the AND gate 280 in the snapshot register of FIG. 9 causing the latch 284 to reset. When the latch 284 becomes 0, the signal EN
ABLE HI-PRI 41 and ENABLE HI-PRI 43 (not shown) go to 0, removing those conditions from gate 600. In this way, the deadlock condition is eliminated, which causes gates 600 and 602 to go to zero and the deadlock correction signal (NO
T RESET IN4-HI PRI) is removed. After that, normal operation will continue. Type 1 deadlock detection and correction occurs within one switch 10 and has no effect on other switches within the network or changes in the propagation of multicast or broadcast operations over that network. Do not cause.

The second deadlock condition of type 2 occurs between two adjacent stages of one multistage network as shown in FIG. An example of type 2 deadlock is shown where nodes 7 and 15 are attempting to multicast at the same time. Node 7 is switch 10C,
Multicast to 10E, 10F, 10G, and switches 10C, 10 as shown by the connecting lines in FIG.
In F and 10G, the required connection is immediately obtained. However, the node 7 cannot complete the multicast connection because it cannot obtain the connection necessary for the switch 10E. The node 15 includes switches 10D, 10E,
Multicast to 10G and 10H, switch 10
For D, 10E, and 10H, the connection was immediately obtained as shown by the connection line in FIG. 16, but the switch 10G was not obtained, so that the multicast connection cannot be completed. Nodes 7 and 15 are deadlocked and cannot solve this problem by themselves. Node 7 is switch 10
It does not release the connection to G until it gets a connection to switch 10E, and node 15 does not release the connection to 10E until it gets a connection to switch 10G. Solving this problem is more difficult than Type 1 deadlocks.
That is, it may span several or many switch chips in two adjacent network stages. The modification requires removing the non-matching priorities created in the second stage switches. However, it is difficult to detect it with the second stage switch. In other words, it is not possible to detect that deadlock has occurred because what each switch does is to determine the matching priority. Therefore, this problem must be detected by the first stage switch which can detect that the multicast operation is not being processed as it should be done in the next stage. After the first stage detects this problem, it issues a correction signal to the second stage switch to re-prioritize and eliminate the deadlock condition. Similar to the elimination of Type 1 deadlocks, this modification occurs without terminating or altering the propagation of multicast or broadcast operations over the network.

The logic required to detect and correct a Type 2 deadlock condition is shown in FIGS. 18 and 19, where all of this logic is the first stage switch 1
It is supposed to be included in 0D. However, this logic would mean that the second stage switch for larger networks would have to detect and correct similar deadlocks associated with the third stage switch.
All switches 1 regardless of the network stage
It is within 0.

Switch 10D detects the occurrence of a Type 2 deadlock condition using the indication returned from the second stage switch via the OUT X-ACCEPT line.
20 and 21 show the timing of a multicast operation from node 15 of FIG. 16 that has experienced a type 2 deadlock. This timing shows that the first stage connection at switch 10D is made easily and without contention via the command entering pulse 81. At this time, the node 15 is connected to the IN X-ACCEPT line from the switch 10D,
A pulse 71 indicating that all three connections of the first stage have been made and cannot be broken for any reason other than the end of the operation commanded by node 15.
Receive. At this time, node 15 issues a pulse 73 commanding the connection to the second stage switch, causing pulse 75 to go to zero accordingly. This is a composite of the OUT x-ACCEPT pulses entered from the four switches in the second stage and output to gate 102 of FIG. When each switch in the second stage makes a commanded connection, it is associated with the signal IN
First stage switch 10 by starting X-ACCEPT
Let D know. This signal is OUT x-ACCE of switch 10D.
It is directly connected to the PT signal. OUT x- to switch 10D
The ACCEPT of 0 informs the first stage switch 10D that the commanded connection to be made to the second stage via the output port of stage 1 is pending and has not yet been made. OUT x-ACCEPT to switch 10D is 1
To inform the first stage switch 10D that the commanded connection to be made to the second stage has been made via the first stage output port.

In FIGS. 20 and 21, the OUT2-ACCEPT signal from the second stage switch 10F is the switch 10F.
It remains a logic 1 because there is no commanded connection to be made at, so a OUT2-ACCEPT of 1 completes that commanded connection (none). OUT3
-ACCEPT indicates that by completing the connection and ending pulse 407. OUT4-ACCEPT is shown to be slower, but completes the connection and pulse 4
This is indicated by ending 08. OUT1-ACCEP
T indicates that it is impossible to complete the connection at switch 10E under a type 2 deadlock condition, so pulse 405 is held zero and the required connection is not made. The switch 10D detects the timeout of the type 2 deadlock. This initiates a timeout countdown after at least one output port reports a connection complete and at least one output port reports its failure.

18 and 19 show exemplary logic used to detect a type 2 deadlock by monitoring OUTX-ACCEPT, which logic is indicated by block 546 in FIG. . Each OU
The TX-ACCEPT line is monitored by the same logic represented by gates 104, 500, 506, 508 and latches 502, 504 for monitoring OUT1-ACCEPT. The type 104 gate (also shown in FIG. 7) only allows monitoring of the associated OUTX-ACCEPT signal in supporting a valid connection. With a valid connection from input port 1 to output port 1, gate 1 reproduces the waveform applied to OUT1-ACCEPT. When the OUTX-ACCEPT signal falls and shows that the connection is pending in the next round,
Latch 502 is set to record its first occurrence. Latch 502 is ENABLE HI-PRI 11 to gate 500
It can only be set in the high priority mode of operation indicated by the signal, which holds latches 502 and 504 in the reset state when there is no high priority operation in progress.
The gate 506 detects the rising edge of the OUT1-AACCEPT signal indicating that the commanded connection has been made in the second stage switch 10E connected to the output port 1 of the first stage switch. The first fall of OUT1-ACCEPT before this first rise sets latch 504 to indicate that one switch in the next stage has performed the task of making its commanded connection. . This logic is OUT1
-Works only for the first pulse of the ACCEPT signal, latches 502 and 504 normally remain set, so that this switch only activates these latches once to detect deadlock in the next stage. become.
This logic is not valid for subsequent stages of the larger network. That is, the same function as in the second stage switch detects a Type 2 deadlock condition in the third stage and the first stage deadlock detection logic remains dormant.

Gate 522 makes one of the switches in the next stage its connection, as indicated by the active NEXT DONE 11 signal from latch 504, and some switches in the second stage still make that connection. Detects no conditions.
This is detected by the ORing of a signal such as NOT DONE 14 from gate 518 indicating that a connection has been commanded between input port 1 and output port 4, but OUT4-ACCEPT indicates completion of the connection. . OR gate 536 ORs all conditions similar to those detected by gate 522 or provides the state of the other output port. OR like this
The output of gate 536 is active during high priority operation when some of the connections in the second stage of this network are made and some are not. The output of the activated OR gate is delayed at block 540 and is used to start and enable the timeout counter 538.

20 and 21, OUT3-ACCEPT in this example first shows the completed connection to the second stage switch on the rising edge of pulse 407 to relate the timeout counter to the deadlock timing diagram. At the rising edge of pulse 407, pulse 405 is still zero.
This is in line with the indication that some connections in the second stage are made and some are still pending. This detection starts the timeout counter 538 via the OR gate 536 and the delay block 540 (pulse 40
9). If the deadlock indication detected at gate 536 remains active for a certain amount of time (due to the timeout counter), then the suspicion is confirmed and it is classified and detected as a Type 2 deadlock condition. This is TIME in Figures 18 and 19.
-OUT IN1 Occurs when the signal becomes active, indicating that this particular time interval has passed. The output of counter 538 is gated by the appropriate high priority enable signal in gates 541-544 to send a correction signal to the output port associated with the multicast or broadcast operation. This modification signal is sent to all of the second stage switches involved in the multicast or broadcast regardless of whether a connection is made. This correction signal is applied to the first stage switch 10
Now switch 10 from D to OUTX-REJECT line
Pulse 4 sent to the second stage switch connected to D
Twenty. Pulse 420 is issued on the OUTX-REJECT line which is not used during the high priority setup time.
Gate 541 to Type 2 deadlock logic (Dead
lock Type2 Logic Block) OUT1-R from block 546
Figure 7 shows the path to the EJECT signal. This reject pulse 420 to each switch in the second stage enters via the INX-REJECT line and is directed to a Deadlock Type1 Logic Block 548 as shown in FIG. With type 1 deadlock logic in the second stage
IN X-REJECT signal is type 1 at gate like 608
NOR-processed with those of the deadlock. Thus a type 2 deadlock indication is sent from the previous stage via the REJECT interface line connecting the two stages to the second stage switch, and the type 1 dead detected in its own switch. Causes the high-priority operations to be reordered as if the lock conditions were done.
The internal deadlock correction signal, ie, the output of the gate 606 (NOT RESET IN4-HI-PRI) enters the AND gate 280 in the snapshot register of FIG.
To reset. Thus the deadlock condition is eliminated by the reordering of the high priority operations, which causes the second
The priority is matched through the switches of the stages.

The size of the pulse 420 appearing on the OUTX-REJECT line is controlled by the logic that generated the pulse. In FIG. 18 and FIG. 19, the output of the gate 541 that generates and sends the pulse 420 is inverted by the gate 550 and AND
It is sent to gate 500 where it is used to reset latches 502 and 504 under abnormal conditions that detect type 2 deadlocks. When the latch 504 is reset, the gate 536 is first activated to set the conditions for enabling the time-out to the gates 522, 526, and 5.
Remove from 30,534. This disables the timeout counter 538 after a delay by block 540 and terminates the pulse 420. Thus, the time of the delay block controls the width of pulse 420. After detecting the deadlock, the latches 502 and 504 again monitor the first occurrence of the corresponding OUT-ACCEPT pulse, and the second stage resumes checking if those conditions are correctly constructed. 20 and 21 show pulse 42
5,427,428 shows that now all second stage connections are correctly created and that MESSAGE DATA signals can be transferred in a multicast fashion. These conditions are to activate the OR gate 536 for the second time and restart the counting of the timeout counter 538. However, at this time, the required connection is made before the counter 538 times out.
The connection being made causes the OR gate 536 to go to 0, resetting the counter 538 before the timeout.

FIGS. 7-11, FIGS. 13, 14, 17, and 18 and 19 show typical circuits required in a dual priority switch. . It is necessary to add these functions in order to totally define all the input ports connected to all the output ports. However, the method is an obvious extension of what is shown and need not be shown here.

[0091]

According to the present invention, in addition to the single transmission normally supported by a switching network, both broadcast and multicast transmissions through that network can be performed earlier and faster. A switching system for networks can be provided.

[Brief description of drawings]

FIG. 1 illustrates an embodiment of a four-input (4 × 4) crossbar switch device according to the present invention having a control line for handling dual priority selection within the switch.

FIG. 2 shows details of the 4 × 4 crossbar switch device of FIG. 1 and its interface connections including novel HI-PRI interface lines provided on each input and output port to control its dual priority mode. Fig.

FIG. 3 shows a method for generating serial data information to be sent to a part of the present invention via four data lines.

FIG. 4 is a diagram showing a method of cascading this 4 × 4 switching device into a multi-stage network to form a system having 5 or more nodes.

FIG. 5 is a representative priority broadcast example showing how node 3 broadcasts to all 16 nodes through two stages of a dual priority switch over a high priority path. FIG.

FIG. 6 shows a node 2 from a node 7 via two dual priority switch stages in the same network.
4, 10, 12 and from node 1 to nodes 5, 6,
The figure which shows the example of the typical priority multicast in which two different multicasts are simultaneously performed to 13 and 14.

FIG. 7 is an example of a dual priority switch used to create a high priority path between a given input port and a given output port of a dual priority switch for high priority broadcast and multicast. FIG. 6 illustrates an example and special deadlock detection and correction logic required to perform priority broadcast and multicast operations. FIG. 12 is a partial view which completes one drawing together with FIGS. 8 to 11, FIG. 8 being connected to the right and FIG.
Are connected.

FIG. 8 is a view similar to FIG. 7. FIG. 12 is a partial view that completes one figure together with FIG. 7 and FIGS. 9 to 11, with FIG. 7 connecting to the left and FIG. 10 connecting below.

FIG. 9 is a view similar to FIG. 7. FIG. 12 is a partial view which completes one drawing together with FIGS. 7, 8, 10 and 11, wherein FIG. 7 is connected to the top and FIG. 10 is connected to the right.

FIG. 10 is a view similar to FIG. 7. FIG. 12 is a partial view that completes one drawing together with FIGS. 7 to 9 and FIG. 11, where FIG. 8 is connected to the top, FIG. 9 is connected to the left, and FIG. 11 is connected to the right.

11 is a view similar to FIG. 7. FIG. 7 is a partial view that completes one drawing together with FIGS. 7 to 10, and FIG. 10 is connected to the left.

FIG. 12 is a dual priority switch 2
FIG. 6 is a timing diagram showing how to sequentially create high priority broadcast and multicast paths at the first available time through a multi-tiered network.

FIG. 13 is a diagram showing a high-priority function logic including a snapshot register and a register clock and a high-priority pending logic, which is a partial view which completes one figure together with FIG. Link.

FIG. 14 is a view similar to FIG. FIG. 14 is a partial view which completes one drawing together with FIG. 13, and FIG.

FIG. 15 is a timing diagram illustrating an example of snapshot register timing and a method of sequentially servicing multiple requests at the earliest time based on embedded priority.

FIG. 16: 2 consisting of dual priority switches
FIG. 3 is a diagram showing two different types of deadlock conditions (type 1 and type 2) that can occur when performing priority broadcast or multicast over a tiered network.

FIG. 17 is a diagram showing logic for detecting and correcting a type 1 deadlock condition.

FIG. 18 is a diagram showing logic for detecting and correcting a type 2 deadlock condition. It is a partial view which completes one figure with FIG. 19, and FIG. 19 is connected on the right.

FIG. 19 is a view similar to FIG. 18. FIG. 19 is a partial view that completes one drawing together with FIG. 18, and FIG. 18 is connected to the left.

FIG. 20 is a timing diagram showing an example of detection and correction of a type 2 deadlock condition and transfer after correction. FIG. 22 is a partial view which completes one drawing together with FIG. 21, and FIG. 21 is connected below.

FIG. 21 is a view similar to FIG. 20. FIG. 21 is a partial view which completes one drawing together with FIG. 20, and FIG.

[Explanation of symbols]

 10 4 × 4 dual priority switch 20, 22, 24, 26 nodes

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventors Peter, Michael, Kogge, New York, USA Endicott, Dorchester, Drive, 7 (72) Inventors Gilbert, Clyde, Bundling, The, Third Endy, New York, USA Cot, East, Campville, Rhode, 1255 (56) References JP-A-60-232743 (JP, A) JP-A-62-503208 (JP, A) 7th Annual Joint on the IE IE Computer and Com communications Society (1988-3-27) (US) "The Architure of a Mulicast" roadband P acket Switch "p. 1-8

Claims (11)

[Claims] 1. A plurality of input ports and a plurality of output ports, capable of operating in both a low priority mode having a low priority level and a high priority mode having a high priority level, said plurality of input ports Switch means capable of simultaneously configuring a transmission path from any one of the plurality of output ports to one or more of the plurality of output ports, and the switch means for solving contention between the switch means in broadcast communication or multicast. A network switching system comprising: a broadcast multicast means for giving different priority levels to input messages to each of the input ports when operating in the high priority mode. 2. The broadcast multicast means includes allocating means for allocating a plurality of priority levels and holding the plurality of priority levels as pending in the switch means until they are executed in order of priority level. The system of claim 1. 3. The switching means comprises a switching element that can be commanded by the HI-PRI interface line to operate in a high priority mode capable of performing priority broadcast and multicast functions. system. 4. Means are provided for indicating the status of the broadcast or multicast connection in the first switching element to the second switching element in the preceding stage, the connection status indication being such that all connections are active. 2. A positive feedback signal that identifies that it was made in the first switching element and that, when inactive, all connections were made in the first switching element. system. 5. Asynchronous, non-clocked, non-buffered switching wherein said switch means may asynchronously perform a single destination connection in low priority mode and synchronously perform priority broadcast and multicast functions in said high priority mode. The system of claim 1 forming part of a network. 6. A snap for servicing a broadcast function and a multicast function, and determining the priority of a pending connection in a sequential cyclic priority type so that one requesting device cannot be locked out for the broadcast function or the multicast function. The system of claim 1 further comprising shot register means. 7. A plurality of ports each having a plurality of input ports and a plurality of output ports and capable of simultaneously configuring a transmission path from one or a plurality of the plurality of input ports to a plurality of the plurality of output ports. And a plurality of input ports and a plurality of output ports, each of which is provided at a stage subsequent to the transmission side switching means, and which has one or more of the plurality of input ports and the plurality of output ports. A plurality of receiving side switch means capable of simultaneously forming a transmission path in a plurality of the same, and a broadcast multicast for simultaneously forming a communication path from one or a plurality of transmitting side switch means to a plurality of receiving side switch means Priority non-buffering switching system with means. 8. The broadcast / multicast means receives service based on a synchronization priority system in the case of contention or connection blocking, holds a pending broadcast operation and a multicast operation as pending, and The system of claim 7, which is executed immediately when the blockage is resolved. 9. The system of claim 7 including means for detecting and eliminating deadlock conditions that may occur due to the execution of simultaneous priority broadcast or multicast operations. 10. A switching device for a network having a plurality of nodes each having a plurality of input ports and a plurality of output ports, one connection control circuit for each input port, and I and Z for each output port. A multiplexer control circuit for connecting any of the I inputs to any of the Z output ports, each having a unique value of 2 or more, and a message to the input port. A switching device for a network comprising means for assigning different priorities to each other and means for prioritizing so as to maintain a plurality of broadcast or multicast operations at the highest priority at the same time and in any combination. 11. A data bit input terminal and four control input terminals, wherein one of the control input terminals is a priority control signal input and the other control input is VALI.
11. The device of claim 10, which is a D, ACCEPT, and REJECT control signal input, wherein the priority control signal is activated to enable execution of broadcast or multicast operations within the switching device. .