JPH0685161B2 - Network switching system - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to multi-stage switching networks, and more particularly to systems that use bufferless switching elements to create multi-stage networks. The invention is equally applicable to synchronous or asynchronous bufferless networks.

[0002]

BACKGROUND OF THE INVENTION The present invention relates to parallel processing switching networks, and more particularly to an improved multi-stage switch for interconnecting N system elements, where N is several or thousands of computer processors, Or it may be a combination of multiple processors or other computer system elements. The invention particularly relates to a bufferless switching system that operates asynchronously at each node of the network. With the improvement according to the invention, the speed of a multi-stage switching network is improved by adding a high priority interconnection mode to the normal low priority interconnection mode of the network, which can handle two different message transfer priorities. Only one switching element is provided to create the network.

Multistage switching networks have become the means used to interconnect multiple devices within a computer system. Systems often require multiple paths through the switching network to perform different functions. Peter Franaszek's “Path Hierarchies in Interconnection Networks”
(IBM Jounal of Research and Development, Volume 31,
No. 1, January 1987), describes some of the problems associated with interconnect networks for high performance multiplexer systems. This document proposes a network structure that optimizes the delay of each network function by separating the control flow from the data flow and transferring the control information through the hierarchy of physical paths at varying speeds. This proposal is an implementation of a hierarchical network using crosspoint chips.

US Pat. No. 4,952,930 discloses two hierarchical paths for low latency message transfer and for ensuring the transfer of longer latency messages.

One problem with this is that it is a substantial performance problem due to blocking in multi-stage networks, ie, data transfer delays between stages and delay limits to resolve contention at each stage of the network. . In order to avoid or reduce this blocking, layering of two networks with different latency periods has been proposed. The first network is unbuffered for low latency, the second network is buffered for storage, and forward use ensures message transfer under all traffic conditions. The message is first sent via the low latency path. If this transmission fails due to blocking or contention, it is retransmitted via the guaranteed transfer path. This allows about 90% of normal messages to be sent on the low latency path, and retransmission ensures the transfer of messages blocked on the low latency path.

One problem arises from the use of multiple passes. That is, as the number of devices to be interconnected in the system increases, the amount of interconnects becomes a significant and costly problem, and the increase in the number of interconnected networks creates a major problem in creating multiple paths. Become. For modern parallel processors, it is not common to configure thousands of processors to hook into thousands of memory modules. The interconnection problem for such methods is very serious.

Some of the above problems in the prior art have already been solved by the inventor of the present invention, and a method for enabling multiple functions to be transmitted through the same network path will be described in the detailed description.

In making the present invention, the inventor is aware that others are challenging various problems in this field of networking. Some of the documents that show this are listed below.

US Pat. No. 4,679,190 discloses a method of transferring high priority messages in a multi-stage network using a multi-stage interconnection connector for voice and data packets. The invention of this specification relates to different transmission methods for synchronization, clocking and time slot transmission. Hi /
There is no control by the Lo priority interface line, and the relatively complicated method of priority and switch connection is different and is applicable only to 2 × 2 sub-switches. The priority level is encoded in the data line.

US Pat. No. 4,821,258 discloses a packet switching system. Here, access to the same output bus is determined by priority when there is contention, and only one data packet token is allowed to access one bus. This is a synchronous
It is a telephone transmission method with different clocking and time slotting, and is not controlled by the Hi / Lo priority interface line. This is a buffered switch that requires a data FIFO. Priority levels are those encoded on the data lines and their implementation requires complex logic and switch addressing schemes. This system does not have the ability to terminate from the transmitter.

US Pat. No. 4,667,323 discloses a network for high and low priority message transmission over a single ring data path, but apparently similar networks with trunk, star and Ethernet work topologies. Intended for function. This method uses station token holding and no switches. The present invention is a multi-stage switching network.

The bus also has a priority configuration. For example, a representative such bus priority method is disclosed in US Pat. No. 4,670,855. This is a compatible interface card, which is one of a number of compatible interface circuit cards that can be used to determine control of a common data path based on priority To decide.

US Pat. No. 4,623,886 discloses a bus interface unit which dynamically determines which information to use, in order to ensure that high priority data is transmitted before low priority data. 1 illustrates a network communication system that employs techniques for handling message transmissions.

US Pat. No. 4,213,201 discloses an improved crossbar switch which is biased by the lowest priority processor of an executing parallel computer with random suppression on the processor side involving fixed priority conflict resolution. This is done by giving each processor a threshold as it is created.

Since its purpose includes assigning different priority levels to multiple functions so that each function is sent over the same path, the IBM Technical Disclosure Bulletin (IBM TD
Seeing some of B.) is meaningful. Token ring structures have been proposed as an alternative to trees to rank the functions of one network. HS
Stone's method allows trees and token-ring networks to manage the priority between nodes so that one network can detect a request from N messages, and to select and share that transaction. A combination of switches has been proposed which broadcasts to all processors. The detailed ordering of the requirements method is used here. The first document on this was IBM TDB, Volume 32, Issue 1, June 1989, pp. 281 et seq. "ENHANCED MEANS (a fetch-
and-add instruction) FOR PARALLEL SYNCHRONIZATION
IN CROSSBAR SWITCHING NETWORKS ”.

This method evolved, and IBM TDB,
Volume 32, Issue 4A, September 1989, Page 225 and below, "LO
W-COST COMBINING SWITCH THAT IMPLEMENTS A MULTIPRO
CESSOR JOIN ”.“ PRIORITY-RESOLUTION MECHANISM FOR REDU on page 338 and below of this document.
CING COLLISIONS IN A MULTI-PROCESSOR INTERCONNECTI
"ON NETWORK" shows a priority resolution mechanism in the form of a switching node that makes memory access requests optional according to the rotation order of the number of memory modules.
tch and Add) Synchronization instructions are also described in “PARALLEL SYNCHRONIZATION WITH HARDWARE” on page 259 and below of this document.
COLLISION DETECTION AND SOFTWARE COMBINING ”.

This parallel processor and memory synchronization is further described in IBM TDB, Volume 32, No. 8B, "TE", January 1990.
CHNIQUE FOR PRIORITY RESOLUTION IN NETWORKS THAT S
UPPORT PARALLEL SYNCHRONIZATION ”.

Data switching network (IEEE 8
A 96 'Futurebus (as shown in the Futurebus) is a processor between processors in a multiprocessor system where parallel processing conditions and one bus are not sufficient to carry the required traffic at multiple offices. It can be applied to many things like telecommunications. The basic solution is IBM TDB, Volume 31, No. 9, "DATA-S", February 1989.
WITCHING NETWORK FORA MAGNETIC DISC STORAGE SYSTEM
However, future bath technology requires some form of control arbitration, as shown in this document. This form is not applicable for the improvements described here.

[0019]

The problem with these documents is to dynamically and rapidly create and disconnect the interconnection of elements to handle several or thousands of processors in one switching network, This means that if possible, one chip must be able to do it inexpensively and easily. To have the ability to scale to thousands of elements, to allow arbitrary untuned interconnect wire lengths, and solutions to distributed processing systems, as well as to enable future frequency increases. , N switching paths must be made in parallel and a device must be designed to allow simultaneous data transfer through them.

[0020]

SUMMARY OF THE INVENTION A switch, referred to as an ALLNODE switch, is provided that allows interconnection of multiple processors or other functional elements, including command-based digital systems. This provides a way to transfer control and data between elements over one common, small number of point-to-point interconnect wires.

The switching device is provided at a node having a plurality of input and output ports, which has a connection control circuit at each input port and I inputs, where I and Z are any unique value greater than one. A multiplexer control circuit is included at each output port to connect any of the outputs to any of the Z outputs.

[0022]

In accordance with the present invention, the same network can be implemented by using a new system that allows multiple functions to assign different priority levels to each function, allowing each to send over the same physical path. Sent via a pass.

According to the present invention, a multi-stage switch having dual priority or dual priority is provided. This switch allows two priorities, assigning different priorities to each function so that each function is transmitted over the same physically single network path.

Thus, the dual priority switching system of the present invention ensures that each node has complete control over the data it transmits, ie it does not lose control of that data by being somewhere in the buffer switch in the network. To provide a bufferless switch for a multi-stage switching network system. This system receives incoming requests for connections to requested output ports that support the selection of competing requests, and when this requested output is in use and requires restart of the request message It has a low priority node for sending the reject signal to the request transmission source element. The system also has a high priority node switch that reserves the requested path and has greater latency than the low priority node switch that does not reject the message. This high priority node can be used to provide a guaranteed transfer path.

For example, referring to the above example, low latency messages may be assigned to low priority message levels and guaranteed forwarding messages may be assigned to high priority message levels. At this time, both message types can be transmitted via the same path by the means described here. This allows most of the purposes of multiple paths to be achieved without the need for additional networks to perform additional functions.
The present invention can form a hierarchical network function through a single path.

The present invention will be described for message transmission through a multi-stage network. Networks and protocols are objects that show the concept. This selected network switch and protocol is US Patent Application No. 07.
No. 677,543 (filed Mar. 29, 1991), the invention is applicable to most bufferless network switches and protocols.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1, which illustrates a preferred switch, the switch is a 4 × 4 crossbar switch for sending 4-bit data in parallel to any one of four input ports and any four output ports. Operates asynchronously. A switch such as that shown in Figure 1 can support up to four simultaneous connections at any given time. The switch can operate in one of two modes, a low priority mode or a high priority mode. The individual modes will be described below.

1 to 4 are common with the above-mentioned US application Ser. No. 07 / 677,543. The present invention features the logic and timing of the control signals shown in FIGS.

As shown in FIG. 1, this preferred switch provides a node having a plurality of input and output ports, and a connection control circuit for each input port, and I and Z as any value greater than one. , A multiplexer control circuit is included for each output port to connect any of the I inputs to any of the Z outputs.

However, according to the present invention, dual priority switches are provided with matching operation in a multi-stage network. This switch allows two priorities,
Each function is assigned a different priority level so that each function can transmit over the same physically single network path.

The preferred embodiment is a 4 × 4 crossbar switching device, the function of the present invention is to have any of the four input ports in an mutually exclusive relationship with the four unused output ports according to priority. Is to give a means to connect to any of.

In FIG. 1, a 4 × 4 crossbar switching device can simultaneously support up to four connections at any given time. For example, the input port 1 can be connected to the output port 3, the input port 2 can be connected to the output port 4, the input port 3 can be connected to the output port 2, and the input port 4 can be connected to the output port 1.

The switching device 10 of the present invention is unidirectional, ie data flows across the device 10 in only one direction, ie from the input port side to the output port side. This switching device 10 is unidirectional,
As shown in Fig. 1, 4x4 ALL-NODE switching device 1
By connecting 0, four nodes (20, 22, 2
Bidirectional communication between 4 and 26) is supported. Each node 2
0, 22, 24, 26 have two sets of unidirectional interconnect wires, one towards switch 10 and one out of switch 10. The dashed line inside the switching device 10 indicates that the function of this switch is to connect one input port, such as input port 1, to one of the four output ports. This switching device 1
0 provides exactly the same function for each input port, allowing it to be connected to any unused output port.
As shown in FIG. 2, the switch 12 has four data bit inputs and four control inputs. A new high priority (HI-PRI) interface control line is used for this basic AL
It adds a new dual priority feature to the LNODE switch configuration. In addition, there are VALID and REJECT control signals and an ACCEPT line which is a required line.

In FIG. 2, block 12 is an enlarged view of the switching device 10 and specifies the interface line connected to the switching device 10 in detail. Lines 31, 3 of each input port to the switching device 12
2, 33, 34 are lines 41, 42, 4 of the respective output ports
3, 44 and the number and function are the same. Interface lines to each input and output port are prefixed INX- or OUTX- to indicate the number of ports (X) associated with 8 signals, ie 4 data lines and direction.
4 control lines (VALID, ACCEPT,
REJECT and HI-PRI). With 4 data lines
VALID line and HI PRI line are switching devices 1
The two REJECT and ACCEPT control lines have signal flow in the opposite direction, with signal flow from the two inputs to and through the outputs.

Input port interface line 31,
Reference numerals 32, 33 and 34 command the connection between the input port and the output port inside the switching device 12 and transmit control information for making to the device 12. In addition, these port interface lines carry data information to be transferred from the input port through the device 12 to the output port. The four data interfaces included in the interface lines 31, 32, 33, 34 do not limit the data transfer across the switching device 12 to 4-bit information, each being a serial data string that enables the transmission of data of any size. including. For example, if all of these four data lines are transmitting serial data at 40 MHz, data can be transferred at 160 Mbit / sec.

This switch interface requires only eight signals as shown in FIG. 3 to send and control dual priority data through this network, and the data transfer width is 1/2 byte (4 bits) at a time. is there. These signals are:

DATA: 4 parallel signals used to command switch connections and send data messages.

VALID: Indicates that one message is being transmitted when it is active. RESET when inactive
Command to force all switches to reset to the IDLE state. All switch functions are reset except for the high priority latch.

HI-PRI: Indicates that the message being processed is in high priority mode when active.

When inactive, issue the TERMINATE high priority command to reset all associated high priority latches.

REJECT: The signal flow is the reverse of the other six signals. REJECT when active for low priority transfers
Indicates that a condition has been detected. It has no meaning in HP mode operation.

ACCEPT: The signal flow is in the same direction as the REJECT signal, and the reverse of that of the other six signals. A WAIT condition is detected when low and indicates that a high priority connection cannot be made at this time. When high, the WAIT condition has ended, indicating that a commanded high priority connection has been made.

In FIG. 3, blocks 50, 52 and 54 represent an exemplary method for generating serial data in the form of a message that can be transmitted to and across the switching device 14, which is a partial view of the switching device 12. . Serial data generation logic similar to that provided by blocks 50, 52 and 54 is provided by switching device 12.
Can be used at each of the other input ports to. Each input data line group produces serial data by shifting four synchronization lines 31 of data controlled by the same clock signal (40 MHz in FIG. 3) to four clock shift registers 54 for the same clock. Present serial data on the given input port to be synchronized. However, 4 to the switching device 14
Different input port sources (31, 32, 33, 3
4) may be asynchronous to each other based on different unsynchronized 40 MHz clock signals.

The process of sending a serial message through the switching device 14 is a first-in first-out buffer (FIF
O) 50, which accumulates the data messages to be sent. The message to be transmitted is then moved to buffer 52. The message stored in the buffer 52 is moved to the shift register 54 in preparation for transmission, and the data is data bit 0 to the first bit of shift register 1, data bit 1 to the first bit of shift register 2, and data bit 2 To the first bit of the shift register 3, the data bit 3 to the first bit of the shift register 4, the data bit 4 to the second bit of the shift register 1, and so on.
Dispersed across 4. At this time, the shift register 54 starts to send the serial data to the switching device 14 via the four synchronized data lines so that the serial data continuously flows until the entire message is sent. The switching device 14 uses the first 8 bits transmitted (in the first two clock cycles of serial data from the serial register 54 to the switching device 14 via the interface 31) to select the connection path through the switching device 14 and Establish. In the example of FIG. 3, the switching device is connected to the input port 1 (31) via the dotted line so that each of the seven lines in the interface 31 is uniquely and directly connected to each of the corresponding lines in the interface 42. Output port 2
(42) shows what makes a temporary connection between.

In FIG. 4, eight switching devices 1 are provided.
A method of increasing the number of nodes in a system by cascading 0 blocks is shown. 8 cascaded switching devices 10A-10H
, Which have the same configuration as the device 10 except for the connection of the input port and the output port. 1 via a connection through two of the blocks of switching device 10
Any of the 6 nodes can communicate with any other node. For example, node 5 has switches 10B and 10B.
Messages can be sent to node 15 via H.

Switching device 1 with all connections being two
Since it is performed through 0 blocks, a network composed of 8 switching device blocks is called a two-stage switching network. Other multi-stage networks can be similarly constructed by using the switching device 10 blocks in three stages, four stages, and the like. The number of nodes that can be interconnected in this type of network can be very large, but for convenience of explanation, FIG.
4 is representative of the characteristics of a larger network, the one of FIG. 4 will be described here.

In low priority mode, this switch can receive commands from each input port. These commands arrive asynchronously and request a connection to a particular output port. If the requested output port is available (NOT BUSY, ie not used to support a previously commanded connection), the command is executed and the connection is made. If the output port is BUSY,
The command is rejected and the input port returns to the IDLE state (that is, ready to accept the next incoming command). This rejected connection in low priority mode is broken or killed if all of the paths in this network are not made.
D), so it is called KILL.

The switches are cascaded to create a network larger than the 4x4 interconnect type supported by that individual switch. FIG. 4 shows how to do this by connecting one output port of one switch to the input port of a second switch. In this large network, the first switch may make a valid connection and the next switch may become BUSY and issue a REJECT. This REJECT indication is sent backwards to the output port of the previous switch, which has already made a valid connection. In this case, the switch breaks its active connection and indicates that fact by sending a REJECT signal to the input port to which it is connected.
On the other hand, this input port issues REJECT to its source and
Return to LE status. This method is called KILL because the REJECT sequence breaks or kills all previously created connections. Everything in this KILL path is returned to the IDLE state. Also, the part of the message whose transmission has started is completely lost, that is, it is made KILL, and this message must be retransmitted from the beginning.

If two or more of the input ports receive commands at the same time and contend for a connection to the same NOT BUSY output port, the lower input port wins the dispute and makes the desired connection, And the other is rejected and those connections become KILLED. Therefore, low priority paths through this simple network use this KILL function. If any part of this path is rejected, the entire path is immediately broken and the message must be retransmitted from scratch.

Initially, messages sent in high priority mode behave at the switch in the same way as messages sent in low priority mode. The requested output port is
If NOTBUSY, an effective connection will be made on a first come, first served basis. Or if multiple inputs contend for the NOT BUSY output at the same time, the lower input is chosen. However, the high priority mode prohibits issuing a REJECT in response to a broken connection, and a special high priority that keeps that connection pending in the switch until the broken connection is available. Performs the additional function of setting the penting latch. Then it immediately makes a pending connection and gives a positive feedback to the requester. This pending connection will not be lost or lose its priority unless terminated by the message source.

In place of the REJECT response, the high priority mode issues a WAIT response when the connection cannot be established. This WAIT response is
It consists of setting the ACCEPT signal to 0 and keeping it at 0 for a period of the WAIT condition. When a pending connection is made, the ACCEPT signal is forced to a logic 1 as a positive indication that the WAIT state has ended. When the node requesting the connection detects a WAIT response, it temporarily suspends transmission of the message and continues where it left off when the WAIT condition is removed. Thus, in high priority mode the sending node does not retransmit blocked messages from the beginning as in low priority mode, but simply aborts and continues if an ACCEPT occurs.
This timing is such that the sending node receives the ACCEPT indication and continues as early as possible, allowing high priority messages to be sent at such early times. Moreover, all stages before the blocking (here winning the previous dispute over the connection) stage are held for the duration of the WAIT period and are not recreated for the high priority message in transit. Thus, this ensures the transfer of high priority messages through the network as early as possible.

If more than one high priority message is waiting for an output port to become available, the message associated with the lowest input port will be connected first,
Others continue WAIT with the snapshot register. After all the requests waiting in the snapshot register have been serviced, this register causes all requesters to connect to the output port before one given requester can be serviced next. Gives an equal chance to do. In this way, it provides a way to ensure that a requester given through a high priority path through the network will not be completely blocked from this network and experience starvation.

For large networks, the first switch may make a valid connection and the second switch may detect a WAIT condition. In this case, the WAIT condition is sent backwards to the previous switch. This predecessor switch simply forwards this WAIT indication in the opposite direction without breaking its connection. This happens in all previously connected switches until the WAIT is propagated to the message source.

It is possible to reset all high priority paths at any time by the source returning HI-PRI to the zero state. The source has no ultimate control over the entire network.

5-10 show detailed logic for a portion of the dual priority switching device of the present invention. This part provides one low priority or high priority data transfer connection between one input port (eg input port 1) and one output port (eg output port 1) of the 4 × 4 dual priority switching device 10. This is a typical circuit required to build. Latch 7
0, 72, 74 and 74 control the normal low priority paths, their behavior is how they create the low priority paths, and how the connections within that switch are RE.
Regarding whether it will be broken when it becomes JECT (KILLED),
It is described in detail in Japanese Patent Application No. 4-24105 and U.S. Patent Application No. 07 / 677,543.

The novel method according to the invention is based on the basic ALLNOD
This is the addition of the second high priority path for performing the guaranteed transfer function to the E (all nodes) switch logic. The implementation of this new logic is latches 172,17
4, block 140, delay block 84, gate 17
8, 182, 78, 95, 115 and IN1-HI-PRI of input port 1 and output port 1 as shown in FIGS.
It consists of new interface control signals at each port, such as OUT1-HI-PRI. The functional operation of these logic elements is described below.

FIG. 11 shows the timing sequence generated by the node attached to input port 1. Figure 11
Shows the signal sequence used by input port 1 to command a new high priority connection of input port 1 to output port 1 through a dual priority switching device. This operation starts with the simultaneous activation of the IN1-HI-PRI and IN1-VALID interface control lines to logic 1 by input port 1. The IN1-HI-PRI signal is shown in Fig. 5-1.
Controls the high priority path of 0, and its actuation to a logic 1 causes the resets of latches 172 and 174 to unset and enable them.

Next, as shown in FIG. 11, IN1-DA occurs.
Command pulse 81 on the TA1 interface line, which commands input port 1 to make a high priority connection to output port 1. This command is IN1-HI
-Features a pulse 81 on the IN1-DATA 1 line that specifies that when PRI is active it is a high priority connection and that the connection should be to output port 1. When pulse 81 is on the IN1-DATA 2 line, it indicates that the connection is to output port 2, IN1-DATA 3 indicates the connection to output port 3, and so on. In the example shown in FIG. 11, if IN1-DATA 1 has a pulse 81, latch 172 is set at the rising edge of that pulse and latch 174 is set at its falling edge. When the latch 174 is set, the dual priority switch will
Latch the fact that it has received a command to make a high priority connection from input port 1 to output port 1 as indicated by the COM HI-PRI 11 signal from. Latch 172
When is set, the PREHI-PRI 11 signal becomes active and A
The ND gate 95 is activated to generate the WAIT11 signal.
The WAIT 11 signal is sent to the AND gate 182 through the NOR gate 115 (inverted here), and there, FIG.
It is returned to node 1 via the IN1-ACCEPT line as shown at 1 to produce pulse 71. Pulse 71 provides an acknowledgment to input port 1 that a commanded connection has been made. As long as the WAIT 11 signal is active, the dual priority switch is waiting for a connection to be made and has not yet succeeded in making a connection. When this connection is made, the WAIT 11 signal becomes inactive, causing the IN1-ACCEPT signal to rise through gates 115 and 182. The pulse 71 is generated in this manner, and the positive feedback indicating that the connection is made is given to the input port 1. Pulse 71 is a fast connect time when pulse 71 is the same width as pulse 81, but the connection is made immediately (within the duration of pulse 81) so that it is delayed by a path that implements the logic shown in FIGS. Indicates.

The COMHI-PRI 11 signal also enters the NOR gate 182, where N and other similar signals from other input ports are present.
ORed and any one of them is gated 180
And the output port 1 through the replacement block 85 to generate the BUSY signal. This causes all low priority requests for output port 1 to be immediately denied until all high priority requests for that output port have been serviced.

The formation of the high priority connection to output port 1 is controlled through logic block 140, which receives commands from latches 147 and similar latches associated with other input ports to prioritize, This makes those connections. If it determines that input 1 is the highest priority requester for output 1, block 140 activates the "ENABLE HI-PRI 11" signal to inform the dual priority switch that it is now making a connection. Details of the operation of the block 14 are shown in FIGS.
3 and FIG. 8 will be described later. This activated "ENABLE
HI-PRI 11 ”signal is AND gate 1 as shown at 207
If 78 is entered and the low priority connection is currently active for output port 1 as detectable by a latch such as 74 which is active through NOR gate 80, further propagation is prohibited. However, normally NOR gate 80
Does not block the "ENABLE HI-PRI 11" signal at gate 178 and activates the "HI-PRI 11" signal immediately or as soon as the low priority connection is broken. This “HI-PRI 11
Signal is low priority signal at gate 190 (LCONNECT 11)
Is ORed to generate a combined signal CONNECT 11 which causes the dual priority switch to connect from input port 1 to output port 1. CONNECT 11 signal is gate 19
It is inverted at 2 and enters the gate 95 to inactivate the WAIT 11 signal.

The CONNECT 11 signal is also used to make a direct connection of the six interface lines between input port 1 and output port 1. The four data lines of input port 1 are connected to the four data lines of output port 1. The details of the typical connection are AND gate 122 and OR.
Shown by gate 130. By CONNECT 11 entering the AND gate 122, the output of the AND gate 122 is IN1-
It directly follows the value of DATA 1 and is gated by the OR gate 130 to OUT1-DATA 1. The AND gates 124, 126, 128 which provide the other inputs of the OR gate 130 are all held at logic 0 and do not affect the gate 130. This can usually be activated at the time when one CONNECT signal is given, which causes a 1 to a particular output port.
This is because the books can be connected. Therefore, CONNEC
If T 11 is active with respect to gate 122, then gate 12
CONNECT 21, CONNECT 31 and CONNECT 41 to 4,126,128 must all be inactive. Similarly, IN1-HI-PRI and IN1-VALID lines are also CONNECT 11
The input port 1 is connected to the output port 1 based on the signal. Typical connections are shown through gates 154 and 162 for the IN1-HI-PRI line. As a result, all 6 signals on input port 1 are directly connected to the same signal on output port 1 and the pulse shape on input port 1 is temporarily generated on output port 1 and the two logic passing through it. 2 such as 154 and 162 to experience only the slight delay introduced by the gates (similar to 154 and 162).
Through the gates and directly through the dual priority switch without buffering. There is one exception that the waveform of the input port 1 in FIG. 11 is different from the output waveform. That is, the pulse 81 is extracted from the input waveform and the latch 17
4 and not passed to output port 1. There are two reasons for this.

1) By the time the CONNECT 11 signal becomes active, pulse 81 disappears and cannot pass to output port 1.

2) The pulse 81 specifies the first stage switch connection to be made and has no other meaning. Hence pulse 8
It is better not to let 1 go through this network further.

The two feedback signals from output port 1 to input port 1 also have a connection made when the CONNECT 11 signal becomes active. AND gate 94 outputs OUT1-REJECT
Shown is CONNECT 11 which is selected through NOR gate 92 and OR gate 90 as the source of the 1-REJECT signal. ACCEPT signals from the four output ports are gates 104, 106 and 1 respectively.
08, 110 and ANDed by gate 102. Individual monitors for the four OUTX-ACCEPT signals enter gate 104 and generate NOT CONNECT 11 gate 19
This is made possible by the inversion of their corresponding CONNECT signals, generally indicated by 2.

In a multi-stage network, pulse 71 indicates that the network's first stage switch made the connection. The next step is to command the second stage network switch to make its connection by issuing a pulse 73 to IN1-DATA 1 as shown in FIGS. This example is the two stage network shown in FIG. 4 and the second stage switch logic is the same as the logic shown in FIGS. The second stage receives a command by pulse 73 on the IN1-DATA 1 line to make exactly the same high priority connection from input port 1 to output port 1 as in the first stage.
The second switch stage is connected to switch stage 1 by the CONNECT 11 signal as described above, and FIG. 1 except that switch stage 2 does not receive the pulse 81 tripped by stage 1.
It receives exactly the same waveform as stage 1 as shown in FIG.

The events occurring at the stage 2 switches are similar to the events previously occurring at the stage 1 switches. The operation starts at stage 2 with input port 1 at stage 2, and then IN
The 1-HI-PRI and IN1-VALID interface control lines are simultaneously at logic 1 when they are connected through stage 1. The IN1-HI-PRI signal controls the high priority paths of FIGS. 5-10 and their activation to logic 1 causes latches 172 and 17
Remove reset from 4 and enable them.

The next thing that occurs is IN1-, as shown in FIG.
Command pulse 73 on DATA 1 interface line
, Which commands input port 1 to make a high priority connection to output port 1. The pulse 73 on IN1-DATA 1 sets the second stage latch 172 on the rising edge of pulse 73 and the latch 174 on its falling edge. Due to the set latch 174, the dual priority switch is set to COM HI-PRI 11 from the latch 174.
Latch the fact that it has received a command to make a high priority connection from input port 1 to output port 1 as indicated by the signal. The set latch 174 activates the PRE HI-PRI 11 signal, which activates the AND gate 95 to produce the WAIT 11 signal. The WAIT signal is passed through the OR gate 115 (inverted there) to A
It is sent to ND gate 182, where it is returned to switch stage 1. This causes the signal to pass back through the switch in stage 1 to node 1 via the IN1-ACCEPT lines, producing pulse 75 as shown in FIG. Pulse 75 gives an acknowledgment when the commanded connection is made. WAIT11
As long as the signal is active, the dual priority switch is waiting for a connection and has not yet made a connection. When the connection is made, the WAIT 11 signal becomes inactive and causes the IN1-ACCEPT signal to rise through gates 115 and 182 to produce pulse 75, providing positive feedback through stage 1 where the connection is made. Pulse 75 exhibits a lower connection time than pulse 71 due to its wide width. This is because in stage 2 output port 1 is BUSY in the previous connection and cannot be used immediately for the connection indicated by OUT1-NOT BUSY signal 201 in FIG. 11, but can be used to make a new connection until pulse 201 occurs. Means no.

At the time of pulse 201, “ENABLE HI-PRI 1
A "1" signal is emitted by block 140 as shown by pulse 209. This indicates that the next connection from input port 1 will be made to output port 1. This "ENABLE HI-PRI 11 activated". "Signal is AND gate 178
Enter and at gate 190 low priority signal (LCONNECT 11)
And OR to generate a composite signal CONNECT 11 that causes the dual priority switch to connect from input port 1 to output port 1. This CONNECT 11 signal is inverted at gate 192 and enters gate 95 where it deactivates the WAIT 11 signal (indicated by the end of pulse 205) and ends pulse 75. This makes a connection through both stages of the two-stage network, where two nodes pass from the first node through the input port 1 of switch stage 1 through the output port to the input port 1 of switch stage 2 and its output port. It is connected by a network path extending to 1 and to the second node. At this time, message data as shown in FIG. 11 can flow from the first node to the second node.

As a result, the high priority command is stored in the switch stage from the high priority command, and immediately after the required output port becomes available based on the priority, the high priority path is created at the highest speed. Furthermore, as soon as a connection is made, positive feedback is provided to the node making the connection so that it does so at the earliest point.

The essence of this high priority method is the function provided by block 140, shown in detail in FIGS.
Representative logic is shown for making a high priority connection from input port 1 to output port 1 by latches 252 and 254 when operating on gates 250 and 258 and delay block 257. Gates 260, 266
The same logic is shown for making a high priority connection from input port 2 to output port 1 by latches 262 and 264 when acting on 268 and delay block 267. The logic for making a high priority connection from input port 3 to output port 1 by latches 272 and 274 is shown when operating on gates 270, 276, 278 and delay block 277. Gate 28
The logic for making a high priority connection from input port 4 to output port 1 by latches 282 and 284 is also shown when operating on 0, 286, 288 and delay block 287.

Block 140 requires sequential logic operations and decisions that require a clock signal. This is the first that required a clock to implement any of this all-node switch concepts. The clock used in FIGS. 12 and 13 is 40 MHz in this example, but generally, this clock frequency is determined by the technique at the time of implementation.

Performed at block 140 and shown in FIGS.
Continuing with the example of input port 1 commanding a high priority connection to output port 1, the function shown in 3 is used, and input port 2 commanding a high priority connection to output port 11 to indicate the priority function to it. Will be described here by adding the simultaneous requests of "COM HI-PRI 11" signal and "COM HI-P"
The RI HI-PRI 21 "signal activates this information for AND gates 250 and 260 respectively to block 140.
Carry to. In general, the gate 250 has the NOT CONNECT 11 signal (gate 192 of FIGS. 5-10) inactive (CONNECT 11-
Gate 192 is active) meaning "CO
Does not pass M HI-PRI 11 "signals, which means that if the required connection is already made by a low priority path, then there is no need to make a connection over a high priority path and the high priority operation ends. However, in the normal case, the NOT CONNECT 11 signal is active to gate 250, and high priority operation is advanced by allowing latch 252 to receive the output of gate 250. Latch 2
52 is the IN1-HI-PRI signal on the reset line,
If the input port 1 is operating at a high priority, it can function. The latch 252 is set when the gate 250 becomes active in synchronization with the rising edge of the 40 MHz clock signal as shown in the timing chart of FIG. 14, and IN1-HI PEN
Generate a DING signal. The purpose of the logic of block 140 is to record this pending command and make the desired connection based on priority at the earliest time. Latch 2
The -Q output of 52 is fed back to its SET input terminal, and IN1-HI
-It remains set after the PRI signal is initially set until it becomes inactive at the reset input to that latch,
And reset it.

The latches 254, 264, 274 and 284 are 4-bit snapshot registers (SNAP SHOT REGIST).
ER), which allows all pending connections to be created cyclically, while preventing individual users from occupying output port connections and circumventing other users who cannot make the desired connection. The snapshot register is only allowed to be "snapshot" at specific intervals for the purpose of determining which connection is pending. This "snapshot" interval is defined by AND gate 300 which provides the snapshot register with a clock signal which causes it to sample pending connection requests from gates 252, 262, 272 and 282, respectively. This clock of the snapshot register is generated by the 40 MHz gate 300 when output port 1 is not busy with the OUT1-NOT CONNECTED signal from gate 320 with none of the snapshot register bits set.
Basically this snapshot register is clocked at 40 MHz unless output port 1 currently has a connection to it and there is no active bit in the snapshot register.

FIG. 14 shows that input ports 1 and 2 issue a pending high priority command for connection to output port 1 and output port 1 is a 0 prior to the previous low priority connection due to OUT1-NOT CONNECTED signal 302. Indicates the timing of the snapshot register when it is in use.
FIG. 14 shows IN1-HI PENDING and IN2-HI PENDI in this case.
The NG latches 254 and 264 are set to indicate that both are waiting for output port 1 to become available. At pulse time point 301, output port 1 terminates its previous connection and is ready for use. If the snapshot register does not have the bit previously set, then the CLOCK SNAP SHO
The T REGISTER signal becomes active during the period when it coincides with the next 40 MHz clock signal after pulse 301 and pulse 30
3 is generated. The pulse 303 enters all four bits of the snapshot register and latches them into the latch 252 and 252, respectively.
The state corresponding to the states 262, 272, 282 is set. In this example, snapshot register latch 2
54 and 264 are set together at this time. This activates the “ENABLE HI-PRI 11” signal after a delay of 10 ns through the block 257 and the gate 258. This selects input port 1 as the next to connect to output port 1 by issuing pulse 305. Latch 264 is set with pulse 303, but the "ENABLE HI-PRI 21" signal is not active at the same time as pulse 305. That is,
This is because the "NOT ENABLE HI-PRI 11" signal is 0 at this time and is prevented by the gate 266.

The connection to the output port 1 after the input port 1 sends the message to the output port 1 is shown in FIG.
As shown in, the IN1-HI-PRI signal is deactivated by deactivating it, which results in COM HI-PRI 11, IN1-HI PENDING and
Reset ENABLE HI-PRI 11 (one bit in the snapshot register). At this time, the latch 264
Only the set remains in the snapshot register and the gate 266 is allowed to pass its indication to the delay block 267, thereby "ENABLE H
The I-PRI 21 ”signal 268 becomes active after 10 ns, as shown in FIG.
Pulse 307 of 4 and then select input port 2 to connect to output port 1. Input port 2
After sending the message to output port 1, its connection to output port 1 is that IN2-HI-P as shown in FIG.
It is cut off by making the RI signal inactive, and this
M HI-PRI 21, IN2-HI PENDING and ENABLE HI-PRI 21
(Based on resetting one bit in the snapshot register). Output port 1 will now service all of its pending connections, and the CLOCK SNAP SHOT REGISTER signal 300 will start the snapshot register clock again by issuing pulses such as 309 and 311 and this will output port 1 Will be reconnected or another high priority operation will be latched in the snapshot register.

Delay blocks 257, 267, 277, 2
The purpose of 87 is to prevent one connection from coming too close to the previous one and to prevent malfunctions before the interface signal drops.

FIGS. 5-10 and FIGS. 12 and 13 show the circuitry required within the dual priority switch. Further, the functions of FIGS. 5-10 are required to collectively define all of the input ports when each of them connects to all the output ports.

However, those implementations are shown in FIGS.
Is an obvious extension of and is not shown here.

[0079]

According to the present invention, it is possible to provide a switching device called an all-node switch that enables interconnection of a plurality of processors or other functional elements including a digital system in a command type.

[Brief description of drawings]

FIG. 1 is a diagram generally illustrating one embodiment of the present invention as a 4 × 4 crossbar switch having a control line for handling dual priority selection internally.

FIG. 2 is a diagram showing details of the 4 × 4 crossbar switch device of FIG. 1 and its interface connection.

FIG. 3 shows an exemplary method for generating serial data information to be sent to a switching device via four data lines.

FIG. 4 is a diagram showing an exemplary method of cascading 4 × 4 switching devices to accommodate a system having 5 or more nodes.

FIG. 5 illustrates a preferred embodiment of a dual priority switch by representatively showing high and low priority paths between a given input port and a given output port of the dual priority switch. FIG. 6 is a partial view that completes one drawing together with FIGS. 6 to 10, with FIG. 6 connected to the right and FIG. 8 connected to the bottom.

FIG. 6 is a view similar to FIG. FIG. 9 is a partial view that completes one drawing together with FIG. 5 and FIGS. 7 to 10, wherein FIG. 5 is connected to the left, FIG. 7 is connected to the right, and FIG.

FIG. 7 is a view similar to FIG. 5, 6 and 8-10
FIG. 6 is a partial view that completes one drawing with FIG. 6 being connected to the left and FIG.

FIG. 8 is a view similar to FIG. 5 to 7 and 9, 10
It is a partial view which completes one figure with FIG. 5, and FIG. 9 is connected on the right.

FIG. 9 is a view similar to FIG. FIG. 11 is a partial view that completes one drawing together with FIGS. 5 to 8 and FIG. 6, with FIG. 6 connected to the top, FIG. 8 connected to the left, and FIG.

FIG. 10 is a view similar to FIG. FIG. 10 is a partial view which completes one drawing together with FIGS.
Are connected.

FIG. 11 is a timing diagram showing an example of how to sequentially form high priority paths at a first available time point through a two-stage network including a plurality of dual priority switches.

FIG. 12 is a diagram showing a detailed logic of a high priority switch function including a snapshot register and a register clock, and a high priority pending logic. FIG. 14 is a partial view which completes one drawing together with FIG. 13, and FIG. 12 is connected below.

FIG. 13 is a view similar to FIG. FIG. 13 is a partial view that completes one drawing together with FIG. 12, and FIG.

FIG. 14 is a timing diagram illustrating typical snapshot register timing and a method for sequentially servicing multiple requests at the earliest time based on a built-in priority method.

[Explanation of symbols]

 10 dual priority switch device 12 broadcast communication switch device 14 broadcast communication switch device 20 to 26 node 52 message 54 shift register 56 message buffer

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventors Peter, Michael, Kogge, New York, USA Endicott, Dorchester, Drive, 7 (72) Inventors Gilbert, Clyde, Bundling, The, Third Endy, New York, USA Cot, East, Campville, Road, 1255

Claims (8)

[Claims] 1. A switch means for providing a plurality of transmission functions to one network path, a first node having a first priority, and a second node having a second different priority. A switching system for a network, wherein the switch means assigns different priorities to the respective functions so that the respective functions can be transmitted through the same physically one network path. 2. The system of claim 1 wherein said allocating includes allocating means for allocating a high priority message level to guaranteed transfer messages. 3. The switch means is instructed to operate in a dual priority high / low mode by a HI-PRI interface line and to function in a high priority mode for immediate data passing under contention free conditions. The system of claim 1 including a switching element that is capable. 4. The switching means for automatically changing to a high priority mode under conflicting and blocking conditions with switching elements that can be commanded by the HI-PRI interface line to operate in a dual priority high / low mode. The system of claim 1 including the means of. 5. The system of claim 1, wherein the switching system forms part of an asynchronous, non-clocked and unbuffered switching network. 6. The system of claim 1 using snapshot register means for servicing high priority pending connections in a rotational priority manner so that no requesting device can be locked out or experience data starvation. 7. A switching device for a network having a plurality of nodes each having a plurality of input ports and output ports, wherein a connection control circuit for each input port and I and Z for each output port are provided. A multiplexer control circuit for connecting any of the I inputs to any of the Z outputs as unique values of two or more, and means for assigning different priority levels to one function And a switching device for a network having one physical network path through which each function to be sent can be passed. 8. A control input having four data bit input terminals and four control input terminals, one of which is a priority control signal input, and the other control input is VALI
8. A control signal input for D, ACCEPT and REJECT.
Switching device.