JPH07122841B2 - Digital signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, in a digital signal processing device, in which operation is stopped during standby of the device in order to reduce power consumption of the device.

(Prior Art) A digital signal processing device which starts operation from a fixed address every predetermined period and performs program processing of digital signals is provided with a circuit for externally stopping the operation clock of the digital signal processing device. In the standby state where there is no digital signal to be processed, the digital signal processing is stopped by stopping the supply of the operation clock to reduce the power consumption. When the supply of the operation clock is restarted, the operation of the digital signal processor is started at the same time as the supply of the operation clock.

(Problems to be Solved by the Invention) However, in the above method, a fixed address start is entered in the middle of the operation start of the digital signal processing program in the first cycle when the operation is started, and the digital signal processing program operation is started. There was the problem of drooling.

In order to solve the above-mentioned drawbacks, the present invention provides a digital signal processing device for operating a program for digital signal processing from a stable synchronization point when the operation is resumed from a stopped state of digital signal processing. With the goal.

(Means for Solving the Problems) In order to solve the above problems, the present invention receives a fixed address start signal every predetermined period to start a processing operation from the fixed address, and a digital signal for each internal clock. In the processing device, the processing operation stop circuit (G1, F1, G2) that stops the supply of the internal clock to the digital signal processing circuit in response to the stop instruction signal, and the internal operation from that point when the stop instruction signal is released A reset circuit (F2, F3, F that gives a reset signal to the digital signal processing circuit for setting the processing operation of the digital signal processing circuit to the initial state for a time corresponding to at least several clocks of the clock.
4 and F5), and the program counter of the digital signal processing circuit until the fixed address start signal continues after the time corresponding to at least several clocks of the internal clock has elapsed from the time when the stop instruction signal was released. Start inhibit circuit (F2, F3, F4, F5, F6, F8, G that gives a signal to set a fixed address to the digital signal processing circuit
4) and is provided.

(Operation) Since the present invention has the signal processing device configured as described above,
First, when the stop instruction signal is released, the reset circuit causes the digital signal processing circuit to perform the reset operation for at least several clocks of the internal clock, and therefore, the complicated setting that requires several clocks for initialization is performed. Even the signal processing circuit can be reset sufficiently stably.

Next, when the stop instruction signal is released, from this time point, a time corresponding to at least several clocks of the internal clock has elapsed (after the reset signal is released), and until the subsequent fixed address start signal is received, the start inhibition circuit is provided. Allows the program counter of the digital signal processing circuit to
Since the fixed address is set, the digital signal processing circuit is in the reset state when the processing operation is started from the fixed address by the fixed address start signal, so that the program operation of the digital signal processing is stabilized.

(Embodiment) FIG. 1 is a control circuit diagram of a digital signal processing apparatus showing an embodiment of the present invention, FIG. 2 is a timing chart of respective input signals thereof, and FIG. 3 is a timing of signals of respective portions of FIG. It is a chart.

Reference numeral A is a digital signal processing circuit for program-controlling a digital signal. When a logic "0" is received at the reset terminal ▲ ▼, it is reset to a predetermined initial state when the operation clock terminal DCLK receives the clock. . And the zero start terminal ▲ ▼ is logical "1".
When the processing operation is received, the processing operation exits from address 0, and each time the operation clock terminal DCLK receives a clock, the program counter (not shown) is advanced by one to perform each processing operation. In addition, the zero start terminal ▲ ▼ is logical "0".
When receiving the clock, the program counter is set to address 0 when the clock is received at the operation clock terminal DCLK. The digital signal processing circuit A receives the internal clock and performs the processing operation. During the period when the internal clock is not applied, the processing operation including the reset operation is not performed. It is in a power state.

SYNC is a fixed address start signal, which forms a pulse signal of a constant cycle for periodically starting the program of the digital signal processing circuit A to a fixed address. CLK is an internal clock and forms a clock pulse as a timing for performing each digital signal processing of the digital signal processing circuit A. PCNT is a stop instruction signal, and instructs the digital signal processing circuit A to stop the processing operation while the signal is "0".

The flip-flop F1 is reset when the data terminal D receives "0" of the stop instruction signal PCNT and subsequently receives the falling edge of the internal clock CLK at the gate cp via the inverter G1, and the stop instruction signal PCNT is released. Then, when the signal PCNT becomes "1", it is similarly set by the falling edge of CLK.

The operation clock terminal DCLK receives the output Q of the flip-flop F1 and the internal clock CLK via the AND gate G2, and receives the internal clock CLK for the period in which the flip-flop F1 is set. That clock advances the program counter pc (shown in FIG. 3).

The flip-flops F2 to F5 form a delay circuit, are reset by receiving the falling edge of the stop instruction signal PCNT at each reset terminal R, and are reset to the data terminal D of the leading flip-flop F2.
Receives a logic "1" and outputs each output Q to the data terminal D of each next stage.
Then, when the stop instruction signal PCNT becomes "1", it is sequentially set every time the subsequent internal clock CLK is received by the gate terminal cp. That is, each of the flip-flops F2 to F5 is set sequentially delayed by one pulse of the internal clock CLK from the rising time of the stop instruction signal PCNT, so that the flip-flop F5 at the final stage is set to 4 times the internal clock CLK from the rising edge of the stop instruction signal PCNT. It is set with a delay of pulse. The flip-flop F5 is provided with a reset terminal ▲ ▼ for the digital signal processing circuit A at the time of the reset.
Is reset to "0", and at the time of setting,
Release the reset.

The flip-flops F6, F7 and the AND gate G3 form a differentiating circuit, and a pulse having the width of the cycle of the internal clock CLK at the first rising edge of the internal clock CLK after the fixed address start signal SYNC becomes “1”. Is output from the AND gate G3.

The flip-flop F8 and the flip-flops F2 to F5 form a start inhibition circuit, and the flip-flops F2 to F5 to
It is reset at the same time as F5, and is set when the flip-flop F6 is set after the flip-flop F5 is set. The NOR gate G4 receives the output of the AND gate G3 and the negative side output of the flip-flop F8 (indicated by ▲ ▼ in FIG. 3), and when these outputs are both "0", the zero start terminal ▲ ▼ is " 1 "and the processing operation of the digital signal processing circuit A is started.

In the above configuration, the fixed address start signal SYNC is generated at a constant cycle, and if the stop instruction signal PCNT continues to be "1", the flip-flop F5 is "1" and the digital signal processing circuit. The reset of A has been released, and the negative output of flip-flop F8 is "0" and NOR gate G4 is effectively accepting the input from gate G3. Therefore, the zero start terminal ▲ ▼ is "1" until the fixed address start signal SYNC is generated, and when the signal SYNC is generated, the flip-flop F6 is set at the subsequent rising edge of the internal clock CLK and the zero start terminal ▲ ▼ becomes " 0 ", the program counter pc becomes 0, and the processing program is started from the address 0.

Next, when "0" of the stop instruction signal PCNT occurs, the program processing is stopped since no pulse is given to the operation clock terminal DCLK thereafter. Continuous stop instruction signal PCNT is "1"
Returning to, the flip-flop F5 is set to the fourth pulse of the internal clock CLK, and the digital signal processing circuit A
Is reset. That is, the reset operation is performed during the four cycles of the internal clock CLK, and stable and reliable reset is performed.

After that, when the fixed address start signal SYNC is generated, the flip-flop F6 is set by the subsequent rise of the internal clock CLK, and the AND gate G3 becomes "1",
At the same time and thereafter, the negative side output of the flip-flop F8 becomes "0". At this time, the program counter pc is 0, the flip-flop F7 is set by the subsequent rise of the internal clock CLK, and the AND gate G3 becomes "0", so that the NOR gate G4 becomes "1" and the operation clock DCL
K advances program processing.

When the fixed address start signal SYNC occurs, for example, after the stop instruction signal PCNT is generated and before the flip-flop F5 is set, the waveforms of F6, F7, and G3 in FIG. However, since G is "1" at the time of the fall of G3, G4 maintains "0" and the program processing is stopped. That is, although the internal clock CLK is supplied, since the logic "0" is supplied to the zero start terminal ▲ ▼, the program counter is maintained at the address 0 (during repeated setting of the address 0) during that period, and the program processing is performed. Therefore, the digital signal processing circuit A remains in the initial setting state. When ▲ ▼ continues to be "0" at the time point of FIG. 3, the program processing is proceeded in the same manner as above.

As described above, according to the present invention, when the stop instruction signal from the processing operation stop circuit is received, the digital signal processing circuit is reset and the stop instruction signal is released,
Even if a fixed address start signal for program processing is generated before the subsequent predetermined time elapses, the processing does not start immediately at this time, but it starts after the predetermined time after the cancellation, so it is certain A reset and stable start is obtained.

[Brief description of drawings]

FIG. 1 is a control circuit diagram of a digital signal processing apparatus showing an embodiment of the present invention, FIG. 2 is a timing chart of signals of main parts of the circuit of FIG. 1, and FIG. 3 is each part of the circuit of FIG. 3 is a timing chart of the signal of FIG. A: Digital signal processing circuit SYNC: Fixed address start signal CLK: Internal clock PCNT: Stop instruction signal F5: Flip-flop (reset circuit) F8: Flip-flop (start inhibit circuit)

Claims (1)

[Claims] 1. A device for receiving a fixed address start signal every predetermined period to start a processing operation from a fixed address and performing digital signal processing for each internal clock, and receiving a stop instruction signal, the digital signal of the internal clock. A processing operation stop circuit for stopping the supply to the processing circuit, and an initial processing operation of the digital signal processing circuit for a time corresponding to at least several clocks of the internal clock from the time when the stop instruction signal is released. A reset circuit for giving a reset signal to be set to the state to the digital signal processing circuit, and a pull circuit after a time corresponding to at least the several clocks of the internal clock has elapsed from the time when the stop instruction signal is released. The program count of the digital signal processing circuit is continued until the fixed address start signal is received. The signal to be set to a fixed address, the digital signal processing device comprising providing a start prohibition circuit that gives to the digital signal processing circuit.