JPH07122089A - Flash type nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a flash memory which is highly integrated by providing an operating condition in which a source line commonly used between adjacent memory cells. CONSTITUTION:In a memory cell array, a source line of two adjacent column memory cells is comonly formed. The distance along the direction of the word line of the memory cell array is reduced compared with the conventional one. A positive high voltage is applied to a selective bit line only during a writing operation and the common source line and non-selective bit lines are all made operable in an open condition. Thus, source lines are not required to be separated between adjacent memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash type nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Among electrically rewritable non-volatile semiconductor memory devices, one having a function capable of simultaneously erasing a plurality of memory elements is referred to as a flash type non-volatile semiconductor memory device, hereinafter referred to as a flash memory. To call.

As an example of a memory element (hereinafter referred to as a memory cell) which is a basic unit of this type of memory device, a memory cell having a structure called a stacked gate type (stack gate type) is shown in FIG. In FIG. 5, a gate insulating film 2 having a film thickness of about 10 nm is formed on the surface of a P-type silicon substrate 1, a floating gate 3 made of polycrystalline silicon is provided on the gate insulating film 2, and further on the floating gate 3. Is formed on the floating gate insulating film 4 having a thickness of about 25 nm.
Has a control gate 5 on it. The surface of the semiconductor substrate 1 not covered with the floating gate 3 and the control gate 5 has N
The source 11 and the drain 10 are formed by the type impurities.

The operation of the memory cell of this type will be briefly described. To write (store data) in the memory cell, for example, +12 V is applied to the drain 10, 0 V (ground potential) is applied to the semiconductor substrate 1, and the control gate 5 is further applied. A ground potential is applied to (source 11 is open or ground potential). Since the floating gate is not connected to an external power source, its potential is controlled by the capacitance ratio formed by the gate insulating film 2 and the floating gate upper insulating film 4, the control gate,
It is uniquely determined from the potentials of the source, drain, and semiconductor substrate. By setting each electrode to such a potential, a strong electric field (10 MV /
cm or more) is applied to the gate insulating film 2,
A Fowler-Noldheim current based on a quantum mechanical tunnel effect flows in the gate insulating film, and an electron is extracted (released) from the floating gate 3 to the drain 10.
As a result, the memory cell is written (data storage).

On the other hand, erasing memory cells (erasing data)
Refers to injecting electrons into the floating gate of the memory cell in the written state as described above, but the following method is often adopted. The semiconductor substrate 1, the source 11 and the drain 10 are set to 0V (ground potential), and 14V is applied to the control gate electrode. Similar to the case of writing, a fairly strong electric field is applied to the gate insulating film 2 between the drain 10 and the floating gate 3 (10 MV / cm according to the potential of each part shown above).
Above) will be applied. Under such a strong electric field, it is possible to write in the gate insulating film in the same manner as writing.
A r-Noldheim current flows, and electrons are injected from the drain 10 to the floating gate 3 to erase the memory cell.

In this way, writing and erasing of memory cells are performed. In the case of a flash memory, writing is performed for each memory cell, whereas erasing is performed by simultaneously applying voltage to the control gates of memory cells within a certain range. Is applied. As a result, the memory cells in the above range can be erased collectively, and the erase time can be shortened even when the storage capacity of the storage device becomes large.

FIG. 3 schematically shows the arrangement and wiring of memory cells in a conventional flash memory. In FIG. 3, six memory cells A to F are arranged in a matrix of 2 columns and 3 rows, and the drains of the cells are column lines B1 and B2.
Sources are column lines S1 and S2 (source lines) to (bit lines)
And the control gates are row lines W1, W2, W3.
Connected to (word line). Write and erase operations in the conventional flash memory cell array will be described with reference to FIG.

When writing data to the memory cell A, the first
The word line W1 is applied with a ground potential, and the second and third word lines W2 and W3 are applied with a suitable positive voltage of, for example, about 5V, while the first bit line B1 is applied with about 12V. The second bit line B2 is set to the ground potential, and the first and second source lines S1 and S2 are set to the floating state (open state).

When each potential is set in this manner, a high voltage of 12 V is applied between the drain and the control gate of the memory cell A, so that the electrons accumulated in the floating gate are F.
The lower-Noldheim current draws the bit line B1 to which the drain is connected. On the other hand, in the other memory cells B to F, since a voltage smaller than that in the memory cell A is applied between the drain and the control gate, writing is difficult. That is, the memory cell B has 0V, the memory cells C and E have (12-5 =) 7V, and the memory cells D and F have (5-0 =) 5V. Only voltage is applied.

On the other hand, in the case of erasing, unlike the writing in the flash memory, the erasing is performed by applying a high voltage to the control gates of the memory cells within a certain range at the same time. In the example of FIG. 3, when erasing the memory cells A and B, the word line W
About 14 V is applied to the first and second word lines W
2 and W3 are set to the ground potential. In addition, the first bit line B1, the second bit line B2, and the first and second source lines S1 and S2 are all set to the ground potential. By setting such a potential, about 14 V is applied only to the memory cells A and B, electrons are injected into the floating gates of the memory cells A and B, and erasing is performed.

[0011]

In FIG. 3, the memory cells A, C, and E in the column direction and the memory cells B, D, and F adjacent to each other have a common source line, and as shown in FIG. If a common source line can be arranged in the middle of the column of cells, the average mutual interval in the row direction of the memory cell column can be reduced, and therefore the area occupied by the memory cell array can be reduced.

However, as described above, in the conventional flash memory, since a voltage of about 5 V is applied to the non-selected word lines W2 and W3 at the time of writing, the memory cells C to F become conductive or weakly conductive. When the source lines are shared as shown in FIG. 4, current paths (leakage current paths) of L1 and L2 are formed via the common source line. As a result, not only the current consumption at the time of writing increases, but also the potential of the bit line B1 drops depending on the degree of the leak current, which causes a decrease in the writing speed. Therefore, conventionally, the source lines of memory cells in different columns must be formed separately.

An object of the present invention is to make the source lines of the memory cell columns adjacent to each other in the row direction common, so that the average spacing in the row direction between the memory cells is reduced as compared with the conventional one, and the flash having higher integration is realized. It is to provide memory.

[0014]

In the flash memory of the present invention, the sources of the storage element groups of two adjacent columns are connected to a column line located in the middle of the columns of the storage element groups as a common source line. , The semiconductor substrate and the selected row line are set to the ground potential, a positive middle voltage is applied to each non-selected row line, and each column line including the common source line except the selected column line is in a floating state. In addition, the second positive high voltage is applied to the selected column line to realize the second storage state in which electrons are emitted from the floating gate of the selected storage element.

[0015]

A common source line is provided in the middle of two adjacent storage element columns to set the operating conditions of the storage element that can prevent the formation of a leak current path during writing.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an arrangement and wiring of memory cells in a flash memory according to an embodiment of the present invention together with peripheral circuits.

In FIG. 1, among the drains of the memory cells A to F, the drains of A, C and E are column lines B1, B, D and F.
Of the column lines B1,
B2 is connected to the high voltage generating circuit C4 and the sense amplifier C5 via the column switching transistors S1 and S2, which are NMOSFETs, respectively. Here, the input gate electrodes of the column switching transistors S1 and S2 are all connected to the column decoder C3. The control gates of the memory cells A to F are connected to the row decoder C2 via the word lines W1 to W3. Further, the common source line S of the memory cells A to F
Is connected to the ground potential via a source switch transistor SST composed of, for example, NMOSFET. Here, the input gate electrode of the source switch transistor SST is connected to the source switch circuit C1.

In the block configuration of FIG. 1, for example, a first electron injection into the floating gate electrodes of the memory cells A to B is performed.
To realize the memory state of the column switching transistor S first
After making S1 and S2 conductive by the signal from the column decoder,
The ground voltage is generated from the high voltage generation circuit C4, and the column line B1,
Set B2 to ground potential. In addition, word lines W2, W
3, the common source S is set to the ground potential, the word line W1 connected to the memory cells A to B is selected from the row decoder circuit C2, and a positive high voltage of, for example, about 14V is applied. Further, the substrate of the device is set to the ground potential throughout.
By setting the potentials of the electrodes in this way, electrons are injected into the floating gate electrodes of the memory cells A to B in the same manner as in the conventional example (explanation of FIG. 3), and as a result, The first storage state in which electrons are accumulated is realized.

On the other hand, for example, in order to realize the second storage state in which electrons are emitted from the floating gate electrode of the memory cell A, first, the column switching transistor S1 is turned on by a signal from the column decoder, and then the high voltage is applied. The generation circuit C4 generates a positive voltage of, for example, about 12 V, and the column line B1 is set to a positive high voltage. At that time, a ground potential is generated in the column switching transistor S2 by a signal from the column decoder to make it non-conductive,
The column line B2 is set in a floating state. Further, the signal from the source switch circuit C1 is used to supply the source switch transistor S.
ST is turned off and the common source line S is set in a floating state. Finally, from the row decoder circuit C2 to the memory cell A
The word line W1 connected to B is selected and set to the ground potential, and the other word lines W2 to W3 are set to the potential of about 5V, for example. Further, the substrate of the device is set to the ground potential throughout. By setting the potentials of the respective electrodes in this manner, electrons are emitted from the floating gate electrode of the memory cell A, and as a result, the second storage state in which electrons are not stored is realized. In this case, since the non-selected column line B2 and the common source line S are set in the floating state, the leak current path (L1 and L2 shown in FIG. 4) is not formed.

FIG. 2 is a block diagram showing the arrangement and wiring of memory cells according to the second embodiment of the present invention together with peripheral circuits.

In FIG. 2, main column lines B1 and B2 connected to the high voltage circuit C4 and the sense amplifier C5 via the column switching transistors S1 and S2, respectively, extend from the main column line B1 to the column selection transistor BS11. BS12
.. through the sub-column lines B11, B12 ...
From the main column line B2, column selection transistors BS21 and BS2
The sub column lines B21, B22 ... Are branched via 2 ... The connection to the sub-column lines B11, B21 or B12, B22 of each memory cell and the source line S arranged in the middle thereof is exactly the same as the connection to the column lines B1, B2 and the source line S in FIG.

By thus forming the column lines into a main and sub-layered structure, even when a large number of memory cells are connected in the column line direction, a specific sub column line is selected when a specific memory cell is selected. Since only the main column line needs to be selected, the capacity of the main column line can be reduced and the operation can be speeded up.

[0024]

As described above, according to the present invention, the source line common to the memory elements of both columns is provided in the middle of the two adjacent memory element columns to reduce the average spacing in the row direction between the memory elements. In that case, by setting the non-selected bit line and the common source line at the time of writing to the floating state as the operating condition of the memory element, the formation of the leak current path is prevented, and the memory cell array area excluding the peripheral circuit is roughly There is an effect that the size can be reduced to 2/3 (67%) and the device can be highly integrated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arrangement and wiring of memory cells in a flash memory according to an embodiment of the present invention together with peripheral circuits.

FIG. 2 is a block diagram showing an arrangement / wiring of memory cells according to a second embodiment of the present invention together with peripheral circuits.

FIG. 3 is a schematic diagram showing an arrangement / wiring of memory cells in a conventional flash memory.

FIG. 4 is an explanatory diagram in the case where the source wiring is common in FIG.

FIG. 5 is a diagram showing a structure of a stacked gate type memory cell.

[Explanation of symbols]

1 P-type silicon substrate 2 Gate insulating film 3 Floating gate 4 Floating gate upper insulating film 5 Control gate 10 Drain 11 Source C1 Source switch circuit C2 Row decoder C3 Column decoder C4 High voltage generation circuit C5 Sense amplifier S1, S2 Column switching transistor B1 , B2 column line, main column line W1, W2, W3 word line S source line, common source line SST source selection transistor AF memory cell BS11, BS12, BS21, BS22 column selection transistor B11, B12, B21, B22 sub column line

Claims (3)

[Claims] 1. A structure having a floating gate provided between a control gate of a MOS transistor and a semiconductor substrate, wherein a first memory state is realized by injecting electrons into the floating gate, and electrons are injected from the floating gate. A large number of storage elements that realize the second storage state by being discharged are arranged in a matrix, and a column-direction conductor line or column line to which the source and drain of each element are connected and a row to which a control gate is connected are connected. Direction, that is, a row line, and the semiconductor substrate, each column line, and each unselected row line are set to the ground potential, and a first positive high voltage is applied to the selected row line to select the selected row line. In a flash-type nonvolatile semiconductor memory device that realizes the first storage state in a stored memory element group, the sources of the memory element groups in two adjacent columns are in the middle of the columns of the element group. The column line located is connected to this as a common source line, the semiconductor substrate and the selected row line are set to the ground potential, a positive middle voltage is applied to each unselected row line, and the common source line is connected. And each column line except the selected column line is placed in a floating state, and a second positive high voltage is applied to the selected column line, so that the second column is applied to the selected storage element. A flash-type non-volatile semiconductor memory device characterized by realizing a memory state. 2. A plurality of sub-column lines are branched from the column lines connected to the drains of the storage elements via column selection means, respectively.
The flash nonvolatile semiconductor memory device according to claim 1, wherein the drain of the memory element is connected to each sub column line. 3. The positive voltage applied to the storage element for realizing the first and second storage states of the storage element is all 14 V or less, according to claim 1. Flash type nonvolatile semiconductor memory device.