JPH07121989A - Scramble recorder/scramble reproducer - Google Patents

Abstract

PURPOSE:To obtain a scrambler which can freely alter readability at the time of reproducing without providing a specific circuit. CONSTITUTION:An error correction encoder 13 of a scramble recorder inverts parity codes P, Q at a predetermined period. Data scrambled by using a user's bit of a subcode is added to an encoder 12 and recorded. A scramble reproducer decodes an error correction by an error correction decoder 13 with a reproduction parity as it is when the scrambled data is reproduced as it is. When the scrambled data is normally reproduced, the subcode is extracted from the reproduced data by the decoder 12 to extract data for indicating scrambling, the codes P, Q are returned to the original, and then an error is corrected by the decoder 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble recording device for scramble recording an audio signal or the like to prevent illegal copying and a scramble reproducing device for descramble reproduction.

[0002]

2. Description of the Related Art As a scrambler of this type, for example, as disclosed in Japanese Patent Application Laid-Open No. 4-285763, first and second analog audio signals are alternately switched at a predetermined cycle and a first audio carrier wave is used. There is known a method of frequency-multiplex-recording an FM-modulated signal and an FM-modulated signal with a second sound carrier on a recording medium. Further, in order to realize this scramble method, a circuit for alternately switching the first and second analog audio signals at a predetermined cycle is used. In the digital scrambling method, the first and second
Another possible method is to periodically switch the audio signal in the unit of frame.

[0003]

However, in the above-described conventional scrambling method, since only two audio signals are periodically switched, there is no degree of freedom in scrambling, and therefore the clarity of the reproduced signal (reader (Ability) cannot be changed freely. In addition, since descrambling is easy, it is not practically sufficient, and there is a problem that a special circuit for periodically switching is required.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a scramble recording device and a scramble reproducing device which can freely change the clarity at the time of reproduction without providing a special circuit.

[0005]

In order to achieve the above object, the present invention provides an error correction method using a Reed-Solomon code in the scramble mode in view of the fact that no correction error occurs if error correction is normally performed. A correction error is intentionally generated. That is, according to the present invention, a coding unit that adds a parity to information and performs error correction coding with a Reed-Solomon code, and a parity that is added by the coding unit when data is not scramble-recorded is left unchanged, In the case of scramble recording, there is provided a scramble recording device having a scramble means for inverting the parity at a predetermined cycle and adding side information indicating that the parity has been inverted for each predetermined cycle. Further, according to the present invention,
Decoding means for performing error correction decoding by calculating the syndrome of reproduction data having parity, and when reproducing scrambled data as it is, the decoding means controls so as to perform error correction decoding with the reproduction parity as it is. When the scrambled data is normally reproduced, the side information is extracted from the reproduced data, the reproduction parity is returned to the original at each predetermined cycle, and then the decoding means is controlled to perform error correction decoding. There is provided a scramble reproduction device having a descramble means.

[0006]

According to the present invention, when scramble-recording data, the parity is inverted at a predetermined cycle, and if this reproduced data is directly error-corrected and decoded, a correction error occurs,
It cannot be played normally. Side information from playback data (so-called subcode, etc., hereinafter referred to as subcode)
Is extracted, the parity is returned to the original state, and error correction decoding is performed, no correction error occurs and normal reproduction is possible. Therefore, by making the period of parity inversion variable, the clarity at the time of reproduction can be freely changed without providing a special circuit.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an outline of an embodiment of a scramble recording device according to the present invention, FIG. 2 is a block diagram showing an outline of an embodiment of a scramble reproducing device according to the present invention, and FIG. 3 is an error correction of FIG. A block diagram showing an example of a scramble circuit in the encoding unit and a descramble circuit in the error correction decoding unit of FIG. 2, FIG. 4 is a block diagram showing the error correction decoding unit of FIG. 2 in detail, and FIG. 5 is an error of FIG. FIG. 6 is a flowchart for explaining the operation of the correction decoding unit for error-correcting the C1 sequence of the double Reed-Solomon code. FIG. 6 shows the operation of the error-correction decoding unit of FIG.
6 is a flowchart for explaining an operation of error correcting two streams.

Digitally recorded P is applied to the input terminal 11 '.
The CM signal and the P and Q parity codes for error correction are input, and this input signal is encoded by the encoder 20 in a predetermined format together with subcodes such as user's bits. The encoded data is corrected and coded by the error correction coding unit 30 using, for example, a Reed-Solomon code of only the C1 series or a double Reed-Solomon code of the C1 series and the C2 series, and output via the output buffer 50 to an output terminal. 16 'is output and recorded on the recording medium.

The error correction coding unit 30 of this embodiment can use a scramble circuit as shown in FIG. 3, for example, and when the scramble control signal K'is input from the function key 40, the error correction coding unit 30. In, the parity codes P and Q are inverted at a predetermined cycle (described later). When the parity codes P and Q are inverted in this way, the encoder 20 generates data indicating that scrambling has been performed using the user's bits of the subcode.

Next, an outline of the scramble reproducing apparatus of this embodiment will be described with reference to FIG. The signal input to the input terminal 11 is a PCM signal and P and Q parity codes for error correction, a subcode, etc. are encoded in a predetermined format. When the input signal is input to the input terminal 11, the decoder 12 causes the PCM signal to be input. The signal, P, Q code, subcode, etc. are decoded and applied to the error correction decoding unit 13 shown in detail in FIG.

The error correction decoding unit 13 performs error correction using, for example, a double Reed-Solomon code of C1 series and C2 series, and the scramble mode is not released from the function key 14 via the normalization instructing section 13B. In this case, the syndrome is calculated by keeping the P and Q codes as they are by the control signal K, while when the scramble mode is released, the P and Q codes are inverted at the above cycle extracted from the sub code to The error correction is performed by returning to the above and calculating the syndrome. The signal error-corrected by the error correction unit 3 is output to the output terminal 16 via the output buffer 15. The scramble mode is canceled by inputting a password, for example, from the function key 14.

Here, the error correction coding unit 30 on the recording side
The scramble circuit and the descramble circuit in the error correction decoding unit 13 can be configured by the same circuit as shown in FIG. In FIG. 3, the parity code P, Q is supplied to the input terminal 17A, and the parity code P,
Q passes through the inverting buffer 18A or the non-inverting buffer 18B and is output to the output terminal 19. Inversion buffer 18A
Is controlled by the control signal Z applied to the control terminal 17B, and the non-inverting buffer 18B controls the control signal Z by the inverter 1
It is controlled by the control signal Z inverted by 8C.

Therefore, the scramble circuit shown in FIG. 3 is provided in the error correction coding section 30 shown in FIG. 1, and the codes P and Q are inverted at a predetermined cycle so that the clarity at the time of reproduction is different from the scramble recording. can do. Further, by providing the descramble circuit shown in FIG. 3 in the error correction decoding unit 13 shown in FIG. 2 (specifically, the arithmetic circuit 4 shown in FIG. 4), the codes P and Q are inverted at the above cycle when the scramble mode is released. Then, the error is corrected normally without causing a correction error.

Next, the error correction decoding unit 13 shown in FIG. 4 will be described in detail. First, let S1, S2, S3, S4, and S5 be the receiving-side syndromes for errors of 3 words or more, and let the error values be e1, e2, and e3, the following equation holds (the following addition is modulo 2 addition (exclusive OR) )).

[0015]

[Number 1] S0 = e1 + e2 + e3 S1 = x1 * e1 + x2 * e2 + x3 * e3 S2 = x1 2 * e1 + x2 2 * e2 + x3 2 * e3 S3 = x1 3 * e1 + x2 3 * e2 + x3 3 * e3 S4 = x1 4 * e1 + x2 4 * e2 + x3 ⁴ * e3 S5 = x1 ⁵ * e1 + x2 ⁵ * e2 + x3 ⁵ * e3

Here, x1, x2 and x3 indicate error positions (error locations). Further, when a 3-word error occurs, the following equation is obtained by first transforming the equation of the syndrome assuming the error position x1.

[0017]

## EQU00002 ## T0 = S1 + x1 * S0 = (x1 + x2) * e2 + (x1 + x3) * e3 T1 = S2 + x1 * S1 = x2 * (x1 + x2) * e2 + x3 * (x1 + x3) * e3 T2 = S3 + x1 * S2 = x2 * ¹ * 2 ) * E2 + x3 ² * (x1 + x3) * e3 T3 = S4 + x1 * S3 = x2 ³ * (x1 + x2) * e2 + x3 ³ * (x1 + x3) * e3 T4 = S5 + x1 * S4 = x2 ⁴ * (x1 + x2) * e2 + x3 ⁴ * * E3 Next, by further modifying this equation,

[0018]

## EQU3 ## If T1 ² + T0 * T2 = P1 T2 ² + T1 * T3 = P2 T3 ² + T4 * T2 = P3,

[0019]

[Number 4] P1 = (x1 + x2) * (x2 + x3) 2 * (x1 + x3) * e2 * e3 P2 = x2 * x3 * (x1 + x2) * (x2 + x3) 2 * (x1 + x3) * e2 * e3 P3 = x2 2 * x3 ³ * (x1 + x2) * (x2 + x3) ² * (x1 + x3) * e2 * e3 Here, in order to erase the error position x1 from each equation (Equation 4) that gives P1, P2, and P3,

[0020]

## EQU00005 ## If A = P2 / P1 = x2 * x3 B = P3 / P2 = x2 * x3, and if the value of the position xi is correct, then A = B ... (1) holds, and A + B = D To do.

In the present embodiment, the value of the error position xi is assumed, the arithmetic circuit 4 calculates the above D, and the PC control unit 6 obtains the value of the position xi at which D becomes "0".
In this case, the value of the position xi normally changes from “1” to n (n is the number of codewords) in sequence, and there are three values of the position xi at which the value of D becomes “0”. Then, these three values are stored in the arithmetic register 5. Here, since the values of the position xi stored in the arithmetic register 5 are x1, x2, and x3, x1, x2, and x3 are known after that, and the values x1, x2, and x3 are used as follows. Then, the error values e1, e2, e3 are obtained.

[0022]

## EQU00006 ## E = S2 + (x1 + x2) * S1 + x1 * x2 * S0 is calculated, E = (x1 + x3) * (x2 + x3) * e3 Therefore, E / (x1 + x3) * (x2 + x3) = e3

First, the value e3 is calculated by calculating, and then the syndrome is corrected by the value e3 as follows.

[0024]

## EQU00007 ## S0m = S0 + e3 = e1 + e2 S1m = S1 + x3 * e3 = x1 * e1 + x2 * e2 S2m = S2 + x3 ³ * e3 = x1 ² * e1 + x2 ² * e2 Then,

[0025]

## EQU8 ## F = S1m + x1 * S0m = (x1 + x2) * e2 ∴F / (x1 + x2) = e2 is calculated, and finally S0m + e2 = e1

The positions x1, x2, x3 and the values e1, e2, e3 of all the errors are obtained by calculating
Therefore, a 3-word error is required. The error correction decoding unit 13 of the present embodiment will be described with reference to FIG.
This control program is stored in 8, and is read by a program counter (PC) 7 under the control of a program counter (PC) control unit 6 and decoded by a decoder 9 to generate a syndrome check unit 1, a syndrome register 2, and an input selector. 3 and the arithmetic circuit 4.

As an example, the syndrome check unit 1 in the case of 6 parities is composed of parallel 6-stage adders, registers, and multipliers of coefficients α to α ⁵ . In each stage, the syndromes S0 to S5 are obtained for the input data Wi (i = 0 to 5) by the following calculation, and the syndromes S0 to S5 are stored in the syndrome register 2 shown in FIG.

[0028]

## EQU9 ## S0 = ΣWi S1 = Σα ⁱ Wi S2 = Σα ²ⁱ Wi S3 = Σα ³ⁱ Wi S4 = Σα ⁴ⁱ Wi S5 = Σα ⁵ⁱ Wi

The syndrome Si read out from the syndrome register 2 and the current error position xi,
The intermediate operation results xi and ei of the error position and the value stored in the operation register 5 are selected by the input selector 3 based on the selection signal from the decoder 9 and the product-sum operation is performed by the operation circuit 4. The branching and the like due to the selection of the data necessary for the following calculation and the condition determination are performed by the PC based on the syndrome Si stored in the syndrome register 2 and the D (= A + B) stored in the calculation register 5.
It is controlled by the control unit 6.

The operation of this embodiment will be described in detail. First, the arithmetic circuit 4 checks the value of the syndrome Si, and this value determines the correction operation mode. 1. When all the values of the syndrome Si are "0" In this case, it is determined that there is no error. This operation is S
It is determined by the result of sequentially adding the values of i, that is, ΣSi
When = 0, the error flag is set to “0” and the process ends. 2. When the addition result ΣSi of the syndrome Si is not “0” First, it is assumed that the number of errors is 1, and at this time,

[0031]

## EQU10 ## S0 = x1 * e1 S1 = x1 ² * e1 S2 = x1 ³ * e1 S3 = x1 ⁴ * e1

It becomes Therefore, if there is one error, the minimum condition is

[0033]

[Equation 11] As A = S1 ² + S0 * S2 B = S2 ² + S1 * S3 C = S0 * S3 + S1 * S2, A = B = C = 0

If the condition is satisfied, the variable x1 is obtained with S1 / S0 = x1, and the data value at the position of this variable x1 is set to w.
Since 1e is w1e = w1 + e1, the correct data value w1 becomes w1 = w1e + e1. The data value w1e of the variable x1 is replaced with the correct value w1 to perform error flag processing, and the correction is completed.

3. In the above 2, if A = B = C = 0 is not established, the number of errors is set to 2 or more. Here, the input data of the arithmetic circuit 4 is S0 to S5. First, the value x1 which does not actually exist is substituted for the error position xi, and Ti and Pi are obtained as follows.

[0036]

Equation 12] T0 = S1 + x1 * S0 T1 = S2 + x1 * S1 T2 = S3 + x1 * S2 T3 = S4 + x1 * S3 T4 = S5 + x1 * S4 P1 = T1 2 + T0 * T2 P2 = T2 2 + T1 * T3 P3 = T3 3 + T2 * T4

Next, when x1 is sequentially changed from 1 to n, 3-1. When P1 = P2 = P3 = 0 holds, the number of errors can be determined to be two. At this time

[0038]

(13) A = T1 / T0 B = T3 / T2

As a result, the value of xi at which A + B = D becomes "0" is sequentially stored in the arithmetic register 5. In this calculation, the parity part of the codeword can be omitted in order to reduce the processing time. By the above calculation,
When the number of errors is two, the values of the variable xi are x1 and x2, and the value of D is “0” twice. Therefore, the values of x1 and x2 are obtained. The error values e1 and e2 are

[0040]

[Equation 14] e2 = T0 / (x1 + x2) e1 = S0 + e2

The values w1 and w2 are calculated as w1 + e1 and w1 + e1, respectively.
The error flag processing is performed as w2 + e2, and the correction is completed. 3-2. When P1, P2 and P3 do not become "0" at the same time In this embodiment, in order to correct the 3-word error, the error position x1 is deleted from each equation (Equation 4) that gives P1, P2 and P3 described above. Is used.

[0042]

[Expression 15] A = P2 / P1 B = P3 / P2

As a result, if x1 is correct, A = B holds. Therefore, the value of xi for A + B = D = 0 is sequentially stored in the register 5. Here, if the number of errors is 3, D
Value becomes “0” three times, so error positions x1, x2,
x3 is obtained, and then these error positions x1, x2, x3
The error values e1, e2, and e3 are obtained from First,

[0044]

When E = x2 * T0 + T1 is calculated, E = (x1 + x3) * (x2 + x3) * e3 Therefore, E / (x1 + x3) * (x2 + x3) = e3

Is calculated to obtain e3, and this e3 is used to correct the syndrome as follows.

[0046]

S0m = S0 + e3 = e1 + e2 S1m = S1 + x3 * e3 = x1 * e1 + x2 * e2 S2m = S2 + x3 ² * e3 = x1 ² * e1 + x2 ² * e2 Next, F = S1m + x1 * S0m is calculated and F = (X1 + x2) * e2 ∴F / (x1 + x2) = e2

Then, by finally obtaining S0m + e2 = e1, all error positions x1 to x3 and the value e are obtained.
1 to e3 are required. 3-3. When there is no xi for D = 0 In this case, the number of errors is considered to be four or more, so only error flag processing is performed and no correction is performed.

Here, as described above, in the normal error correction, the value of the syndrome Si is calculated by the arithmetic circuit 4 and
Signals A, B and C shown in FIG.
P3 is checked and the corrective operation mode is determined based on this value as follows. 1. When all the values of the syndrome Si are "0" ... No error occurs. 2. When the addition result ΣSi of the syndrome Si is not “0”, (1) the number of errors is 1 ... A = B = C = 0. (2) The number of errors is 2 ... A = B = C = 0 does not hold, and P1 = P2 = P3 = 0 holds. (3) The number of errors is 3 or more ... A = B = C = 0 does not hold, and P1 = P2 = P3 = 0 does not hold.

By the way, the number of rewritable data when the number of errors is 1 in 2 (1) of the condition 2 described above, the number of rewritable data is 1 out of 24 in the CD and 1 out of 32 in the DCC.
In (2), the number of rewritable data when the number of errors is 2 is 2 out of 24 in CD, 2 in 32 out of DCC, and 2 in 3 (3) when the number of errors is rewritable. The number of possible data is 3 out of 24 in CD and 3 out of 32 in DCC, which is an appropriate number. Therefore, in the case of scramble recording, the intelligibility at the time of reproduction can be freely changed without arranging a special circuit by inverting the parity in such a cycle.

Next, referring to FIG. 5 and FIG.
The process of error correcting the C1 and C2 sequences of the multiple Reed-Solomon code will be described. First, the C1 correction process will be described with reference to FIG. When the C1 correction process starts (step 101), first, the syndromes S0 to S3 are checked by the equation [C1] shown in the upper part of the following equation (Equation 18) (step 102), and then the following equation (Equation 19) is shown. The syndromes S0 to S3 are converted into indices (α → i) (step 103).

[0051]

[C1] S0 = W0 + W1 + W2 + ... + W23 S1 = α ²³ W0 + α ²² W1 + α ²¹ W2 + ... + W23 S2 = α ⁴⁶ W0 + α ⁴⁴ W1 + α ⁴² W2 + ・ ・ ・ ・ ・ + W23 S3 = α ⁶⁹ W0 + α ⁶⁶ W1 + α ⁶³ W2 + ... + W23 [C2] S0 = W0 + W1 + W2 + ... + W31 S1 = α ³¹ W0 + α ³⁰ W1 + α ²⁹ W2 + ・ ・ ・ ・ ・ + W31 S2 = α ⁶² W0 + α ⁶⁰ W1 + α ⁵⁸ W2 + ・ ・ ・ ・ ・ + W31 S3 = α ⁹³ W0 + α ⁹⁰ W1 + α ⁸⁷ W2 + ・ ・ ・ ・ ・ + W31 S4 = α ¹²⁴ W0 + α ¹²⁰ W1 + α ¹¹⁶ W2 + ・ ・ ・ ・ ・ + W31 S5 = α ¹⁵⁵ W0 + α ¹⁵⁰ W1 + α ¹⁴⁵ W2 + ・ ・ ・ ・・ + W31

[0052]

[Formula 19] C1: S0 S1 S2 S3 C2: S0 S1 S2 S3 S4 S5

Next, it is judged whether or not all the syndromes S0 to S3 are "0" (step 104). If YES, all of the C1 error flags F0, F1 and F2 are "0".
Is written (step 105), the block address is incremented by 1 (step 106), and the above process is repeated until all blocks are completed (step 10).
7).

On the other hand, when all the syndromes S0 to S3 are not "0" in step 104, first, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated based on the following equation (Equation 20), Then, it is determined by the following equation (Equation 21) whether or not there is a one-word error (step 109).

[0055]

Σ1 = S1 + S0 * S2 σ2 = S2 + S1 * S3 σ3 = S1 * S2 + S0 * S3

[0056]

Σ1 + σ2 + σ3 = 0 1 word error σ1 + σ2 + σ3 ≠ 0 1 word error or more

In the case of a 1-word error, 1-word correction is performed based on the following equation (Equation 22) to write the correction data Wi (step 110), and then C1 error flag F0 is set to "1" based on Table 1 as well. "1" is written (step 111). Next, the block address is incremented by 1 (step 112) and the process proceeds to step 107.

[0058]

[Equation 22] [1 word correction] Error position: Xi = S1 / S0 Error value: Ei = S0 Correction: Wi = S0 + Di (Di ... error data)

[0059]

[Table 1]

On the other hand, if the one-word error is not found in step 109, X1, X2, ψ1 to ψ3 for detecting a two-word error are calculated by the following equation (equation 23), and then the following equation (equation 24). Then, it is determined whether or not there is a 2-word error (step 114).

[0061]

[Equation 23]

[0062]

Ψ1 + ψ2 + ψ3 = 0 2 word error ψ1 + ψ2 + ψ3 ≠ 0 2 word error or more

In the case of a 2-word error, 2-word correction is performed based on the following equation (Equation 25) (step 115), and the correction data Wi and Wj are written by the following equation (Equation 9) (step 116), Then, as shown in Table 1, C
1 "1" is written in the error flags F0 and F1 (step 117). Next, the block address is incremented by 1 (step 118) and the process proceeds to step 107.

[0064]

[Equation 25]

[0065]

[Equation 26] [Wi, Wj correction] From S0 = Ei + Ej S1 = Xi * Ei + Xj * Ej Xj * S0 + S1 = (Xi + Xj) * Ei Ei = (Xj * S0 + S1) / C1 Ej = S0 + Ei Wi = Ei + JiDj Wi

If no 2-word error occurs in step 114, "1" is written in both C1 error flags F0, F1, and F2 as shown in Table 1 (step 1
19), then the block address is incremented by 1 (step 120) and the routine proceeds to step 107.

Next, the C2 correction process will be described with reference to FIG. The C2 correction process is started after the C1 correction process is completed (step 121), and first, the syndromes S0 to S5 are checked by the lower stage [C2] of the above equation (Equation 18) (step 122), and then the above equation (Equation 18). The syndromes S0 to S5 shown in the lower part of 19) are converted into indices (α → i) (step 123). Next, the C1 error flag is read and the number N of error flags is calculated by the following equation (Equation 27).
(E) and the error position Xi are detected (step 12
4).

[0068]

[C1 Flag Calculate] Read: C1 Flag Location Count: C1 Flag Number Resister: C1 Flag Location X1, X2, X3
X4, X5, X6

Then, it is determined whether the number of errors is "0" by determining whether all the syndromes S0 to S5 are "0" (step 126).
2 "0" is written in the error flags F0 and F1 (step 127), the block address is incremented by 1 (step 128), and if all blocks are not completed, the process returns to step 122, and if completed, this C
2 The correction process ends (step 129).

On the other hand, when all the syndromes S0 to S5 are not "0" in step 126, the above equation (Equation 2)
Based on 0), it is determined whether or not there is a one-word error (step 132). In the case of a 1-word error, 1-word correction is performed based on the above equation (Equation 21) to obtain the corrected data Wi.
Is written (step 133), and then “0” is written to the C2 error flags F0 and F1 (step 134).
Then, the block address is incremented by 1 (step 135) and the process proceeds to step 129.

Then, in the present invention, if the one-word error is not detected in step 132, it is judged whether or not the error number ERR in frame units exceeds the set value N '(step 136). 136
Go to the following, and if it exceeds, go to the erasure routine.

In step 137, it is determined whether or not there is a two-word error by the above equation (equation 24), and if there is a two-word error, two word correction is performed based on the above equation (equation 25) (step 138). Corrected data W by the formula (Equation 26)
i, Wj are written (step 139), and then "0" is written in the C2 error flags F0, F1 (step 14).
0). Next, the block address is incremented by 1 (step 141) and the process proceeds to step 129. Also,
If the two-word error is not found in step 137, the process proceeds to the erasure routine. In the erasure routine, the syndrome is corrected as follows according to the number N of error flags.

[0073]

Equation 28] [6Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E4 * S1 + E5 * S0 Y6 = T5 / I6 [syndrome correcting] S0 + Y6 → S0 S1 + Y6 * X6 → S1 S2 + Y6 * X6 2 → S2 S3 + Y6 * X6 3 → S3 S4 + Y6 * X6 ⁴ → S4

[0074]

[Equation 29] [5Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D1 * S1 + D
4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X5 ² → S2 S3 + Y5 * X5 ³ → S3

[0075]

[4 Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Syndrome correction] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X4 ² → S2

[0076]

[3 Erasure, Y3] T2 = S2 + B1 * S1 + B2 * S0 Y3 = T2 / I3 [Syndrome correction] S0 + Y3 → S0 S1 + Y3 * X3 → S1

[0077]

[Equation 32] [2Erasure, Y2] [1Erasure, Y1] T1 = S1 + X1 * S0 Y2 = T1 / I2 Y1 = S0 + Y2

[0078]

As described above, according to the present invention, when data is scrambled and recorded, the parity is inverted at a predetermined cycle. Therefore, if this reproduced data is error-corrected and decoded, a correction error occurs, When the subcode is extracted from the reproduction data, the parity is restored and the error correction decoding is performed, the correction error does not occur and the reproduction can be normally performed. Therefore, by making the period of parity inversion variable, the clarity at the time of reproduction can be freely changed without providing a special circuit.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of a scramble recording device according to the present invention.

FIG. 2 is a block diagram showing an outline of one embodiment of a scramble reproduction device according to the present invention.

3 is a block diagram showing an example of a scramble circuit in the error correction coding unit of FIG. 1 and a descramble circuit in the error correction decoding unit of FIG.

FIG. 4 is a block diagram showing the error correction decoding unit of FIG. 2 in detail.

5 is a flowchart for explaining an operation of the error correction decoding unit of FIG. 2 for error correcting the C1 sequence of the double Reed-Solomon code.

6 is a flowchart for explaining an operation of the error correction decoding unit of FIG. 2 for error correcting the C2 sequence of the double Reed-Solomon code.

[Explanation of symbols]

1 syndrome check unit 2 syndrome register 3 input selector 4 arithmetic circuit 5 arithmetic register 6 PC (program counter) control unit 7 program counter (PC) 8 ROM 9, 12 decoder 13 error correction decoding unit (decoding means) 13B normalization instruction unit (Descrambling means comprises decoder 12 and function key 14) 14,40 Function key 18A Non-inversion buffer 18B Inversion buffer 18C Inverter 20 Encoder (Error correction encoding section 30 and function key 40 constitute scrambling means) 30 Error correction coding unit (coding means)

Claims (2)

[Claims] 1. A coding means for adding parity to information and error-correcting coding with a Reed-Solomon code, and scramble recording of data while leaving the parity added by the coding means when data is not scrambled recorded. In this case, the scramble recording device includes a scramble unit that inverts the parity at a predetermined cycle and adds side information indicating that the parity has been inverted at each predetermined cycle and records the side information. 2. Decoding means for performing error correction decoding by calculating the syndrome of reproduced data having parity, and when reproducing scrambled data as it is, the decoding means carries out error correction decoding while leaving reproduced parity as it is. When the scrambled data is reproduced normally, the side information is extracted from the reproduced data and the reproduction parity is returned to the original at each of the predetermined cycles, and then the decoding means performs error correction decoding. A scramble reproducing apparatus having a descrambling means for controlling to perform.