JPH07120971B2 - Semi-fixed equalizer - Google Patents
Semi-fixed equalizerInfo
- Publication number
- JPH07120971B2 JPH07120971B2 JP61169345A JP16934586A JPH07120971B2 JP H07120971 B2 JPH07120971 B2 JP H07120971B2 JP 61169345 A JP61169345 A JP 61169345A JP 16934586 A JP16934586 A JP 16934586A JP H07120971 B2 JPH07120971 B2 JP H07120971B2
- Authority
- JP
- Japan
- Prior art keywords
- equalizer
- equalizers
- delay
- amplitude
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半固定等化器の自動設定装置に係り、特に特
定被呼者に対し、予め記憶されている情報に基づき、等
化器を自動的に選択設定して、特定伝送歪に対して最適
な補償を行う半固定等化器の自動設定装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic setting device for a semi-fixed equalizer, and particularly to an equalizer based on information stored in advance for a specific called party. The present invention relates to an automatic setting device for a semi-fixed equalizer, which automatically selects and sets the above to optimally compensate for specific transmission distortion.
一般交換回線に生ずる伝送歪には、振幅歪の他に遅延歪
があるが、変復調器によって補償しきれない、このよう
な伝送歪は等化器を挿入することによって補償すること
ができる。Transmission distortion that occurs in a general exchange line includes delay distortion in addition to amplitude distortion, which cannot be completely compensated by a modulator / demodulator. Such transmission distortion can be compensated by inserting an equalizer.
一方、一般交換回線の場合、回線を介して通信する相手
が複数存在し、相手方が変われば、両者を結ぶ回線構成
も変わるため、固定等化器により特定回線構成のみ等化
処理を施して、その回線のみのデータ品質を改善しても
意味がなく、また全ての相手方に対し、個々に全て固定
等化器を設置することは到底不可能に近い。従って、従
来にあっては、簡易な固定等化器（FIXED COMPROMISE
EQUALIZER）を用いていた。On the other hand, in the case of a general switched line, there are multiple parties communicating via the line, and if the other party changes, the line configuration connecting the two will also change, so the fixed line equalizer performs equalization processing only on the specific line configuration. There is no point in improving the data quality of only that line, and it is almost impossible to install fixed equalizers individually for all parties. Therefore, in the past, a simple fixed equalizer (FIXED COMPROMISE
EQUALIZER) was used.
しかしながら、従来の簡易な固定等化器を用いるという
方法では、伝送歪が少ない回路にあっては、逆に伝送歪
を増加させ、データ品質の低下を招来するため、固定等
化器自体に大きな伝送歪補償特性を持たすことができ
ず、大きな伝送歪を持つ回線に対しては、不充分な伝送
歪補償しかできないという問題点を有する。However, in the method of using the conventional simple fixed equalizer, in a circuit with less transmission distortion, on the contrary, the transmission distortion is increased and the data quality is deteriorated. There is a problem that the transmission distortion compensation characteristic cannot be provided, and the transmission distortion compensation cannot be performed sufficiently for a line having a large transmission distortion.
本発明は上記に鑑みてなされたものであり、データ品質
の低下を招来せずに広範囲に及ぶ伝送歪の補償を行い得
るようにするため、固定された等化値を持つ複数個の等
化器によって等化処理を行う半固定等化器を用い、発呼
者側が予め記憶されていた等化器の設定パターンの情報
に基づき特定被呼者に対して生ずる伝送歪に最適な等化
器を選択して設定する半固定等化器を提供するものであ
る。The present invention has been made in view of the above, and a plurality of equalizations having a fixed equalization value are provided in order to be able to compensate for a wide range of transmission distortion without degrading data quality. A semi-fixed equalizer that performs equalization processing by the equalizer is used, and the equalizer that is most suitable for the transmission distortion generated for a specific called party based on the information of the equalizer setting pattern stored in advance on the caller side. The present invention provides a semi-fixed equalizer for selecting and setting.
以下、添付した図面に基づいて、本発明による半固定等
化器の一実施例を詳細に説明する。Hereinafter, an embodiment of a semi-fixed equalizer according to the present invention will be described in detail with reference to the accompanying drawings.
図は本発明による半固定等化器を用いた変復調装置（MO
DEM）の説明図である。The figure shows a modulator / demodulator (MO) using a semi-fixed equalizer according to the present invention.
It is an explanatory view of DEM).
送信データに対し変調処理を施す変調器１と、変調器１
に対して入力される送信データを制御入力と兼用し、送
信データとして入力されたダイヤル番号に従い、後述す
る網制御回路に制御信号を出力し、更に予めユーザーに
よってプログラムされ、ダイヤル番号と対応づけられて
いる半固定等化器の設定条件を後述する半固定等化器に
対して制御信号として出力する制御回路２（例えばマイ
クロコンピュータ）と、制御回路２から出力される制御
信号（ダイヤル番号情報）に従ってダイヤル発信し、回
線接続を行い、回線接続した後は、変調器１からの送信
キャリアを回線へ送出し、相手方から送信されてきた受
信キャリアを後述する半固定等化器を介して後述する復
調器へ入力する網制御回路３と、適当に選択された補償
特性を持つ４個の振幅等化器A,B,C,Dとから成る半固定
等化器６と、４個の遅延等化器E,F,G,H,とから成る半固
定等化器７と、振幅等化器A,B,C,Dを各々選択する選択
ゲート回路４と、遅延等化器E,F,G,Hを各々選択する選
択ゲート回路５と、受信キャリアに対して復調処理を施
す復調器とから構成されている。Modulator 1 for performing modulation processing on transmission data, and modulator 1
The transmission data to be input to is also used as the control input, and according to the dial number input as the transmission data, the control signal is output to the network control circuit described later, and further programmed by the user in advance to be associated with the dial number. Control circuit 2 (for example, a microcomputer) that outputs the setting conditions of the semi-fixed equalizer as a control signal to a semi-fixed equalizer described later, and a control signal (dial number information) output from the control circuit 2 According to the above, dial transmission is performed, the line is connected, and after the line is connected, the transmission carrier from the modulator 1 is sent to the line, and the reception carrier transmitted from the other party is described later via the semi-fixed equalizer described later. A network control circuit 3 for inputting to the demodulator, a semi-fixed equalizer 6 consisting of four amplitude equalizers A, B, C, D having appropriately selected compensation characteristics, and four delay equalizers. Semi-fixed equalizer 7 consisting of equalizers E, F, G, H, select gate circuit 4 for selecting amplitude equalizers A, B, C, D, and delay equalizer E, It is composed of a selection gate circuit 5 for selecting F, G, and H, and a demodulator for performing demodulation processing on a reception carrier.
また、前記振幅等化器A,B,C,D及び遅延等化器E,F,G,H
は、例えば、各々、以下の如き特性を補償する。Further, the amplitude equalizers A, B, C, D and the delay equalizers E, F, G, H
Compensates for the following characteristics, respectively.
振幅等化器Ａは0.5φ市内ケーブルの0.5kmの損失特性、
振幅等化器Ｂは0.5φ市内ケーブルの1kmの損失特性、振
幅等化器Ｃは0.5φ市内ケーブルの2kmの損失特性、振幅
等化器Ｄは0.5φ市内ケーブルの4kmの損失特性を各々補
償する。更に、遅延等化器Ｅは搬送1/2リンクの遅延特
性、遅延等化器Ｆは搬送１リンクの遅延特性、遅延等化
器Ｇは搬送２リンクの遅延特性、遅延等化器Ｈは搬送４
リンクの遅延特性を各々補償する。Amplitude equalizer A is a loss characteristic of 0.5φ city cable for 0.5km,
Amplitude equalizer B is a loss characteristic of 1km of 0.5φ city cable, amplitude equalizer C is a loss characteristic of 2km of 0.5φ city cable, and amplitude equalizer D is a loss characteristic of 4km of 0.5φ city cable. To compensate each. Further, the delay equalizer E is the delay characteristic of the carrier 1/2 link, the delay equalizer F is the delay characteristic of the carrier 1 link, the delay equalizer G is the delay characteristic of the carrier 2 link, and the delay equalizer H is the carrier. Four
The delay characteristics of the links are respectively compensated.
すなわち、振幅等化器Ａ〜Ｄは、0.5kmステップで最高
7.5kmまで補償でき、遅延等化器Ｅ〜Ｈは1/2リンクステ
ップで最高7.5リンクまで補償できる。That is, the amplitude equalizers A to D are the highest in 0.5km steps.
It can compensate up to 7.5km, and the delay equalizers E to H can compensate up to 7.5 links in 1/2 link step.
以上の構成においてその操作を説明する。The operation of the above configuration will be described.
発呼者側から被呼者を呼び出すために、送信データとし
てダイヤル番号が出力されると、送信データは制御回路
２に入力される。制御回路２は予めその記憶部（ROM
（図示せず））にダイヤル番号に対応した等化器設定の
組合せパターン（例えば表１の如き組合せパターン）が
格納されている。When a dial number is output as transmission data to call the called party from the calling side, the transmission data is input to the control circuit 2. The control circuit 2 has its storage unit (ROM
(Not shown)) stores a combination pattern of equalizer settings (for example, a combination pattern as shown in Table 1) corresponding to a dial number.
制御回路２は入力されたダイヤル番号情報に基づき、所
定の演算を行い、制御信号を網制御装置３、及び選択ゲ
ート回路４、選択ゲート回路５へ出力し、網制御装置３
に対し、ダイヤル発信させるとともに、半固定等化器6,
7における振幅等化器Ａ〜Ｄ及び遅延等化器Ｅ〜Ｈの選
択等化設定を行い、入力されたダイヤル番号に対応する
被呼者側からの受信データを復調処理するのに最適な等
化器の組合せを実現する。 The control circuit 2 performs a predetermined calculation based on the inputted dial number information and outputs a control signal to the network control device 3, the selection gate circuit 4 and the selection gate circuit 5, and the network control device 3
In addition to dialing, the semi-fixed equalizer 6,
Optimal for demodulating the received data from the called party corresponding to the input dial number by performing selective equalization setting of the amplitude equalizers A to D and the delay equalizers E to H in 7. Realize a combination of chemicals.
例えば、表１を参照して説明すると、丙会社に対して電
話を行おうとする場合、送信データとして「06−XXX−X
XXX」が制御回路２に入力されると、制御回路２は記憶
されている等化器の組合せパターン（振幅特性に関して
はＢを設定し、A,C,Dはパス、また遅延特性に関しては
F,H,を設定し、E,Gはパス）に基づいて、各々の選択ゲ
ート回路4,5を制御する。その結果、半固定等化器6,7内
は、B,F,Hのみが等化設定される。For example, referring to Table 1, when trying to make a call to a company, the transmission data is "06-XXX-X".
When "XXX" is input to the control circuit 2, the control circuit 2 sets the stored equalizer combination pattern (B is set for the amplitude characteristic, A, C, D are paths, and the delay characteristic is set.
F, H, are set, and E, G control the respective selection gate circuits 4 and 5 based on (Pass). As a result, in the semi-fixed equalizers 6 and 7, only B, F, and H are equalized and set.
従って、丙会社において、回線が持つ特性伝送歪に対し
て最適な補償が可能となる。Therefore, the company will be able to optimally compensate for the characteristic transmission distortion of the line.
但し、同じ相手方に対して送信データを出力しても交換
回線の場合、必ずしも同じ回線構成とはならないが、最
も接続される確立の高い回線構成に合わせて等化器の組
合せパターンを決定すれば良い。蓋し、等化残は変復調
器で補償することが可能である。However, even if the transmission data is output to the same party, the same line configuration will not always be obtained in the case of a switched line, but if the equalizer combination pattern is determined according to the line configuration with the highest probability of being connected. good. The equalization residual can be compensated by a modulator / demodulator.
以上、説明した通り本発明による半固定等化器にあって
は、固定された等化値を持つ複数個の等化器によって等
化処理を行う半固定等化器を用い、発呼者側が予め記憶
されていた等化器の設定パターンの情報に基づき、特定
被呼者に対して生ずる伝送歪に最適な等化器を選択して
設定するため、データ品質の低下を招来せずに広範囲に
及ぶ伝送歪の補償を行い得る。As described above, in the semi-fixed equalizer according to the present invention, a semi-fixed equalizer that performs equalization processing by a plurality of equalizers having fixed equalization values is used, Based on pre-stored equalizer setting pattern information, the optimum equalizer is selected and set for the transmission distortion that occurs for a specific called party, so a wide range can be achieved without degrading data quality. It is possible to compensate for transmission distortion that extends to a maximum.
図は本発明による半固定等化器を用いた変復調装置の説
明図である。 符号の説明 ２……制御回路、３……網制御回路 4,5……選択ゲート回路、6,7……半固定等化器The figure is an explanatory diagram of a modulator / demodulator using a semi-fixed equalizer according to the present invention. Explanation of symbols 2 ... Control circuit, 3 ... Network control circuit 4,5 ... Select gate circuit, 6,7 ... Semi-fixed equalizer
Claims (2)
を補償する等化器であって、 所定距離ごとの伝送損失特性を補正する複数の振幅等化
器と、 所定搬送リンク数ごとの伝送遅延特性を補償するための
複数の遅延等化器と、 前記複数の振幅等化器を選択する第１の選択ゲート回路
と、 前記複数の遅延等化器を選択する第２の選択ゲート回路
と、 種々の等化値を得るための前記複数の振幅等化器及び遅
延等化器の組合せを予め設定して記憶した記憶部を有
し、ダイアル番号に基づく前記記憶部に設定されたデー
タに従って前記第１及び第２の選択ゲート回路を制御す
る制御回路とを備え、 前記複数の振幅等化器及び遅延等化器を直列に接続する
と共に、該直列に接続された振幅等化器及び遅延等化器
の夫々の端から送信データ及び受信データを入力するこ
とによって、発呼者側で入力したダイアル番号に基づき
等化器の設定パターンを変更し、被呼者との関係で生ず
る伝送歪みの是正に最適な等化値を自動設定することを
特徴とする半固定等化器。1. An equalizer for compensating waveform deterioration due to transmission distortion occurring in a telephone line, comprising: a plurality of amplitude equalizers for correcting transmission loss characteristics for each predetermined distance; and transmission delay for each predetermined number of carrier links. A plurality of delay equalizers for compensating for characteristics, a first select gate circuit that selects the plurality of amplitude equalizers, and a second select gate circuit that selects the plurality of delay equalizers, It has a storage unit that presets and stores a combination of the plurality of amplitude equalizers and delay equalizers for obtaining various equalization values, and according to the data set in the storage unit based on a dial number. A control circuit for controlling the first and second selection gate circuits, wherein the plurality of amplitude equalizers and delay equalizers are connected in series, and the amplitude equalizers and delays connected in series are provided. Transmit data and receive data from each end of the digitizer. By inputting the data, the setting pattern of the equalizer is changed based on the dial number input on the calling side, and the optimum equalization value is automatically set to correct the transmission distortion caused by the relationship with the called party. A semi-fixed equalizer characterized in that
kmごとの伝送損出特性を補正するものであり、前記遅延
等化器は、搬送2n（ｎは任意の整数）リンクごとの遅延
特性を補償するものである、特許請求の範囲第１項の半
固定等化器。2. The amplitude equalizer is 2 m (m is an arbitrary integer)
The transmission loss characteristic for each km is corrected, and the delay equalizer compensates the delay characteristic for each carrier 2 n (n is an arbitrary integer) link. Semi-fixed equalizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169345A JPH07120971B2 (en) | 1986-07-18 | 1986-07-18 | Semi-fixed equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169345A JPH07120971B2 (en) | 1986-07-18 | 1986-07-18 | Semi-fixed equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6326126A JPS6326126A (en) | 1988-02-03 |
| JPH07120971B2 true JPH07120971B2 (en) | 1995-12-20 |
Family
ID=15884840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169345A Expired - Lifetime JPH07120971B2 (en) | 1986-07-18 | 1986-07-18 | Semi-fixed equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120971B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2212715B1 (en) * | 1972-12-29 | 1978-03-10 | Ibm France |
-
1986
- 1986-07-18 JP JP61169345A patent/JPH07120971B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6326126A (en) | 1988-02-03 |
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