JPH0712066B2 - Highly reliable sealing structure and manufacturing method thereof - Google Patents

Highly reliable sealing structure and manufacturing method thereof

Info

Publication number
JPH0712066B2
JPH0712066B2 JP62210338A JP21033887A JPH0712066B2 JP H0712066 B2 JPH0712066 B2 JP H0712066B2 JP 62210338 A JP62210338 A JP 62210338A JP 21033887 A JP21033887 A JP 21033887A JP H0712066 B2 JPH0712066 B2 JP H0712066B2
Authority
JP
Japan
Prior art keywords
solder
sealing
highly reliable
sealing portion
sealing structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62210338A
Other languages
Japanese (ja)
Other versions
JPS6454748A (en
Inventor
忠雄 九嶋
太佐男 曽我
正広 合田
守 沢畠
貢 白井
伸一 和井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62210338A priority Critical patent/JPH0712066B2/en
Publication of JPS6454748A publication Critical patent/JPS6454748A/en
Publication of JPH0712066B2 publication Critical patent/JPH0712066B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616Cavity shape

Landscapes

  • Laser Beam Processing (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、封止構造を有する超大型計算機に係り、特に
はんだ封止部の欠陥を排除しかつ高信頼性のち密はんだ
層をもつ封止構造体及びその製造方法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a super-large-sized computer having a sealing structure, and in particular, it eliminates defects in a solder sealing portion and has a highly reliable sealing with a dense solder layer. TECHNICAL FIELD The present invention relates to a stop structure and a manufacturing method thereof.

〔従来の技術〕[Conventional technology]

従来の装置は、米国特許第4081825号明細書に記載のよ
うにセラミツクス多層板に冷水通路をもつハウジングの
封止構造方式で、封止部は金属ガスケツトによる機械的
な圧着方式によるものである。
The conventional apparatus is a sealing structure method of a housing having a cold water passage in a ceramic multilayer plate as described in U.S. Pat. No. 4,081,825, and a sealing portion is a mechanical crimping method using a metal gasket.

この方式での問題点は、機械的な圧着封止であるため長
期間の使用において、セラミツクス多層板側の疲労破壊
の発生や金属ガスケツトのゆるみ等から封止内外部のリ
ーク発生により、封止内部の半導体素子特性劣化への影
響が大きいことや、場合によつては稼動短期間ごとの封
止部補修点検や部品交換が多いなど稼動上の問題が多
く、長期的な高信頼性が得られない構造であつた。
The problem with this method is that it is mechanically pressure-bonded and sealed, and during long-term use, the ceramic multi-layer board will experience fatigue damage and the metal gasket will loosen, resulting in leaks inside and outside the seal. There are many operational problems, such as a large impact on the deterioration of internal semiconductor element characteristics and, in some cases, frequent repairs and inspections of sealing parts and replacement of parts every short operating period, resulting in long-term high reliability. It was a structure that can not be.

このため、構造的に種々の改良が要求され、ハウジング
のセラミツクス多層板への封止方法としてはSn-Pb系共
晶はんだによるはんだ封止構造指向にある(日経エレク
トロニクス、日経マグロウヒル社、3-26:155、1984)。
しかし、セラミツクス多層板上に多数個搭載された半導
体素子のいくつかが、特性劣化あるいは回路変更のため
に脱接続が必要とされた場合、封止部も当然ながら脱接
続のため加熱溶融と再封止が繰返される。
For this reason, various structural improvements are required, and as a method for sealing the housing to the ceramic multilayer board, there is a solder-sealing structure orientation using Sn-Pb-based eutectic solder (Nikkei Electronics, Nikkei McGraw-Hill, 3- 26: 155, 1984).
However, if some of the semiconductor elements mounted on the ceramic multilayer board require disconnection due to characteristic deterioration or circuit change, the sealing part will of course also be heated and melted and re-connected due to disconnection. The sealing is repeated.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術は、機械的な圧着封止構造であり、圧着力
に対するセラミツクス多層板の耐久性の点について配慮
されておらず、セラミツクス多層板の疲労破壊等で封止
内部の半導体素子特性劣化の問題があつた。また、はん
だ封止構造においては、封止内部の半導体素子の脱接続
に絡み、はんだ封止部の繰返し封止による欠陥排除の点
について配慮されておらず、はんだ封止部の信頼性低下
や封止内外部のリーク発生による半導体素子特性の劣化
などの問題があつた。
The above-mentioned prior art is a mechanical pressure-bonding sealing structure, and is not considered in terms of durability of the ceramic multilayer plate against pressure bonding force, and deterioration of semiconductor element characteristics inside the sealing due to fatigue breakdown of the ceramic multilayer plate, etc. There was a problem. In addition, in the solder sealing structure, no consideration is given to the defect elimination due to the repeated sealing of the solder sealing portion, which is involved in the disconnection of the semiconductor element inside the sealing, and the reliability of the solder sealing portion may be reduced. There was a problem such as deterioration of semiconductor element characteristics due to leakage inside and outside the encapsulation.

本発明の目的は、半導体装置のはんだ封止部の欠陥を排
除し、高信頼性のはんだ封止構造体及びその製造方法を
提供することにある。
An object of the present invention is to eliminate defects in the solder sealing portion of a semiconductor device and provide a highly reliable solder sealing structure and a method for manufacturing the same.

〔問題点を解決するための手段〕[Means for solving problems]

本発明を概説すれば、本発明の第1の発明は高信頼性封
止構造体に関する発明であつて、多層配線基板上に搭載
した複数個の半導体素子の背面から放熱冷却する構造の
ハウジング封止部が該多層配線基板にはんだ封止された
封止構造体において、半導体素子を搭載しない外部領域
に面する封止部のはんだ部分が、内部よりもち密なはん
だ凝固組織であることを特徴とする。
Briefly explaining the present invention, the first invention of the present invention relates to a highly reliable sealing structure, which is a housing seal having a structure in which a plurality of semiconductor elements mounted on a multilayer wiring board are radiated and cooled from the back surface. In the sealing structure in which the stopper is solder-sealed to the multilayer wiring board, the solder portion of the sealing portion facing the external region where the semiconductor element is not mounted has a solder coagulation structure that is denser than the inside. And

そして、本発明の第2の発明は、高信頼性封止構造体の
製造方法に関する発明であつて、第1の発明の高信頼性
封止構造体を製造する方法において、半導体素子を搭載
しない外部領域に面する封止部のはんだ部分を、再溶融
し、次いで急速に凝固させて、内部よりもち密なはんだ
凝固組織を形成させることを特徴とする。
A second invention of the present invention is an invention relating to a method of manufacturing a highly reliable sealing structure, wherein no semiconductor element is mounted in the method of manufacturing the highly reliable sealing structure of the first invention. It is characterized in that the solder portion of the sealing portion facing the outer region is remelted and then rapidly solidified to form a solder solidification structure which is denser than the inside.

前記目的は、半導体装置のはんだ封止したはんだ層部
を、封止内部の半導体素子接合構造部にダメージを与え
ないように、また封止はんだ層の全域を溶かさず、すな
わち封止内外部のリーク発生がないように、該封止はん
だ層の封止外部側から、例えば、放射性エネルギービー
ムであるCW-YAGレーザ光(出力:100W、照射ビーム径:
φ3.0mm)を照射させて加熱溶融し、照射ビームを走査
(速度:10mm/sec)させ瞬時に凝固させることにより達
成される。
The purpose is to prevent the solder-sealed solder layer portion of the semiconductor device from damaging the semiconductor element bonding structure inside the encapsulation, and not to melt the entire area of the encapsulating solder layer, that is, inside and outside the encapsulation. From the sealing outer side of the sealing solder layer, for example, CW-YAG laser light which is a radiant energy beam (output: 100 W, irradiation beam diameter:
It is achieved by irradiating (φ3.0 mm) to heat and melt, scanning the irradiation beam (speed: 10 mm / sec), and instantaneously solidifying.

半導体装置のはんだ封止構造体において、半導体素子の
脱接続に絡んで繰返し封止され発生したボイドやマイク
ロブローホール等の欠陥を有する封止はんだ層は、封止
外部側から照射される放射性エネルギービームによつ
て、部分的に加熱され、外側のはんだフイレツト部から
内側に再溶融し、該ビームを走査させることにより順次
急冷凝固する。この場合、前記欠陥は、部分的な加熱の
再溶融時に除去される。
In a solder sealing structure of a semiconductor device, a sealing solder layer having defects such as voids and micro blow holes that are repeatedly sealed due to disconnection of a semiconductor element is radiant energy emitted from the outside of the sealing. The beam partially heats, re-melts inward from the outer solder fillet portion, and the beam is scanned to rapidly solidify. In this case, the defects are removed during remelting with partial heating.

放射性エネルギービーム照射による加熱は、封止はんだ
層部のフイレツト表面からであり、部分的な加熱による
再溶融部分は、該ビームの移動で加熱源を失ない、また
セラミツクス多層板や封止ハウジングの熱容量の関係も
あり急冷凝固される。急冷凝固したはんだ層部分は組織
的にち密である。したがつて、はんだ封止部は、封止内
部側よりも封止外部側のはんだ組織がち密である二重は
んだ層となる。
The heating by irradiation of the radiant energy beam is from the fired surface of the sealing solder layer portion, and the remelted portion by partial heating does not lose the heating source due to the movement of the beam, and the ceramic multilayer plate and the sealing housing are Due to heat capacity, it is rapidly solidified. The rapidly solidified solder layer portion is structurally dense. Therefore, the solder sealing portion is a double solder layer having a denser solder structure on the sealing outer side than on the sealing inner side.

一般に、はんだ組織が微細であることは、はんだ付継手
部の耐熱疲労寿命が高信頼化にあることや耐食性に優れ
ているといわれている。これによつて、半導体装置のは
んだ封止部は、繰返し封止時の欠陥排除が行われると同
時にはんだ組織のち密化が得られ、高信頼性封止構造体
が得られる。
In general, it is said that the fine solder structure is highly reliable in the thermal fatigue life of the soldered joint and excellent in the corrosion resistance. As a result, in the solder sealing portion of the semiconductor device, defects are eliminated during repeated sealing, and at the same time, the solder structure is densified and a highly reliable sealing structure is obtained.

大型コンピユータのセラミツクス多層基板と冷却ハウジ
ングのはんだ封止部は、最も重要部分であるLSI素子実
装部分を保護しかつ素子上部からの熱冷却構造として必
須構造である。そのため、LSI素子特性を高信頼化に保
つためにもはんだ封止部の接続信頼性の向上が必要なこ
ととなる。
The ceramic multi-layered board of the large-sized computer and the solder sealing part of the cooling housing are essential structures for protecting the most important part of the LSI device mounting part and for heat cooling from the top of the device. Therefore, it is necessary to improve the connection reliability of the solder-sealed portion in order to keep the LSI device characteristics highly reliable.

はんだ封止部の耐熱疲労特性を向上させるためには、は
んだ封止部に熱疲労破壊に起因するボイド等の欠陥がな
いこと、熱疲労に耐えれる十分なはんだ量の確保、はん
だ層そのものを長寿命化させることにつきる。
In order to improve the thermal fatigue resistance of the solder encapsulation part, the solder encapsulation part must be free from defects such as voids due to thermal fatigue failure, ensure a sufficient amount of solder that can withstand thermal fatigue, and ensure that the solder layer itself is It is about extending the service life.

本発明においては、はんだ部分の外部領域の組織をち密
化した。はんだ部分は、ハウジングと水平面で接してい
てもよく、あるいは傾斜をつけて外部領域を広くしても
よい。
In the present invention, the structure of the outer region of the solder portion is densified. The solder portion may be in horizontal contact with the housing or may be beveled to widen the outer area.

このはんだの組成の例には、Sn系、Pb系からなる二元
系、及び複数元素からなる多元系のはんだ合金がある。
Examples of the composition of this solder include a binary alloy composed of Sn-based and Pb-based, and a multi-component solder alloy composed of a plurality of elements.

〔実施例〕〔Example〕

以下、本発明を実施例により更に具体的に説明するが、
本発明はこれら実施例に限定されない。
Hereinafter, the present invention will be described in more detail with reference to Examples.
The present invention is not limited to these examples.

実施例1 本発明の1実施例を、第1図〜第5図により説明する。Embodiment 1 One embodiment of the present invention will be described with reference to FIGS.

第1-1図は、本発明における半導体装置の高信頼性封止
構造体の1例の断面図であり、第1-2図は、そのはんだ
封止部の拡大断面図である。
FIG. 1-1 is a cross-sectional view of an example of a highly reliable sealing structure for a semiconductor device according to the present invention, and FIG. 1-2 is an enlarged cross-sectional view of a solder sealing portion thereof.

第1-1図及び第1-2図において、符号1は多層基板、1aは
厚膜メタライズ、2は入出力ピン、3は半導体素子、4
はCCBはんだ、5はチツプキヤリア、6は共晶はんだ、
7は上くし歯、8は下くし歯、9はハウジング、10は低
温はんだ、11は微細組織はんだを意味する。
In FIGS. 1-1 and 1-2, reference numeral 1 is a multilayer substrate, 1a is a thick film metallization, 2 is an input / output pin, 3 is a semiconductor element, and 4 is a semiconductor element.
Is CCB solder, 5 is chip carrier, 6 is eutectic solder,
7 is an upper comb tooth, 8 is a lower comb tooth, 9 is a housing, 10 is a low temperature solder, and 11 is a microstructure solder.

第2図及び第3図は放射エネルギービームの照射方法の
説明であり、符号9〜11は第1図と同義、9aは薄膜メタ
ライズ、12はレーザ光照射矢図、12aは照射スポツト、1
2b及び12cはスポツト走査方向矢図を意味する。
2 and 3 are explanations of the irradiation method of the radiant energy beam. Reference numerals 9 to 11 are synonymous with those in FIG. 1, 9a is a thin film metallized, 12 is a laser beam irradiation arrow diagram, 12a is an irradiation spot, 1
2b and 12c mean spot scanning direction arrows.

第4図は従来方法によるはんだ封止部縦断面図であり、
符号1、1a、9、9a及び10は前記のとおりであつて、13
はボイド欠陥を意味する。
FIG. 4 is a vertical cross-sectional view of the solder-sealed portion according to the conventional method,
Reference numerals 1, 1a, 9, 9a and 10 are as described above, and 13
Means a void defect.

第5図は耐熱疲労特性の説明図であり、横軸はNf(寿
命)、縦軸はひずみ量を意味する。
FIG. 5 is an explanatory diagram of thermal fatigue resistance, where the horizontal axis represents Nf (lifetime) and the vertical axis represents strain amount.

第1図に示したように、裏面側に入出力ピン2を具備し
たセラミツクス多層板1上に、発熱を放散伝達する上く
し歯7を背面につけ、脱接続を有効にするチツプキヤリ
ア5とCCBはんだ4で接続された半導体素子3を、共晶
はんだ6で搭載し、半導体素子等の発熱を冷却しかつ該
素子特性の保持及び信頼性向上のために、素子搭載全域
部をハウジング9(例えばMoCuあるいはAlN)で該多層
基板1にはんだ封止する。この場合、チツプキヤリア5
と半導体素子3の接続は、Pb-5%SnのCCBはんだ4で、
該基板上への搭載はPb-60%Sn(融点:液相190℃、固相
183℃)の共晶はんだ6である。したがつて、ハウジン
グの該基板封止はんだ材としては、該搭載部を再溶融す
るようなダメージを与えないため、共晶はんだの融点
(固相183℃)よりも低いはんだで封止する必要があ
る。そこで本発明では低温はんだ、例えばPb45%、Bi18
%、残Snからなるはんだ(融点:液相160℃、固相136
℃)で封止した。
As shown in FIG. 1, a chip carrier 5 and CCB solder are provided on the ceramic multilayer board 1 having the input / output pins 2 on the back side, and the upper comb teeth 7 for radiating and transmitting heat are attached to the back surface to enable the disconnection. The semiconductor element 3 connected by 4 is mounted with the eutectic solder 6, and in order to cool the heat generation of the semiconductor element and the like and to maintain the characteristics of the element and improve reliability, the entire element mounting portion is covered with the housing 9 (for example, MoCu Alternatively, AlN) is used to solder-seal the multilayer substrate 1. In this case, the chip carrier 5
The semiconductor element 3 is connected to the CCB solder 4 of Pb-5% Sn,
Mounting on the substrate is Pb-60% Sn (melting point: liquid phase 190 ° C, solid phase
183 ° C) eutectic solder 6. Therefore, the board sealing solder material of the housing must be sealed with a solder lower than the melting point (solid phase 183 ° C) of the eutectic solder so as not to damage the mounting part by remelting. There is. Therefore, in the present invention, low temperature solder, such as Pb45%, Bi18
%, Solder consisting of residual Sn (melting point: liquid phase 160 ° C, solid phase 136
(° C).

封止する場合、Ni-Auめつきメタライズをしたハウジン
グの封止部にあらかじめロジン系フラツクスを用いてむ
かえはんだ層を形成させ、一方のセラミツクス多層板の
封止部(例えばW-Ni厚膜メタライズ1a)にも接続に必要
な量だけのむかえはんだ層を形成させた。
When encapsulating, a solder layer is formed in advance using a rosin-based flux on the encapsulation part of the Ni-Au plated metallized housing, and the encapsulation part of one ceramic multilayer plate (for example, W-Ni thick film metallization). In 1a), only the amount of soldering layer necessary for connection was formed.

フラツクスの除去洗浄を十分にした後に、該セラミツク
ス多層板上にハウジングを位置合せをし、雰囲気炉中
(例えばHe又はN2ガス雰囲気)でそれぞれのはんだを加
熱溶融(最高温度180℃)させて接合し封止させた。
After thoroughly removing and cleaning the flux, the housing is aligned on the ceramic multilayer board, and each solder is heated and melted (maximum temperature 180 ° C) in an atmosphere furnace (for example, He or N 2 gas atmosphere). Joined and sealed.

一般に、接合面積の多い部分のはんだ付部においては、
第4図のはんだ封止部断面図に示すように、はんだ10と
メタライズ1a、9aとのぬれ反応ガスやメタライズそのも
のから加熱による発生ガス等によつて、ガスボイドやマ
イクロブローホール等のボイド欠陥13が生じ、はんだ層
内に形成されやすい。
Generally, in the soldered part where the joint area is large,
As shown in the cross-sectional view of the solder-sealed portion in FIG. 4, a void defect 13 such as a gas void or a micro blow hole is caused by a wetting reaction gas between the solder 10 and the metallization 1a, 9a or a gas generated by heating from the metallization itself. Occurs and is easily formed in the solder layer.

第2図及び第3図は、はんだ封止したはんだ層部のボイ
ド欠陥を排除し、ち密なはんだ組織層を形成させる説明
図である。
FIG. 2 and FIG. 3 are explanatory views for eliminating void defects in the solder layer portion sealed by solder and forming a dense solder texture layer.

第2図で、セラミツクス多層板1上にハウジング9を封
止した低温はんだ層10の封止外部側から放射性エネルギ
ービーム(例えば、CW-YAGレーザ光、出力:約100W、照
射ビームスポツト径:約φ3.0mm)を照射すると、図示
したように、封止はんだ断面層の外側から内側にかけ
て、はんだ層の部分的な再溶融が開始される。この場
合、はんだ層の全域を再溶融させてしまうと、封止内部
の雰囲気が外部とリークしてしまい半導体素子特性の保
持上からも好ましくない。したがつて、再溶融・凝固さ
せるはんだ層領域は、はんだ封止幅の1/3〜1/2がよい。
なお、加熱溶融幅は、該ビームの照射時間、出力等によ
つてコントロールできる。また、凝固は該ビームの照射
を停止するかあるいは照射場所を移動させると加熱溶融
の熱源が供給されず凝固形態をとる。該エネルギービー
ムによる部分的な加熱溶融は、該ビームが高出力による
高熱源であるため瞬時に開始できる特徴がある。逆に、
該エネルギービームの照射停止で部分的な溶融部は、未
溶融部からの熱吸収(熱伝達による)により瞬時すなわ
ち急冷凝固される。
In FIG. 2, a radiant energy beam (for example, CW-YAG laser light, output: about 100 W, irradiation beam spot diameter: about) from the outside of the low temperature solder layer 10 in which the housing 9 is sealed on the ceramic multilayer plate 1 (φ3.0 mm), the partial remelting of the solder layer is started from the outer side to the inner side of the sealing solder cross-sectional layer as shown in the figure. In this case, if the entire area of the solder layer is remelted, the atmosphere inside the sealing leaks to the outside, which is not preferable from the viewpoint of maintaining the semiconductor element characteristics. Therefore, the solder layer area to be remelted and solidified is preferably 1/3 to 1/2 of the solder sealing width.
The heating and melting width can be controlled by the irradiation time of the beam, the output, and the like. Further, the solidification takes a solidification form when the irradiation of the beam is stopped or the irradiation position is moved, because the heat source for heating and melting is not supplied. Partial heating and melting by the energy beam is characterized in that it can be instantly started because the beam is a high heat source with high output. vice versa,
When the irradiation of the energy beam is stopped, the partial melted portion is instantaneously, that is, rapidly cooled and solidified by heat absorption (due to heat transfer) from the unmelted portion.

このため、再溶融して凝固させたはんだ層は、未溶融部
の結晶寸法(約10〜15μm/個)よりもち密なはんだ層
(結晶寸法:約1〜3μm/個)となる。したがつて、第
3図のようにハウジングとセラミツクス多層板のはんだ
封止部が比較的長寸法にある場合は、照射ビームをはん
だ封止部に沿つて走査(前期条件の場合、走査速度5〜
15mm/sec)させるか又は封止構造物を移動させること
で、第1-2図の断面構造が得られる。
Therefore, the remelted and solidified solder layer becomes a denser solder layer (crystal size: about 1 to 3 μm / piece) than the crystal size (about 10 to 15 μm / piece) of the unmelted portion. Therefore, as shown in FIG. 3, when the solder seal portion of the housing and the ceramic multilayer board has a relatively long dimension, the irradiation beam is scanned along the solder seal portion (in the case of the previous term, the scanning speed is 5 ~
15 mm / sec) or by moving the sealing structure, the cross-sectional structure of FIG. 1-2 can be obtained.

また、第3図のような封止構造体においては、該ビーム
照射スポツトを矢図12b、12cのように同時に走査するこ
とで封止構造物への熱ストレスは解消でき高能率であ
る。
Further, in the sealing structure as shown in FIG. 3, by simultaneously scanning the beam irradiation spots as shown in FIGS. 12b and 12c, the thermal stress to the sealing structure can be eliminated and the efficiency is high.

第5図は、本発明で得られた高信頼性封止構体(第1-1
図)の耐熱疲労特性の説明図である。
FIG. 5 shows the highly reliable sealing structure obtained by the present invention (see 1-1
(Fig.) Is an explanatory view of the thermal fatigue resistance property.

はんだ封止部に、放射性エネルギービームを照射させち
密なはんだ組織層を形成させた場合(第5図A)と形成
させない場合(第5図B)との耐熱疲労特性は、該ビー
ム照射有りの方が無しの場合に比べて約10倍以上の信頼
性向上が得られた。更に、ち密なはんだ層部を形成した
構造は、形成なしのもに比べて数段の耐食性向上があつ
た。
The heat-resisting fatigue characteristics of the solder encapsulation part when the radioactive energy beam is irradiated and the dense solder texture layer is formed (FIG. 5A) and when it is not formed (FIG. 5B) are The reliability was improved about 10 times more than the case without one. Furthermore, the structure in which the dense solder layer portion is formed has several stages of improvement in corrosion resistance as compared with the structure in which it is not formed.

実施例2 本発明の構造体の封止部の1例を第6図に示す。すなわ
ち第6図は本発明の他の1例におけるはんだ封止部の拡
大断面図である。第6図において符号1、1a、9、9a、
10及び11は前記のとおりであり、9bはハウジング封止部
を意味する。第6図に示すようにまず、冷却ハウジング
の封止部9bに傾斜加工部を加えてはんだ封止する。ハウ
ジング部の構造が傾斜であるため、はんだ封止時の発生
ガスは封止外部の方に逃げるため、はんだ封止層内の欠
陥は少なくなる。また、この構造により、封止部のセラ
ミツクス多層基板との間隙が封止外部側に大きくなり、
したがつて封止はんだ量が十分に確保できる。
Example 2 An example of the sealing portion of the structure of the present invention is shown in FIG. That is, FIG. 6 is an enlarged sectional view of a solder sealing portion in another example of the present invention. In FIG. 6, reference numerals 1, 1a, 9, 9a,
10 and 11 are as described above, and 9b means a housing sealing portion. As shown in FIG. 6, first, an inclined portion is added to the sealing portion 9b of the cooling housing to perform solder sealing. Since the structure of the housing is inclined, the generated gas at the time of solder sealing escapes to the outside of the sealing, so that the defects in the solder sealing layer are reduced. Also, with this structure, the gap between the sealing part and the ceramic multi-layer substrate is increased to the outside of the sealing,
Therefore, a sufficient amount of sealing solder can be secured.

更に、封止外部側のはんだ面が大きいことは、封止はん
だ層を高信頼性に導くための放射性エネルギービーム照
射も容易で高熱量供給が可能となり、したがつて、瞬時
の再溶融・凝固が封止内部近傍まで行え、ち密なはんだ
層が多く形成でき、より一層の高信頼性向上を図ること
ができる。
In addition, the large solder surface on the outside of the encapsulation makes it easy to irradiate a radiant energy beam to guide the encapsulation solder layer with high reliability and to supply a large amount of heat. Therefore, instantaneous remelting / solidification is possible. Can be performed up to the vicinity of the inside of the encapsulation, a large number of dense solder layers can be formed, and the reliability can be further improved.

〔発明の効果〕〔The invention's effect〕

本発明によれば、はんだ封止部の欠陥の排除が容易にで
き、かつち密なはんだ層を形成することができる。した
がつて、耐熱疲労特性と耐食性に優れた高信頼性封止構
造の半導体装置を製造できる効果がある。
According to the present invention, defects in the solder sealing portion can be easily eliminated, and a dense solder layer can be formed. Therefore, there is an effect that it is possible to manufacture a semiconductor device having a highly reliable sealed structure which is excellent in heat fatigue resistance and corrosion resistance.

【図面の簡単な説明】[Brief description of drawings]

第1-1図は本発明の1実施例のはんだ封止構造体の縦断
面図、第1-2図はその部分拡大断面図、第2図及び第3
図は放射性エネルギービームの照射方法の説明図、第4
図は従来方法によるはんだ封止部縦断面図、第5図は耐
熱疲労特性の説明図、第6図は本発明の他の1例におけ
るはんだ封止部の拡大断面図である。 1:多層基板、1a:厚膜メタライズ、2:入出力ピン、3:半
導体、4:CCBはんだ、5:チツプキヤリア、6:共晶はん
だ、7:上くし歯、8:下くし歯、9:ハウジング、9a:薄膜
メタライズ、9b:ハウジング封止部、10:低温はんだ、1
1:微細組織はんだ、12:レーザ光照射矢図、12a:照射ス
ポツト、12a及び12b:照射スポツト走査方向矢図、13:ボ
イド欠陥
FIG. 1-1 is a vertical sectional view of a solder sealing structure according to an embodiment of the present invention, and FIG. 1-2 is a partially enlarged sectional view thereof, FIG. 2 and FIG.
The figure is an illustration of irradiation method of radiant energy beam, 4th
FIG. 5 is a vertical sectional view of a solder sealing portion by a conventional method, FIG. 5 is an explanatory view of thermal fatigue resistance characteristics, and FIG. 6 is an enlarged sectional view of a solder sealing portion in another example of the present invention. 1: Multilayer substrate, 1a: Thick film metallization, 2: Input / output pin, 3: Semiconductor, 4: CCB solder, 5: Chip carrier, 6: Eutectic solder, 7: Upper comb tooth, 8: Lower comb tooth, 9: Housing, 9a: Thin film metallization, 9b: Housing sealing part, 10: Low temperature solder, 1
1: Microstructure solder, 12: Laser light irradiation arrow diagram, 12a: Irradiation spot, 12a and 12b: Irradiation spot scanning direction arrow diagram, 13: Void defect

───────────────────────────────────────────────────── フロントページの続き (72)発明者 沢畠 守 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 白井 貢 神奈川県秦野市堀山下1番地 株式会社日 立製作所神奈川工場内 (72)発明者 和井 伸一 神奈川県秦野市堀山下1番地 株式会社日 立製作所神奈川工場内 (56)参考文献 特開 昭62−264697(JP,A) 特開 昭61−258456(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mamoru Sawahata 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitori Works, Hitachi Research Laboratory (72) Inventor Mitsuru Shirai 1 Horiyamashita, Hadano City, Kanagawa Prefecture Nitate Works Co., Ltd. Kanagawa Plant (72) Inventor Shinichi Wai 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hiritsu Manufacturing Co., Ltd. Kanagawa Plant (56) Reference JP 62-264697 (JP, A) JP 61-258456 (JP JP, A)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】多層配線基板上に搭載した複数個の半導体
素子の背面から放熱冷却する構造のハウジング封止部が
該多層配線基板にはんだ封止された封止構造体におい
て、半導体素子を搭載しない外部領域に面する封止部の
はんだ部分が、内部よりもち密なはんだ凝固組織である
ことを特徴とする高信頼性封止構造体。
1. A semiconductor device is mounted in a sealing structure in which a housing sealing portion for radiating and cooling from the back surface of a plurality of semiconductor elements mounted on a multilayer wiring board is solder-sealed to the multilayer wiring board. The highly reliable sealing structure, wherein the solder portion of the sealing portion facing the external area is a solder solidification structure that is denser than the inside.
【請求項2】該封止部のはんだの組成が、Sn系、Pb系か
らなる二元系、又は複数元素からなる多元系のはんだ合
金である特許請求の範囲第1項記載の高信頼性封止構造
体。
2. The high reliability according to claim 1, wherein the solder composition of the sealing portion is a binary alloy composed of Sn-based or Pb-based or a multi-component solder alloy composed of a plurality of elements. Encapsulation structure.
【請求項3】多層配線基板上に搭載した複数個の半導体
素子の背面から放熱冷却する構造のハウジング封止部が
該多層配線基板にはんだ封止された封止構造体を製造す
る方法において、半導体素子を搭載しない外部領域に面
する封止部のはんだ部分を、再溶融し、次いで急速に凝
固させて、内部よりもち密なはんだ凝固組織を形成させ
ることを特徴とする高信頼性封止構造体の製造方法。
3. A method of manufacturing a sealing structure in which a housing sealing portion having a structure for radiating and cooling from the back surface of a plurality of semiconductor elements mounted on a multilayer wiring board is solder-sealed to the multilayer wiring board, A highly reliable encapsulation characterized by remelting the solder portion of the sealing portion facing the outer area where no semiconductor element is mounted and then rapidly solidifying it to form a solder solidification structure that is denser than the inside. Structure manufacturing method.
【請求項4】該はんだ凝固組織を形成させる熱源とし
て、放射性エネルギービームを用いる特許請求の範囲第
3項記載の高信頼性封止構造体の製造方法。
4. The method for producing a highly reliable sealing structure according to claim 3, wherein a radiant energy beam is used as a heat source for forming the solder solidification structure.
JP62210338A 1987-08-26 1987-08-26 Highly reliable sealing structure and manufacturing method thereof Expired - Lifetime JPH0712066B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210338A JPH0712066B2 (en) 1987-08-26 1987-08-26 Highly reliable sealing structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210338A JPH0712066B2 (en) 1987-08-26 1987-08-26 Highly reliable sealing structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6454748A JPS6454748A (en) 1989-03-02
JPH0712066B2 true JPH0712066B2 (en) 1995-02-08

Family

ID=16587756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210338A Expired - Lifetime JPH0712066B2 (en) 1987-08-26 1987-08-26 Highly reliable sealing structure and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0712066B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0392673U (en) * 1990-01-10 1991-09-20
US5135397A (en) * 1990-06-28 1992-08-04 Hughes Aircraft Company 3-d weather for digital radar landmass simulation
JPH04372079A (en) * 1991-06-20 1992-12-25 Matsushita Electric Ind Co Ltd Picture display device
EP1920864B1 (en) * 2006-11-13 2022-07-13 Volvo Car Corporation Method for laser brazing with twinspot
JP6189744B2 (en) * 2013-12-26 2017-08-30 京セラ株式会社 Sample holder

Also Published As

Publication number Publication date
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