JPH07119773B2 - Trigger circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trigger circuit used in a digital oscilloscope or the like, and more particularly to a trigger circuit capable of arbitrarily setting a plurality of trigger conditions.

[0002]

2. Description of the Related Art In a device for measuring an electric signal such as a digital oscilloscope, in order to measure a selected event of an input signal, it is necessary to trigger when the event occurs. Conventionally, in order to set a trigger based on a plurality of events, a circuit including the same number of trigger detection means, delay circuits, and logic circuits is used, and a trigger is activated when a predetermined condition is satisfied. Such conventional trigger circuits are described in JP-A-63-169568, JP-A-3-72269 and JP-A-3-73864.

[0003]

In the past, due to the circuit configuration, it was possible to set only certain limited trigger conditions or it was difficult to set complicated trigger conditions. Then, the objective of this invention is providing a trigger circuit with a simple structure.
Another object of the present invention is to set a variety of trigger conditions,
It is to provide a trigger circuit that can be easily changed.

[0004]

The trigger circuit of the present invention comprises:
Analog that converts analog input signals to digital signals
An R having a digital converter, a detecting means for outputting a digital signal indicating the inclination direction of the input signal, and a plurality of address terminals and a plurality of data output terminals as a digital memory.
AM (random access memory). The analog-to-digital converter generally has a resolution of about 10 bits and supplies the high-order bits having the precision necessary for the voltage level determination to the RAM. Further, the output data from the first data output terminal of the RAM is delayed by a desired time and supplied to the third address terminal of the RAM (delay means), and the output data from the second data output terminal of the RAM. A flip-flop (latch means) for latching for a desired time and supplying it to the fourth address terminal of the RAM is provided, digital data corresponding to a desired trigger condition is stored in the RAM (digital memory), and the analog data is obtained. When the input signal matches the desired trigger condition, the RA
Output data is generated as a trigger signal for the third data output signal of M.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a preferred embodiment of the present invention. Although not shown, a RAM (random access memory) 16
The address input terminal and data output terminal of the
It is connected by a bus and its contents can be rewritten arbitrarily. All clocks in the figure are synchronized. The analog / digital (A / D) converter 12 generally has a resolution of about 10 bits and converts an input signal from the input terminal 10 into a digital signal. The RAM 16 receives from the A / D converter 12 at its input address terminal high-order bits having an accuracy necessary for determining the voltage level of the input signal.
The slope detection circuit 14 is provided to make the slope (slope) of the input signal from the input terminal 10 one of the trigger conditions. This latches the logic level "1" when the slope is positive and the logic level "0" when the slope is negative, and supplies it to the address input terminal A3 of the RAM 16 as a slope signal. In addition,
The data output terminal of the RAM may also be used as the data input terminal.

RS flip-flop (latch means) 1
8 receives the set F signal and the reset F signal from the data output terminals D5 and D4 of the RAM 16 and sets and resets the flag signal. First timer (first delay means)
20 receives the start 1 signal from the data output terminal D3, starts counting the clock, and outputs the stop 1 signal when it counts for a set time that can be set arbitrarily.
However, when receiving the reset 1 signal from the data output terminal D2, the first timer 20 is reset. The second timer (second delay means) 22 operates similarly.

An actual operation example of the device of the present invention will be described assuming that an analog input signal shown in FIG. 2 is received. As a first example, when the event E1 has a voltage V1 and a positive slope, and the event E2 has a voltage V2 and a positive slope, the event E1
Consider the trigger condition of triggering at event E2 that comes next. FIG. 3 is a state map satisfying this condition. In addition, in this case, via the address bus and the data bus, the microprocessor stores the data in the RAM 14.
It stores data such as. (Regarding the relationship between address input and data output, which are not shown in Tables 1 to 3 below, the data output value is
0 ". Also,". "In the table indicates an arbitrary value.)

[Table 1]

When the voltage V1 is represented by a digital signal, the MSB
Is "1", the next digit is "0", and the voltage V2 is the MSB is "0" and the next digit is "1". If it is necessary to increase the precision, it is sufficient to use the next digit. When signal input is started, the state of waiting for event E1 is entered. If the address input terminal A6 of the RAM 16 receives "1" and A5 receives "0" at time T1, the input signal is V
When the address input terminal A3 receiving the slope signal is "1" at the same time, the slope of the input signal is positive, and it can be known that the event E1 has occurred. Then, the data output terminal D5 becomes "1" and RS
Since "1" is latched by the flip-flop 18 as a flag signal, the address terminal A2 of the RAM 16 is "1".
1 "and enters the event E2 waiting state. In this event E2 waiting state, when the input signal becomes voltage V2 and the slope becomes positive at time T2, that is, the address terminal A6 of the RAM 16 is" 0 "and A5 is" 1 ". , A3 becomes "1" and the next clock is input to the RAM 16, a trigger signal is output from the data output terminal D6. At the same time, a reset F signal that resets the flag signal of the RS flip-flop 18 is output. As a result, the E1 waiting state is entered again.

FIG. 4 is a state map showing the second embodiment. This is because during the time t1 to the time t1 + t2 that can be set arbitrarily from the time when the event E1 occurs, the voltage V
The trigger condition is that the event E3 in which the slope is negative in 2 occurs. Therefore, the trigger signal occurs at time T4 as shown in FIG. In this case, the microprocessor makes the contents stored in the RAM 14 as shown in Table 2.

[Table 2]

When the event E1 occurs at the time point T1, the start 1 signal and the start 2 signal are generated, and the time t1 counting state is entered. At this time, the first and second timers (delay means) 20 and 22 start counting clocks at the same time,
After a lapse of time t1 and t1 + t2, respectively, the stop 1 signal and the stop 2 signal of the logic level "1" are output to the address terminals A1 and A0 of the RAM 16, respectively.
Latch both terminals to "1". Here, it is assumed that the stop 1 signal is output earlier in time than the stop 2 signal. When the first timer 20 outputs the stop 1 signal,
The state of counting time t1 shifts to the state of waiting for event E3. Here, if the input signal becomes the voltage V2 and the slope becomes negative before the second timer 22 outputs the stop 2 signal, that is,
At time T4, the address terminals A6, A5, A of the RAM 16
3, A1 and A0 are logical levels "0" and "0", respectively.
When it becomes 1 "," 0 "," 1 "and" 0 ", a trigger signal is output from the data output terminal D6, and a reset signal and a reset 1 signal are output from the D2 and D0 terminals to the first and second timers, respectively. And reset 2 signal is output, and
Return to 1 wait state. On the other hand, when the stop 2 signal comes before the event E3 occurs in the E3 waiting state, the RAM outputs only the reset 1 signal and the reset 2 signal without outputting the trigger signal, and returns to the E1 waiting state.

FIG. 5 shows a state map of the third embodiment. In the first embodiment, when the input signal does not reach the voltage V2 at the time point T2, that is, when the event E2 does not occur at the time point T2, as shown by the broken line in FIG. The event E2 triggers. However, in the third embodiment, the trigger is applied only when the event E2 occurs within the time t3 after the event E1 occurs. In this case, the microprocessor makes the contents stored in the RAM 14 as shown in Table 3.

[Table 3]

Similarly to the above, when the signal input is started, the event E1 waits, and when the event E1 occurs, the set F signal and the start 1 signal are generated at the data output terminals D5 and D3, and the RS flip-flop 18 is flagged. signal"
1 "is latched and the event E2 wait state occurs. When the event E2 occurs after the event E1 and before the time t3 elapses, a trigger signal is generated at the data output terminal D6, and the reset 1 signal and the reset F signal are generated. If the event E2 does not occur before the time t3 elapses, the stop 1 signal is generated, the trigger signal is not generated, and the reset 1 signal and the reset F signal are generated. Return to the waiting state for event E1.

The following can be considered as an application example of the third embodiment. In the normal case, as shown by the solid line in FIG. 2, after the event E1 occurs at time T1, the time T2 is reached within time t3.
Event E2 occurs at. Event E within this time t3
This is to trigger when 2 does not occur. In this case, the microprocessor makes the contents stored in the RAM 14 as shown in Table 4.

[Table 4]

As described above, the latch means and the first and second delay means may be used individually or in combination, and it goes without saying that various kinds of trigger conditions other than the above can be set.

According to the trigger circuit of the present invention, the structure is simple by using the digital memory. Further, by simply changing the contents of the digital memory, the voltage level, slope, and time relationship of the input signal as the trigger condition can be set arbitrarily, so that many kinds of trigger conditions can be easily set.

[Brief description of drawings]

FIG. 1 is a block diagram of a trigger circuit according to the present invention.

FIG. 2 is a diagram showing an example of trigger conditions for an input signal used in the embodiment.

FIG. 3 is a state map showing the first embodiment.

FIG. 4 is a state map showing a second embodiment.

FIG. 5 is a state map showing a third embodiment.

[Explanation of symbols]

 10 Input Terminal 12 Analog-to-Digital Converter 14 Inclination Detection Circuit 16 RAM (Random Access Memory) 18 RS Flip-Flop 20 First Timer 22 Second Timer

Claims (3)

[Claims] 1. An analog-to-digital converter for converting an analog input signal into a digital output signal, a tilt detection circuit for generating a digital signal indicating a tilt direction of the analog input signal, and a digital output of the analog-to-digital converter. A digital memory for receiving at least the most significant bit of the signal and a digital output signal of the slope detection circuit at first and second address terminals, respectively, and delaying output data from the first data output terminal of the digital memory by a desired time Then, the delay means for supplying the third address terminal of the digital memory and the output data from the second data output terminal of the digital memory are latched and supplied to the fourth address terminal of the digital memory. Latching means, the digital memory corresponding to a desired trigger condition is added to the digital memory. Accumulating data, when said analog input signal coincides with the above desired trigger conditions, trigger circuit, characterized in that for generating output data as a trigger signal to the third data output signal of said digital memory. 2. An analog / digital converter for converting an analog input signal into a digital output signal, a slope detection circuit for generating a digital signal indicating a slope direction of the analog input signal, and a digital output of the analog / digital converter. A digital memory for receiving at least the most significant bit of the signal and a digital output signal of the slope detection circuit at first and second address terminals, respectively, and delaying output data from the first data output terminal of the digital memory by a desired time A digital data corresponding to a desired trigger condition is stored in the digital memory, and the analog input signal matches the desired trigger condition. Trigger output data to the third data output signal of the digital memory Trigger circuit, characterized in that generated as No.. 3. An analog / digital converter for converting an analog input signal into a digital output signal, a slope detection circuit for generating a digital signal indicating a slope direction of the analog input signal, and a digital output for the analog / digital converter. A digital memory for receiving at least the most significant bit of the signal and the digital output signal of the slope detection circuit at first and second address terminals, respectively, and latching output data from the first data output terminal of the digital memory, Latching means for supplying to a third address terminal of the digital memory, digital data corresponding to a desired trigger condition is stored in the digital memory, and when the analog input signal matches the desired trigger condition. , Using the output data as the trigger signal for the third data output signal of the digital memory Trigger circuit characterized in that occur.