JPH0711919B2 - Static random access memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a static random access memory (hereinafter abbreviated as SRAM), which consumes unnecessary power during data reading. The present invention relates to a static random access memory having an internal control circuit that consumes less power and more reliably performs a read operation to reduce power consumption and yield.

(Prior Art) FIG. 3 shows a part of a conventional SRAM. An address signal input terminal 1 is connected to an address input circuit 2 through which an address signal is guided. It is connected to a row decoder 3 which decodes the row address signal guided. This row decoder 3 is connected to a word line 4 which is selectively driven by the output of the row decoder 3,
The bit line pair 5, is connected to a bit line initialization circuit 6 which initializes the bit line pair 5, ... A plurality of static type memory cells 7 of the same column are connected to the bit line pair 5, and a plurality of static memory cells 7 of the same column are connected to the word line 4. The address input circuit 2 is connected to a column decoder 8 which decodes a column address signal derived from the address input circuit 2. The column decoder 8 selects a bit line pair 5 by the output of the column decoder 8. It is connected to the circuit 9. The column selection circuit 9 is a sense amplifier for amplifying the data read to the bit line pair 5 selected by the column selection circuit 9.
The sense amplifier 10 is connected to a data output circuit 11 that outputs the data output from the sense amplifier 10 to the outside through a data output terminal 12. The address input circuit 2 senses a change in the address signal input to the address input circuit 2 during the read operation, and activates the bit line initialization circuit 6 at the moment of starting the reading of the data of the memory cell 7 of the new address. Is connected to an address change detection circuit 13 for generating an address change detection signal, and this address change detection circuit 13 activates the sense amplifier 10 and the data output circuit 11 for a certain period after the address change detection signal is generated. It is connected to a clock signal generation circuit that generates a clock signal that causes the clock signal.

Each of the memory cells 7 is constructed, for example, as shown in a portion surrounded by a broken line 7 in FIG. That is, N _{1 to} N ₄
And R ₁ and R ₂ are an N-channel MOS-FET (insulated gate type field effect transistor) transistor and a high resistance load, respectively, and the transfer transistors N ₃ and N ₄ each have a bit line pair 5 at one end. The gates of the driving transistors N ₁ and N ₂ are connected to different bit lines and commonly connected to the word line 4, the sources of the driving transistors N ₁ and N ₂ are grounded, and their gates and drains are cross-connected. In addition, the respective drains are connected to the other ends of the transfer gate transistors N ₃ and N ₄ , respectively, and the high resistance load R ₁ and
R ₂ has one end connected to the power supply V _DD, and the other end connected to the drains of the driving transistors N ₁ and N ₂ , respectively. The above transistors N ₁ and N ₂
A flip-flop circuit is formed by the high resistance loads R ₁ and R ₂ .

Further, the bit line initialization circuit 6 is configured, for example, like a portion surrounded by a broken line 6 in FIG. That is, P ₁ and P ₂ are respectively P-channel MOS-FETs, the sources thereof are respectively connected to the bit line pair 5, the drains thereof are both connected to the power source V _DD , and the gates thereof are both connected to the output line of the inverter I _1. Therefore, the inverter I ₁ uses the output line 21 of the address change detection circuit 13 as an input line.

Further, the column selection circuit 9 is configured, for example, like a portion surrounded by a broken line 9 in FIG. That is,
The transfer transistors P ₃ and P ₄ are P-channel MOS-
FET, and its drain is paired with bit line 5,
The input line pairs 25 of the source, each said sense amplifier 10, ▲ ▼ to its gate are both connected to the output line of the inverter I _2, the inverter I ₂ inputs the output line 22 of the column decoder 8 It has a line.

The sense amplifier 10 is constructed, for example, like a portion surrounded by a broken line 10 in FIG. That is, N ₅ , ~,
_{N 10, N 5 ', ~} , N 10' is N- transistor channel _{MOS-FET, P 5, ~} , P 8, P 5 ', ~, P 8' is P- channel MOS-
The gates of the input transistors N ₅ and N ₅ are connected to the sense amplifier input line 25 and ▲ ▼, respectively, and the drains of the control transistors N ₇ and N ₈ are the input transistors N ₅ and N, respectively. The source of ₆ and the gate thereof are both connected to the output of AND1, and AND1 is the output line of the address change detection circuit 13 generated by the clock signal line 23 which is the output line of the clock signal generation circuit and the inverter I ₆ . The inverted signal of 24 is input, the drain of the current limiting transistor N ₉ is connected to the sources of N ₇ and N ₈ , the gate is connected to the power supply V _DD , and the source is grounded. N ₁₀ is an equipotential transistor whose source and drain are connected to the drains of the input transistors N ₅ and N ₆ , and whose gate is connected to the output line 24 of the address change detection circuit 13, and P ₅ and P Reference numeral ₆ denotes a load transistor in which each drain is connected to the power supply V _DD , each source is connected to the drains of the transistors N ₅ and N ₆ , and both gates are connected to the drain of the transistor N ₆ . P ₇ and N ₈ are sense amplifier initialization transistors whose drains are connected to the power supply V _DD , their sources to the drains of the transistors N ₅ and N ₆ , and their gates connected to the output line of the AND1. _{N 5 ', ~, N 10} ', P 5, '~P 8' is _{N 5, ~, N 10,} P 5,
~, And is connected in the same manner as P _8, but the input transistor
The only difference is that the gates of N ₅ ′ and N ₆ ′ are connected to the sense amplifier input line pair 25, ▲ ▼, respectively. Also N
Reference numeral ₁₁ denotes an N-channel MOS-FET transistor, the source and drain of which are transistors N ₅ and N ₅ ′, respectively.
Output line pair of the sense amplifier 10, that is, 26, ▲ ▼
In addition, the gate is an equipotential transistor connected to the output line 24 of the address change detection circuit 13.

The transistors N ₁₀ , N ₁₀ ′, N ₁₁ and P ₇ , P ₈ , P ₇ ′, P
_{At 8} ', the sense amplifier 10 is initialized at the time of reading.

The data output circuit 11 is constructed, for example, as shown in FIG. That, NOR1, ~, NOR6 two-input NOR, I _4, I ₅
Is an inverter, P ₉ is a P-channel MOS-FET, N ₁₂ is N-
It is a channel MOS-FET, and one input terminal of each of NOR1 and NOR2 has an output line pair ▲ ▼, 2 of the sense amplifier 10.
6, the other input terminals of which are respectively cross-connected to the output terminals of NOR2 and NOR1. Also NOR3,
NOR4 the one input terminal of each is connected to the output terminal of the NOR1, NOR2, the respective other input terminal is connected to both the output terminal of the inverter I _4, inverter I ₄ is the clock signal line 23 Is connected to the input end. Also, NO
One input terminal of each of R5 and NOR6 is NOR3 and NOR4
Is connected to the output end of the
Cross-connected to the output terminals of NOR6 and NOR5. The output terminal of NOR5 is connected to the input terminal of the inverter I _5. The drain of the FETP ₈ is connected to the power supply V _DD , the gate is connected to the output terminal of the inverter I ₅ , and the source is connected to the data output terminal 12. The drain of the FET N ₁₂ is connected to the data output terminal 12, the gate is connected to the output end of the NOR 6, and the source is installed.

Next, the read operation of the SRAM of FIG. 3 will be described. First, the address signal is input to the address input circuit 2 via the address input terminal 1, and the row address signal and the column address signal are respectively supplied from the address input circuit 2 to the row decoder 3,
The address change detection circuit 13 detects the address change and outputs an extremely short address change detection signal while being output to the column decoders 8, respectively. By this address change detection signal, the bit line initialization circuit 6 causes the bit line pair
5, 5 are all initialized to the power supply voltage V _DD , and at the same time, a specific word line 4 is selected by the decode output of the row decoder 3 and the memory cells 7 in the same row connected thereto are selected. Bit line pair 5 according to the data of 7,
A potential difference is generated between them, and one of the column selection circuits 9 is selected by the decode output of the column decoder 8, and the potential of the bit line pair 5, of the selected column is transmitted to the sense amplifier 10. On the other hand, the clock signal generation circuit 14 is activated by the address change detection signal, and the clock signal is generated for a certain period of time. The output line pair of the sense amplifier 10 is initialized to the power supply voltage V _DD by the address change detection signal, and then the sense amplifier 10 is activated while the clock signal is generated, and the bit line pair 5 ,
Of the output signal pair of the sense amplifier 10 is amplified through the data output circuit 11 to output data to the data output terminal 12. At this time, the pair of sense amplifier output lines is initialized to the power supply voltage V _DD , so that the data output terminal 12 once becomes a high impedance state, and then the sense amplifier 10 starts to operate and outputs data.
Then, after a certain period of time, when the clock signal ends, the sense amplifier 10 is deactivated, and the data output circuit 11 continues to output data to the outside through the data output terminal 12.

(Problems to be Solved by the Invention) By the way, in the conventional SRAM described above, when the driving force of the bit line pair 5, of the memory cell 7 is weak, a sufficient potential difference is generated in the bit line pair 5 ,. It takes time to appear. On the other hand, since the clock signal operates only for a certain period of time and the sense amplifier 10 is inactivated, there is a possibility that the read operation ends before the data of the memory cell 7 is output, resulting in a defect. there were.

On the contrary, when the driving force of the bit line pair 5 of the memory cell 7 is strong, the sense amplifier 10 is turned on while the clock signal is on even after the data is output to the data output terminal 12. Continues to be activated and the above sense amplifier
There was a drawback that the power consumed in 10 might be wasted.

The present invention has been made in view of the above circumstances, and by deactivating the sense amplifier after the data is output to the data output circuit, it is possible to reliably perform the read operation, and waste power. It is an object to provide a static random access memory that does not consume.

[Structure of the Invention] (Means and Actions for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides a plurality of static memory cells for data storage and data storage between these memory cells. A bit line pair for transmission / reception, a sense amplifier for amplifying the data of the memory cell appearing on the bit line pair, and a high impedance output while the sense amplifier does not amplify and output the data of the memory cell at the time of reading Then, a data output circuit for outputting the data to the outside, an address input circuit for inputting an address signal for selecting any one of the plurality of memory cells, and the address signal Is detected, the bit line pair is initialized to a certain equipotential during reading, and the output line of the sense amplifier is set to a high potential. An address change detection circuit for generating an address change detection signal for activating, and a clock signal for a certain period of time after the address change detection signal is generated at the time of reading to activate the sense amplifier and the data output circuit. And a clock signal generating circuit for deactivating the sense amplifier and the data output circuit to terminate the read operation when the clock signal ends. Is still in a high impedance state, or is provided with a data output sensing circuit for sensing whether it is already in a data output state, until the data output circuit outputs data even after the clock signal is terminated by the data output sensing circuit, Activates the sense amplifier and data output circuit The read operation is ended by deactivating the sense amplifier and the data output circuit by sensing that the data is output, and data is output from the sense amplifier to the data output circuit. A data output sensing circuit that senses that the data has been output, continues to activate the sense amplifier while the data is not yet output, and deactivates the sense amplifier after the data is output, thus ensuring a read operation. It is characterized in that it does not consume unnecessary power.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.
The SRAM shown in FIG. 1 is the conventional SR described above with reference to FIG.
Compared to AM, a data output sensing circuit 15 that senses the state of the data output circuit 11, a clock signal generating circuit 14, and an OR circuit that uses two output lines of the data output sensing circuit 15 as input.
The sense amplifier 10 and the data output circuit 11 are controlled by 16 differently, and the other points are the same as the conventional example. Therefore, in FIG. 1, the same parts as those in FIG. Omit it.

The data output sensing circuit 15 is constructed, for example, as a portion surrounded by a broken line 15 in FIG. That is, NOR15 which inputs the outputs of NOR5 and NOR6 of the data output circuit 11 into two inputs
Produces the signal on output line 30.

Next, the read operation of the SRAM of the present invention shown in FIG. 1 will be described. The operation from the input of the address signal from the address input terminal 1 to the output of the data of the memory cell 7 to the data output circuit 11 and the reading of the data to the outside through the data output terminal 12 is the same as described with reference to FIG. But
The difference is that the sense amplifier 10 and the data output circuit 11 continue to be activated until the output signal of the OR circuit 16 which is the logical sum of the data output sensing circuit 15 and the clock signal generation circuit 14 ends. That is, it is assumed that the force for driving the bit line pair 5, ... Of the memory cell 7 is weak, it takes time until the data is output to the data output circuit 11 through the sense amplifier 10, and the clock signal ends during the read operation. Also, since the sense amplifier 10 and the data output circuit 11 are continuously activated by the output signal of the data output sensing circuit 15, the read operation can be completed. In addition, adjust the length of time the clock signal is being generated to
10 and the data output circuit 11 are activated, and the clock signal is terminated after the signal for activating the sense amplifier 10 and the data output circuit 11 is output from the data output sensing circuit 15 as well. 7 bit line pairs
If the force for driving 5, ... Is so strong that the data is read out to the data output circuit 11 through the sense amplifier 10 quickly, the data output sensing circuit immediately follows.
Since the output signal of 15 ends, the sense amplifier 10 and the data output circuit 11 are deactivated.

[Advantages of the Invention] As described above, in the SRAM of the present invention, the read operation is ended by sensing that the data in the memory cell has been read at the time of read, so that the read operation is performed in comparison with the conventional SRAM. There is an advantage that it can be surely performed, and at the same time, wasteful power is not consumed.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an embodiment of an SRAM according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the data output circuit in FIG. 1, and FIG. 3 is a schematic diagram showing a conventional SRAM. Figure,
FIG. 4 is a circuit diagram showing one specific example by taking out each one of the memory cell, the bit line initialization circuit, the column selection circuit, and the sense amplifier in FIG. 3, and FIG. 5 is the data output circuit in FIG. It is a circuit diagram which shows one specific example. 1 ... Address input terminal, 2 ... Address input circuit, 3
...... Row decoder, 4 ...... Word line, 5, Bit line pair, 6
... bit line initialization circuit, 7 ... memory cell, 8 ... column decoder, 9 ... column selection circuit, 10 ... sense amplifier, 11
...... Decoder output circuit, 12 ...... Data output terminal, 13 ......
Address change detection circuit, 14 ... Clock signal generation circuit,
15 …… Data output sensing circuit, 16 …… OR circuit.

Claims (1)

[Claims] 1. A plurality of static type memory cells for storing data, a bit line pair for transmitting and receiving data to and from the memory cells, and data of the memory cells appearing on the bit line pairs. A sense amplifier that amplifies, and a data output circuit that outputs high-impedance data while outputting high-impedance data while this sense amplifier is not amplifying and outputting the data in the memory cell at the time of reading.
An address input circuit for inputting an address signal for selecting any one memory cell of the plurality of memory cells, and a change in the address signal is detected to detect the bit line pair at the time of reading. Address change detection circuit for generating an address change detection signal for initializing the output line of the sense amplifier to a high potential and for a certain period of time after the address change detection signal is generated during reading. A clock for activating the sense amplifier and the data output circuit to perform the read operation, and deactivating the sense amplifier and the data output circuit to terminate the read operation when the clock signal ends. In a static random access memory equipped with a signal generation circuit, the above data Is the output circuit in a high impedance state?
A data output sensing circuit is provided for sensing whether or not the data output state is present, and the data output sensing circuit activates the sense amplifier and the data output circuit until the data output circuit outputs data even after the clock signal ends. By continuously deactivating the sense amplifier and the data output circuit by sensing the output of data,
A static random access memory characterized by terminating the read operation.