JPH07118495B2 - Film carrier tape - Google Patents

Description

TECHNICAL FIELD The present invention relates to a film carrier tape, and more particularly to a film carrier tape capable of easily carrying out an analysis of actual control defects on a substrate or the like.

[Prior Art] In a semiconductor device having a large number of leads such as an integrated circuit, an automatic bonding technique using a tape-shaped film carrier is widely used because of its advantages in mass production.

Conventional film carrier tape As shown in FIG. 3, an insulating film such as polyimide having a sprocket hole 2 for transporting and positioning and a device hole 3 which is an opening for receiving a semiconductor chip is used as a base film 1. A metal foil of copper or the like is adhered onto 1 to form a wiring lead of a desired shape and a selection pad 5 for electrical selection by etching the metal foil, and this lead and a bump which is an electrode terminal of the semiconductor chip 9. Inner lead bonding (hereinafter referred to as ILB) by thermocompression bonding or eutectic bonding. In this state, the selection pad 5 is used to perform electrical selection and bias test, and then the leads are cut into desired lengths. When the number of leads is large, leave the base film 1 close to the lead cutting point in order to prevent the part of the lead tip that is bonded to the substrate or the lead frame, etc. (outer lead boding; called OLB) from coming apart. Methods are often used. According to this method, the OLB hole 4 shown in FIG. 3 is provided in the base film 1, and the leads are passed over it. To do. By doing this, the OLB can be performed at one time regardless of the number of leads, which is advantageous in terms of mass productivity.

[Problems to be Solved by the Invention]

In the case of the conventional film carrier tape described above, the selection pad 5 needs to be formed in a region outside the OLB hole 4, which is an opening for forming an OLB lead. By providing the selection pad 5 in this region, the semiconductor chip 9 and the IL
From part B (the lead part in the debye hole 3) O
It is possible to electrically check for defects such as shorts and opens in the pattern on the film carrier tape up to the LB lead. However, after this ILB, electrical selection
Whether the pattern is defective or the semiconductor chip 9 itself is defective even if a defective accident occurs due to various causes after cutting the leads and performing the OLB on the printed circuit board or the lead frame, or during use as a product. Since it is not possible to pursue a failure mode or the like, it is very difficult to determine the cause of the failure.

That is, even if the film carrier tape is peeled off from the OLB printed circuit board by a technique such as repair for failure analysis, the selection pad 5 is not present on the film carrier tape and a fine line of 80 μ to 150 μ Since only the pattern formed by the width remains, it is difficult to apply a probe or the like to check the electrical characteristics.
It is also possible to analyze the defect by contacting a probe etc. on the bump of the semiconductor chip, but the lead of the film carrier is already ILB on this bump, and some products may be protected with a resin such as epoxy. Therefore, it takes a lot of man-hours to carry out the failure analysis, and it is difficult to carry out the failure analysis reliably.

In this way, in the film carrier tape system, once the IL
If lead cutting is performed after B is performed, the selection pad disappears, so it is extremely difficult to investigate the cause of the defect. An object of the present invention is to provide a film carrier tape which eliminates the above drawbacks.

[Means for Solving the Problems]

The film carrier tape of the present invention is a sorting pad provided at the tip of a usual outer lead as a wiring lead between an outer lead bonding lead for connecting to the outside and an inner bonding lead for connecting to a semiconductor chip. In addition to, each pad for failure analysis,
It is provided on the upper surface, the lower surface, or both surfaces of the base film.

[Operation] Even after the film carrier tape is connected to each semiconductor chip after inner lead bonding (ILB), the failure analysis pad can be accessed from the outside.
Chip failure analysis and the like can be performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a partial front view of an embodiment of the present invention. In the area on the upper surface of the film carrier between the ILB lead 7 and the OLB lead 8, a defect analysis pad 10 other than the sorting pad 5 is provided on the lead formed by each ILBH lead 7.
Is provided. The defect analysis pad 10 is an ILB lead 7
Since it is connected to, it can be used as a pad for general electrical selection after ILB, but defects such as open OLB lead 8 cannot be checked. It is used for analysis. Specifically, for example, the dimensions of the OLB OLB when the lead pitch between leads 8 of 500μ size sorting pad 5 400Myu～450myu ^□ in failure analysis pad 10 located in the hole 4 is be 300Myu～400myu ^□ Therefore, a normal jig can be used. The position of the failure analysis pad 10 should be as close to the OLB hole 4 as possible,
Allow them to be spaced from each other.

Next, in the case where the number of pins is further increased to form, for example, 400 to 1000 pins, the pitch of the OLB leads 8 is 300 to
400μ pitch, the size of the sorting pad 5 is 250-300μ
^□ In the case of such dimensions and pitches, it is not possible to design the defect analysis pads 10 connected to the respective ILB leads 7 in the area on the upper surface of the film carrier between the ILB leads 7 and the OLB leads 8. It is possible, and even if it is provided, it will be 100 to 150 μ ^□ , so that it will be difficult to perform an evaluation that is stable and reliably reliable as a failure analysis pad. Therefore, in the case of a multi-pin semiconductor device, the second
As shown in the figure, if a defect analysis pad is provided on the back surface of the tape through the through hole 11, the wiring pattern line width connecting the ILB lead 7 and the OLB lead 8 on the upper surface of the film carrier tape is, for example, 100 to 150 μm. Even 150-200 μm
It is possible to form the defect analysis pad 10 of 250 to 300 μ ^□ having the same size as the selection pad 5 through the φ through hole 11. When a defect analysis pad is formed on the back surface of the tape through the through holes in this way, a pad relatively large in dimension is used because there is no pattern for connecting the ILB lead and the OLB lead on the back surface of the tape. Can be formed. This embodiment is particularly useful for improving reliability when applied to a multi-pin IC used in a large computer or the like. Note that the failure analysis pad may be provided on both the upper surface and the lower surface depending on the case.

〔The invention's effect〕

As described above, the present invention, after the OLB work by providing a failure analysis pad connected to each ILB lead on the upper surface or the lower surface or both surfaces of the film carrier tape between the ILB and the OLB lead of the film carrier tape,
Or, if a defect occurs during actual use as a product, it is possible to easily and surely evaluate what kind of electrical defect the IC has when using this film carrier tape. It is also possible to provide quick feedback to IC design and manufacturing process design.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are partial front views of an embodiment of the present invention, and FIG. 3 is a partial front view of a conventional example. 1 ... Base film, 3 ... Device hole, 4 ... OLB hole, 5 ... Selection pad, 7 ... ILB lead, 8 ... OLB lead, 9 ... Semiconductor chip, 10 ... Failure analysis pad, 11 ... Through hole.

Claims (1)

[Claims] 1. A film carrier tape for forming a predetermined wiring pattern on a base film, wherein wiring between an outer lead bonding lead for connecting to the outside and an inner bonding lead for connecting to a semiconductor chip. A film carrier tape characterized in that, in addition to a normal sorting pad provided at the tip of an outer lead, a failure analysis pad is provided on each of the leads on the upper surface, the lower surface, or both surfaces of the base film.