JPH07118479B2 - Transistor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor device, and more particularly to an unsaturated PNP transistor element.

[Prior art]

P used in a conventional bipolar integrated circuit
The NP-type transistor device has drawbacks that the switching speed is slow because the base capacitor is large, the base width is thick and wide, and the storage time becomes large in the saturation region.

The conventional bipolar integrated circuit includes a lateral PNP transistor and a SuB (substrate) PN.
P-transistors are used. The lateral PNP transistor has an h _FE of 20 to 80 and a transition frequency f _T of 4 MHz, and the SuBPNP transistor has an h _FE of 50 to 200 and a transition frequency f _T of 40 MHz. Therefore, when high gain and high frequency characteristics are required, the SuBPNP transistor is advantageous, and its collector is disadvantageously clamped to the substrate potential.

[0004]

In recent years, a SuBPNP transistor has been proposed as a transistor device that eliminates such drawbacks. This transistor has problems such as a low breakdown voltage between the collector and the substrate and a large capacitance.

Therefore, an object of the present invention is to provide a transistor device in which the base capacitor is reduced and the switching speed is improved.

[0006]

A transistor device according to the present invention has a P-type semiconductor substrate as shown in FIG.
(2) N-type semiconductor separated by P-type semiconductor region (6)
The body region (8) forms the collector region,
Formed by a P-type semiconductor region (10) in the rector region
A base region is formed, and an N-type semiconductor is formed in the base region.
The emitter region formed by the region (12) is formed.
And the first transistor (32)
The semiconductor region forming the base region of the transistor is
A collector region, the semiconductor region forming the emitter region,
A base region, and a P-type semiconductor region (1
A second transistor having an emitter region formed of 4).
Transistor (30), the semiconductor substrate is a collector region,
The collector region of the first transistor is a base region,
The base region of the first transistor is referred to as an emitter region.
And a third transistor (34) formed by
The P-type semiconductor region of the second transistor
The periphery and the bottom of the emitter region are formed from the P-type semiconductor region.
It is characterized in that it is surrounded by the collector region .

[0007]

In this transistor device, the first and
A second transistor comprising a second and a third transistor,
The bottom and the periphery of the emitter region formed of the P-type semiconductor region
Part is surrounded by a collector region composed of a P-type semiconductor region.
By the reduction of the base capacitor, the switch
The improvement of the running speed has been achieved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings.

1 and 2 show an embodiment of a transistor device of the present invention, FIG. 1 shows its equivalent circuit, and FIG. 2 shows its configuration. The transistor device, as shown in FIG. 1, a first trunk consisting of PNP transistor
The transistor 32, the second transistor 30, and the third transistor
A register 34 is installed. Transistors 30, 34
Is connected in series, and a transistor 3 is formed between the bases of the transistors 30 and 34 and forms a forward direction from the base side of the transistor 34 toward the base side of the transistor 30.
2 is connected, and the base of the transistor 32 is commonly connected to the intermediate connection point of the transistors 30 and 34. Further, the base of the transistor 34 is commonly connected to the emitter, which is the non-grounded terminal of the transistor 30. Then, the transistor 30 has an emitter electrode 2
0, the base electrode 22 is at the base of the transistor 30, and the collector electrode 2 is at the intermediate connection point between the transistors 30 and 34.
4. The base of the transistor 34 is the base electrode 26, and the collector of the transistor 34 is the collector electrode 28.
Are formed. In this embodiment, the collector electrode 28
Is grounded.

In a transistor device which realizes such an equivalent circuit, as shown in FIG. 2, after an N ⁺ type buried layer 4 is formed on the surface layer of a P type semiconductor substrate 2, N type buried layer 4 is formed.
Type epitaxial layer is formed, and this epitaxial layer is partitioned and separated by the isolation region 6 to form the first N-type semiconductor region 8. A first P-type semiconductor region 10 is formed in the N-type semiconductor region 8, a second N-type semiconductor region 12 is formed in the P-type semiconductor region 10, and an inside of the N-type semiconductor region 12 is formed. Has a high impurity concentration (P
⁺ ) The second P-type semiconductor region 14 is formed. Further, N ⁺ regions 16 and 18 are individually formed in the first and second N-type semiconductor regions 8 and 12 in order to take out electrodes.

The second P-type semiconductor region 14 has an emitter electrode 20, the second N-type semiconductor region 12 has a base electrode 22, the first P-type semiconductor region 10 has a collector electrode 24, and a first electrode. An electrode 26 is formed in the N-type semiconductor region 8 and a reference potential (GND) electrode 28 is formed in the isolation region 6, and the emitter electrode 20 and the electrode 26 are electrically short-circuited.

Therefore, in this transistor device,
P-type semiconductor region 14, N-type semiconductor region 12, and first P
A PNP junction 30 formed of the P-type semiconductor region 10 forms a PNP-type transistor 30.
NP composed of P-type semiconductor region 10 and N-type semiconductor region 8
An NPN transistor 32 is formed by the N junction. In addition, the P-type semiconductor region 10 and the N-type semiconductor region 8
A PNP type transistor 34 is formed by a PNP junction composed of the isolation region 6 of the P type semiconductor region.
Then, the emitter electrode 20 and the electrode 26 are short-circuited,
The electrode 28 is connected to the lowest potential by a reference potential point, that is, ground.

According to this structure, the P-type semiconductor region 14 is the collector region formed by the P-type semiconductor region 10.
It can completely surround the periphery and the bottom of the emitter region. As a result, the base capacitor can be reduced and the base width can be reduced, and the transition frequency f
_T can be improved. That is, it is possible to prevent the switching speed from being lowered due to the charging and discharging of the base capacitor as in the conventional device.

Since the emitter electrode 20 and the electrode 26 are short-circuited, when the transistor 30 enters the saturation region, the transistor 32 becomes conductive and current flows from the collector to the emitter, so that the transistor 30 enters the saturation region. Can be prevented, and the transistor 30 can always prevent the transition to the saturation region. As a result, excessive carrier injection can be suppressed, storage time can be shortened, and switching speed can be improved.

Further, since the base of the transistor 34 connected to the collector of the transistor 30 is connected to the high potential side and the transistor 30 is always in the non-conductive state when the transistor 30 is in the operating state, the collector of the transistor 30 is always in the non-conductive state. It is kept floating from the reference potential (GND). Since the collector potential is floating above the reference potential in this way, it is not clamped as in the past,
There is an advantage that there are no restrictions on circuit usage.

Moreover, according to such a structure, a high current amplification factor can be obtained, and it can be used as a high gain amplifying element as well as a switching element.

[0017]

As described above, according to the present invention, it is possible to reduce the base capacitor, prevent the entry into the saturation region, and improve the switching speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a transistor device of the present invention.

2 is a cross-sectional view of the transistor device shown in FIG.

[Description of References] 2 P-type semiconductor substrate 6 P-type semiconductor region 8 N-type semiconductor region 10 P-type semiconductor region 12 N-type semiconductor region 14 P-type semiconductor region 30 Second transistor 32 First transistor 34 Third transistor Transistor

Claims (1)

[Claims] 1. A P-type semiconductor region is provided on a P-type semiconductor substrate.
A collector region is formed by the partitioned N-type semiconductor region
Formed in this collector region by a P-type semiconductor region
A base region is formed, and an N-type half is formed in the base region.
The emitter region formed by the conductor region is formed
And a half of the first transistor and the half of the base region of the first transistor.
The conductor region is the collector region, and the emitter region is the
A semiconductor region is used as a base region, and a P-type half is formed in this base region.
A second emitter region formed of a conductor region is formed.
A transistor, the semiconductor substrate, a collector region, the first transistor
The collector region of the transistor, the base region, the first transistor
A third base formed with the base region of the emitter as the emitter region.
Provided with a transistor, or a P-type semiconductor region of said second transistor
Of the P-type semiconductor region around and around the emitter region
A transistor device characterized in that it is surrounded by the collector region consisting of a region .