JPH0711784B2 - Computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

This invention relates to a virtual computer system (V
(MS) speed-up method, and more particularly to a method for reducing I / O simulation overhead of VMS.

[0002]

2. Description of the Related Art FIG. 1 shows a main configuration of an actual computer system 10000. 1000 is a central processing unit CPU, 200
0 is the main memory, 3000 is the input / output processor IOP,
4000 is an input / output control device IOC. 100 is C
A signal line between the PU 1000 and the main memory 2000,
200 is a signal line between the CPU 1000 and the IOP 3000, and 300 is the IOP 3000 and the main storage device 2000.
Signal line 400 between the IOP 3000 and the IOC
It is a signal line between 4000. This real computer system 10000 is a system-wide resource (CP) of an operating system (OS) on the main storage device 2000.
U, main storage device, input / output device) are managed and operated.

On the other hand, a virtual computer system (VM
FIG. 2 shows a configuration diagram in S). Real computer system 100
The hardware configuration (00, main storage device, input / output device) of 00 is the same as that of FIG. 1 except that a control program VMCP (or simply CP) of the VMS exists on the main storage device 2000. . With the hardware simulation function of the VMCP, a plurality of logical computers (called virtual machines VM) are logically realized. Each VM, namely, 10,000-1 (VM1), 1
0000-2 (VM2), 10000-3 (VM3)
Is a real computer system (called a host system) 100
It is logically realized as having the same hardware configuration as 00. Main storage device 2000-N (N =
1, 2, 3) OS-N that controls and operates each VM
Exists, and the plurality of OSs are running under one host system at the same time. The hardware configuration (CPU, main storage device,
(IOP, IOC) is logically realized by VMCP, but most of these entities exist on the corresponding hardware configuration of the host system. For example, the main storage device of the VM may occupy a part of the main storage device 2000 of the host system or may share the same, and the input / output device of the VM may be the input / output device of the host system VM. It may be shared between them, or it may occupy some I / O devices. Alternatively, there may be a case where there is no corresponding input / output device on the host system and it is realized by being virtually simulated by VMCP. In any case, the main storage device 2000-N of each VM
From the OS on (N = 1, 2, 3), the same hardware configuration (CPU, main memory, IO) as the host system
P, IOC) will be visible. Here, it should be noted that the architecture of each VM (hardware structure and function viewed from the OS) may be slightly different from that of the host system 10000. Similarly, the VMs may have different architectures.
For example, the set of machine instructions of the host system and each VM
The set of machine instructions in does not have to be exactly the same. However, completely different ones are not covered by the VMS in the present invention because the load of the VMCP becomes large and the emulation mechanism of the host system becomes large. In the virtual machine VM described in the present invention, most of the machine instructions are executed on the host system without intervention of VMCP.
It is necessary to directly execute the program with the same performance as the original performance (execution speed) of the host system. Also in FIG.
Although only three VMs are defined, in general, there may be any number, and the upper limit thereof is determined by the resource capacity of the host system and the performance of each VM. The host system also has a privileged state and a non-privileged state, and machine instructions that have a significant impact on the system (for example, IO instructions, system interrupt mask change instructions) are called privileged instructions and are used only in the privileged state. Can not do it. This is also well known.

In FIG. 3, one VM of VMS (V in this figure
The memory hierarchy of M1) is shown. 2060 is O on VM1
The OS1 is a virtual space created by S1 and exists on the main storage device 2000-1 of the VM1. The main storage device 2000-1 of the VM 1 is the main storage device 200 of the host system.
2 (the main memory 2000 of the host system is divided into a hardware system area 2001 and a programmable area 2002 as shown in FIG. 7). The mapping is the address conversion table 201.
Given by 0. FIG. 4A shows this address conversion table 2010 (1). This address conversion table 2
In 010 (1), the address r on the corresponding main storage device 2002 is described in the entry corresponding to the address v2 on the main storage device 2000-1 of the VM 1. The start address of this address conversion table 2010 (1) is
When the OS 1 on the VM 1 is operating on the main storage device 2000-1, it is stored in one control register RATOR 1110 in the basic control register group 1100 (see FIG. 7) in the CPU 1000. In this case, the address conversion table 2010 (1) exists in the main storage device 2002 of the host system, and its head address is also
It is described by the address of the main storage device 2002 of the host system and set in the register 1110. 2 in FIG.
Reference numeral 060 denotes a virtual space generated by the OS1 on the VM1, and the mapping from the virtual space to the main storage device 2000-1 of the VM1 is given by the address conversion table 2040 managed by the OS1. FIG. 4B shows the configuration of this address conversion table, and the address v2 of the main storage device 2000-1 of the corresponding VM1 is described in the corresponding entry of the address v3 of the virtual space 2060. The start address of this address conversion table 2040 is VM1.
When the OS 1 of the CPU is operating in the virtual space 2060, one control register VATOR 112 in the basic control register group 1100 (see FIG. 7) of the CPU 1000.
It is stored in 0. However, in this case, the address conversion table 2040 is stored in the main storage device 2000-1 of the OS1.
Since it exists above, the start address is also described by the address of the main storage device 2000-1 of the OS 1. The address conversion table 2010 (1) (referred to as conversion table A) is V
The MCP is a table managed and updated for each VM, and the address conversion table 2040 (referred to as a conversion table B) is a table managed and updated by the OS on each VM for its own virtual space. Here, the main storage device 2002 of the host system is the level 1 memory, and the main storage device 2 of each VM.
000-N (N = 1, 2, 3, ...) is a level 2 memory,
The virtual space 2060 created by the OS on each VM (this is
In general, the OS collectively refers to a plurality of spaces created as a level 3 memory. The virtual space is generally divided into pages of a certain size (for example, 4 KB), the pages are mapped to the main storage device, and several consecutive pages (for example, 1 MB of 256 pages) are collected, and 1 Calling a segment is well known. In 2020 in FIG. 3, the VMCP has its own input / output (I
O) IO operation command word (C
CW) group. Since the VMCP itself operates on the level 1 memory, the CCW group 2020 is created with the level 1 memory address. This is Level 1 CCW
Call. Level 1 CCW does not require address translation,
When an O start command is applied to the level 1 CCW, it is interpreted as it is by the IOP 3000, and the IOC
Sent to 4000. The IOC 4000 is to execute each CCW for each input / output device. 2030
Is a CCW prepared by the OS on the VM and described by the level 2 memory address. This Level 2 CCW is created by the OS on the VM. When an IO start command is issued from the OS on the VM to this CCW, the VMCP intervenes and sends this to the VMC.
A method in which P is converted into an equivalent level 1 CCW and the IO is activated using the equivalent level 1 CCW via VMCP is also conceivable. However, this adds to the VMCP overhead. Therefore, although VMCP intervenes, the address of the address conversion table (that is, conversion table A) 2010 from the level 2 memory to the level 1 memory is set to I
Tell OP3000, IOP3000 (See Figure 7)
However, looking at the conversion table 2010, the data address in the level 2 CCW (this is the level 2 memory address)
To the level 1 memory address and executed. This method reduces VMCP intervention and overhead. Well, VM
Most of the above OSs operate on the level 3 memory, and therefore the CCW generated by the OS on the VM often exists on the level 3 memory. 2050 in FIG.
Represents a CCW generated at a level 3 memory address, that is, a level 3 CCW. When the OS on the VM issues an IO activation command to this level 3 CCW, as in the case of the level 2 CCW 2030, the address of the address conversion table from the level 3 memory to the level 2 memory (immediately, conversion table B) , The address of the address conversion table from the level 2 memory to the level 1 memory (that is, conversion table A) is
IOP3000 (Fig. 7), IOP3000
A conversion table B converts a level 3 CCW data address (level 3 memory address) into a level 2 memory address, and the conversion table A converts the result into a level 1 memory address.
A method of executing the CCW is performed by converting the CCW into an address.

FIG. 4C shows the IOP 300 described above.
0 (FIG. 7) is an address translation buffer 3030 provided in a local storage in the IOP 3000 in order to reduce the address translation overhead. In the field 1 of the address translation buffer 3030, the VM number V
M # is the field 2, the start address of the conversion table B of the conversion table A, the field 3 is a distinction flag between them, the field 4 is the CCW data address before conversion, and the field 5 is the field 5 , The level 1 memory address after conversion is described. IOP3000 (Fig. 7)
Look at this address translation buffer, do the address translation,
Next, if it is not here, the address conversion is performed by referring to the conversion table B ′ and the conversion table A, and the result is registered in this conversion buffer 3030. This address translation buffer is
It is in a high-speed local strange in OP3000, and is faster than searching the conversion tables B and A on the main storage device 2002. It should be noted here that the level 2 CCW, the level 3 CCW, and their data buffers must all be fixed on the level 1 memory during IO execution. Now, FIG. 5 shows a method of dividing a continuous area of the main storage device 2002 of the host system and using each divided area exclusively as a main storage device of each VM. When such a VM is used, if a constant address displacement α is added to the address of the main storage device of the VM, the main storage device 200 of the host system
It turns out that the address becomes 2. In the case of FIG. 5, VM
The address displacement of ₁ is α ₁ , and the address displacement of VM ₂ is α ₂ . In such a case, the conversion table 2010 for converting the level 2 memory address to the level 1 memory address is 2
As shown in 010 (2), a table for managing the lower limit address and the upper limit address of each VM is sufficient. In this case, the level 2 CCW address conversion is easy, and the entry of the address conversion buffer 3030 for the level 2 CCW (that is, the entry in which the field 3 of the address conversion buffer 3030 is 0) is unnecessary. Instead, the conversion table 2010 (2) shown in FIG.
There is also a method in which the address is converted (level 2 memory address → level memory address conversion) by taking in the local storage in 0 (FIG. 7), finding the address displacement α by VM #, and adding it. VM shown in FIG.
Main storage device 200 is the main storage device 200 of the host system
A fast VM mode is supported for VMs that are either resident at 2 and fixed, or that occupy some contiguous area of the host system's main memory as shown in FIG. In the high-speed VM mode, most privileged instructions issued by the OS on the VM are directly executed (execution method having the same performance as the host system without going through the VMCP).
To be done. However, the IO instruction on the VM requires VMCP intervention, as shown below.

Now, actually, I issued by the OS on the VM
FIG. 6 shows how the O start instruction is executed by the VMCP. The OS on the VM has a sub-channel number (sub-channel #) that corresponds to the input / output device on a one-to-one basis.
Is specified to issue an IO start command. Since this subchannel # is a subchannel # under the VM, it will be called a virtual subchannel #. The VMCP translates this into the corresponding real subchannel #. This correspondence is VM
It is decided when the definition of. The VMCP checks to which level CCW the OS on the VM that has issued the IO activation instruction issued the IO. Usually it is IO
It is indicated by the operand of the start instruction. Level 3C now
It is assumed that the IO start instruction is issued to the CW. Figure 6
Then, the 2810 CCW group is the CCW group on the level 3 memory, and all the data addresses thereof are the level 3 memory addresses. VMCP is CCW generated by this OS
The IO activation instruction is issued to the group 2810 with 2800 operands. The operand 2800 is a field L indicating the level of CCW, and conversion table B when L = 3.
, The segment size SS, and the page size PS are described. further,
The start address RATOR of the conversion table A, its segment size SS, and page size PS are described, and the address to the CCW group 2810 is also described. These are V
Issuing the I / O start command of MCP, I via line 200
It is sent to OP3000 (FIG. 7) and basic information is set in the corresponding sub-channel register 3011. Also, similar basic information is described in the corresponding sub-channel control block in the sub-channel control block group 2090 shown in FIG. 7 (see sub-channel control block 2091 in FIG. 10). Now, the IOP 3000 (FIG. 7) uses the address translation information in this subchannel to generate the C generated by the OS.
As described above, the CW group 2810 is executed while translating the address.

FIG. 7 is a block diagram showing a hardware configuration diagram and IO execution in a conventional VMS. In the CPU 1000, a prefix register 1010 including an area prefix (PSA) address including hardware interrupt information, a control register group 1100 of the CPU, a basic state of the CPU (interrupt control bit, and next execution) A program status word PSW1020 that contains the machine instruction address, etc.). Furthermore, I
O instruction execution circuit 1030, IO interrupt circuit 1040, I
There are an O instruction execution microprogram 1050, an IO interrupt processing microprogram 1060, and the like. Furthermore, as a flag for VMS, v bit indicating the VM mode exists in 1090. During VM running, this bit is set to 1 by VMCP. Further, the high speed VM mode flag H described above is also present in 1090. Other methods can be considered for the VMS control flag 1090.
For example, VMCP mode (hypervisor mode) and V
It is also considered to provide flags of a high-speed VM mode and a general VM mode in the M mode and the VM mode. Since all are the same and different, the conventional example is shown in FIG. Regarding the IOP 3000, as described above, the sub-channel control block group 20
90 and the address conversion information (FIG. 6) contained in the sub-channel register group 3010, the address conversion buffer 3030 is controlled by the microprogram 3020.
Level 3 CC using the information (see Figure 4-3)
W or level 2 CCW (see FIG. 3) is executed. The main memory 2000 of FIG. 7 is divided into a hardware system area HSA 2001 and a programmable area 2002. HSA2001 is CPU10
00 and IOP 3000 includes hardware information, and the area can be accessed and updated by the CPU and IOP microprograms 1050, 1060, and 3020, but the machine is open to general users of the CPU 1000. It cannot be accessed by instruction. The programmable area 2002 can be accessed by the above machine instruction, and this is the OS or VM.
It becomes the main memory area as seen from the CP. In the IO command,
Those associated with the operations of the input / output device such as the start and stop of IO are queued in the IO request queue 2070 in the form of the request queue. The substance is, as shown in FIG. 8, a control block 2071 including an actual subchannel # with an IO request, which is connected by an address pointer. After queuing to the IO request queue, IOP3
An activation signal is sent via line 200 to 000. IOP3
On the 000 side, the IO request queue 207 in the HSA 2001
0 is accessed, the request queue element 2071 is sequentially taken out, and IO request processing is continued. or,
IO interrupts are queued in the IO interrupt request queue 2080 according to actual interrupt priority. The structure is shown in FIG. The interrupt priority is 0, 1, 2, 3, 4, 5, 6,
There are eight types of sub-channel control blocks in the sub-channel control block group 2090 (FIG. 7) when the IO command is issued, and the sub-channel control blocks in the sub-channel control block group 2090 (FIG. 7) are arranged in the order of the real sub-channel #. By this, the existence position can be uniquely obtained. The head address of this sub-channel control block group 2090 is the CPU 100
It is set to one control register in the control register group 1100 of 0 (FIG. 7). The interrupt priority can be specified for each sub-channel. Now, it is assumed that the OS on each VM issues the IO command by designating the sub-channel # and the interrupt priority (one of 0 to 7). At this time, since the VM mode bit 1090 in FIG. 7 is 1, the IO instruction execution μp 1050
Thus, when this bit is 1, control is passed to VMCP. This is the new PSW in the VMCP PSA2100.
As a result, control is passed to VMCP as a kind of interrupt. The PSA address of the VMCP is the VMCP prefix register 1010 (FIG. 7) when the VM is started.
It is set to, so refer to it.

Now, the VMCP looks at the subchannel # specified by the OS on the VM as a virtual subchannel #, converts it into a real subchannel #, manages the state of the real subchannel #, and if possible, If there is, the IO command is issued on behalf of the OS on the VM (by designating the address translation information 2800 shown in FIG. 6).

At this time, the interrupt priority designated by the OS on the VM is the virtual interrupt priority, and the IO instruction is issued with the virtual priority as it is. Therefore, each real interrupt priority is shared between the OSs on the VM. Therefore, each V in the queue of each actual interrupt priority of the IO interrupt request queue 2080 in FIG.
IO interrupt requests from the sub-channels of the OS on M are queued together.

Execution of IO instructions from the OS on the VM
The reasons for CP intervention are as follows.

(I) The virtual subchannel # specified on the OS on the VM must be converted to the real subchannel #.

(Ii) The OS on each VM is the actual subchannel
It may be shared among others, so a sub-channel schedule between them is required.

As described above, of the I / O instructions, the I / O
For those involving operations of the input / output device such as starting and stopping, simulation by VMCP is performed, and the overhead is high.

Next, FIG. 11 shows a method of controlling the IO interrupt. IO interrupt request from each sub-channel is IOP
Detected by 3000, the corresponding sub-channel control block is queued in IO interrupt request queue 2080 (see FIG. 7). As shown in FIG. 9, the structure of the IO interrupt request queue is queued according to the actual interrupt priority. At this time, the bit of the corresponding real interrupt holding register 1042 shown in FIG. 11 is set to 1. Both the bits of the interrupt pending register 1042 and the corresponding bits of the actual interrupt priority mask register 1041 are 1 and the PSW10
When the 20IO mask is 1, the IO interrupt is activated for the corresponding real interrupt priority, and the control is passed to the IO interrupt processing microprogram 1060. The above operation is realized by the hardware circuit shown in FIG.

As described above, in the VMS, since the respective actual interrupt priorities are shared by the OSs on the VM, the actual interrupt priority mask register 10 is kept running during the VM running.
Each bit of 41 is set to a value obtained by ORing the interrupt priority mask values of the OS on each VM or set to 1 so that interrupts are always enabled. Furthermore, in this case, the IO of the PSW1020
The mask is also set to 1. By doing so, when an IO interrupt request from the subchannel causes a certain bit of the actual interrupt pending register 1042 to become 1, the output of one AND gate in the AND gate group 1046 becomes 1, and thus the OR gate 1043. Output becomes 1 and AN
The output of the D gate 1044 becomes 1 and the IO shown in FIG.
The interrupt circuit immediately activates the IO interrupt processing microprogram 1060. The IO microprogram 1060 removes the subchannel queued in the IO interrupt request queue (FIG. 9) on the corresponding real interrupt priority from the queue and reflects the interrupt in the VMCP prefix. At this time, if the interrupt request queue of the actual interrupt priority becomes empty, the bit of the actual interrupt holding register 1042 of the actual interrupt priority is set to 0. This clears the interrupt hold. By reflecting the interrupt in the VMCP, the control is passed to the IO interrupt processing program of the VMCP. At that time, the actual sub-channel # that generated the IO interrupt and the corresponding VM # are also passed to the VMCP as the IO interrupt parameters. The VMCP performs the following processing in order to reflect this IO interrupt in the corresponding VM.

(I) Convert the real subchannel # into a virtual subchannel #.

(Ii) Check the IO priority mask register of the corresponding VM and the IO mask of the PSW, and determine whether or not the IO interrupt is possible.

(Iii) When the corresponding VM can be interrupted,
The interrupt is reflected in the prefix PSA of the VM.

(Iv) When the corresponding VM cannot be interrupted, the VMCP suspends the interrupt.

As described above, in order to share the actual interrupt priority order among VMs, the mask must be set to a value (usually 1) obtained by ORing the corresponding mask values of each VM. For this reason, there may be a case where an interrupt occurs in the VMCP even for a rank that cannot be interrupted by the corresponding VM.
P will hold the IO. Therefore, the IO command for the relevant sub-channel is always V
Simulation with MCP intervention is required.

[0021]

As described above, the OS on the VM in the conventional virtual computer system
In the execution of the IO start instruction of (3), although the function of the direct execution of the level 3 CCW and the level 2 CCW by the IOP exists, the VMCP always intervenes and its simulation is necessary. For this reason, the simulation overhead of VMCP becomes large for a load with a high IO issue frequency. The I / O interrupt generated as a result of such I / O instruction execution has the same problem.

The above problems are caused by the I issued by the running OS.
The same applies to other instructions that do not involve the operation of the I / O device, for example, an instruction to check the presence / absence of a pending I / O interrupt.

It is an object of the present invention to provide an instruction execution method for eliminating the simulation overhead of VMCP for instructions other than the I / O activation instruction, such as the I / O interrupt check instruction.

[0024]

The reason why the VMCP intervenes with respect to the IO instruction and IO interrupt of the OS on the VM is as described in the prior art as follows.

(I) Conversion between virtual subchannel # and real subchannel # is required.

(Ii) A real subchannel may be shared between OSs on a VM, and a subchannel schedule is required.

(Iii) Since the actual interrupt priority order may be shared between VMs, the interrupt control mask must be set to a value obtained by ORing the interrupt control mask values of the OS on each VM. Therefore, the VM's IO interrupt reservation by VMCP must occur. To prevent this, I on the hardware side
In order to hold the O interrupt, an interrupt control mask register for each VM must be prepared, and an interrupt hold register must also be prepared for each VM, resulting in a large amount of hardware. It's too good to be good. In order to solve the above, a preferred embodiment of the present invention adopts the following method.

(I) The VMCP prepares a conversion table from the virtual sub-channel # to the real sub-channel #, and the conversion table is converted by using the IO instruction execution microprogram. (Ii) The VM information area is provided in the real subchannel control block, and the correspondence between the virtual subchannel # and the converted real subchannel # is described therein.

(Iii) V of the actual subchannel control block
A status field is provided in the M information area, and a flag indicating whether or not it is a dedicated subchannel is provided. This flag is VM
It is set when the sub-channel occupancy is designated by the CP, or when the sub-channel occupancy is designated in the VM definition information, when the VM is defined. When this flag is 1, it means that the sub-channel is exclusively used by the VM.
No sub-channel schedule by VMCP is required.

(Iv) By allocating the VM to the actual interrupt priority order, only the sub-channel for which the IO request of the exclusive source VM has been queued in the interrupt request queue at that priority order. Therefore, the mixture of VMs in the actual interrupt priority can be avoided. Further, the exclusive interrupt control mask of the actual interrupt priority order is made to match the value of the corresponding interrupt control mask of the OS on the exclusive source VM. As a result, when the interrupt control mask of the interrupt priority of the OS on the VM cannot be interrupted because it is 0, the corresponding interrupt control mask of the actual interrupt priority is also 0. Therefore, the interruption of the interrupt by the hardware and the interruption of the VM IO by the VMCP can be avoided.

In order to support the above method, the types of actual interrupt priorities will be increased so that the VM can occupy the actual interrupt priorities.

In particular, according to the present invention, even in the case of an I / O interrupt check instruction, if the actual interrupt priority designated by the instruction is exclusive to the running OS that issued the instruction, the instruction is executed. , Directly without VMCP intervention.

[0033]

By directly executing the I / O interrupt search instruction, the simulation overhead due to VMCP can be reduced.

[0034]

EXAMPLES Examples of the present invention will be shown below. FIG. 12 shows an overall view of an embodiment of the present invention.

The respective constituent elements of the CPU 1000 'are the same as those of the conventional example shown in FIG. 7, but some have a slightly larger function. Among the HSA 2001, there is the same one as shown in FIG. 7 of the conventional example. (IO request queue 2070, IO interrupt request queue 2080, real subchannel control block group 2090 '). However, the prefix management table 2300,
The conversion table address management table 2400 and the VM management table 2700 are new information.

Programmable area 2002 is the same as the conventional example shown in FIG. 7 (VMCP PSA 2100, VM
1 PSA 2110, VM2 PSA 2120, other V
M PSAs may be present as well.

There is also a VMCP 2200, a level 2 memory to level 1 memory address conversion table group 2010, and a level 3 memory to level 2 memory address conversion table group 2040). But interrupt priority #
The conversion table 2500 and the sub-channel # conversion table group 2600 are new information. The IOP 3000 'has the same configuration as the IOP 3000 of the conventional example FIG. 7, but has a slightly larger function. First, the HSA2001
The new information included in the programmable area 2002 will be described.

FIG. 13 shows the prefix management table 2300. This is the PSA address of VMCP, the PS of VM1
A address, PSA address of VM2, PSA of VM3
Contains the address. Although only VM3 is shown in FIG. 13, PSA of most VMs may be registered. The address of this PSA is referred to by the μ program of the CPU 1000 ′, and the address of the programmable area 2002 in the host system is described. The PSA address of each VM is given as one of the operands of the start-only instruction when the VM is started, and is stored in the corresponding entry of the prefix management table 2300 when the instruction is processed. This Prefix Management Table 2
The head address of 300 is stored in one of the control register groups 1100 'of the CPU 1000' (see FIG. 12). This prefix management table is optional and not essential. The time when it is used will be described later. Next, FIG. 14 shows the conversion table address management table 2400. This address management table 2400 is a subchannel # conversion table 2
The start address of 600 and the start address of the interrupt priority level # conversion table 2500 are managed for each VM. The start address of the conversion table address management table 2400 is also the control register group 110 of the CPU 1000 '.
It is stored in one of 0 '. The method of searching the sub-channel # conversion table 2600 and the interrupt priority conversion table 2500 is as shown in FIG. That is, the virtual subchannel # (consisting of 2 bytes) is set to D0 · 256 + D1.
First, the table 2601 at the preceding stage indicated by the content of the corresponding entry of the address management table 2400 is searched for by D0. The address of the latter stage table 2602 is set in the D0th entry of the former stage table 2601, and the D1th entry of the latter stage table 2602 is searched. There, the corresponding real subchannel #D
0'.256 + D1 'is obtained. The virtual interrupt priority # is converted into the corresponding real interrupt priority # only by reading the corresponding entry in the conversion table 2500. The sub-channel # conversion table 2600 and the interrupt priority conversion table 2500 are
The VM is created by the VMCP when specified by the VMCP command or when the VM is defined from the VM definition information.
Is specified by the operand of the start-only instruction when
The conversion table address management table 24 during the processing of the activation-only instruction
00 is stored in the corresponding entry. This conversion table 260
0, 2500, and 2400 are also optional and are not essential. In other words, in the VMS, the VM using the IO execution method of the present invention, if the restrictions of virtual subchannel # = real subchannel #, virtual interrupt priority # = real interrupt priority # are kept, No conversion table is required.

FIG. 15 shows the contents of the VM management table 2700. In this, the size (Z
0, Z1, ...) and its address conversion table 201 from the level 2 memory address to the level 1 memory address.
Address 0 (RATOR0, RATOR1, ...) Is described. These pieces of information are obtained from the definition information of the VM, and the HSA is activated by the VM start-up command.
It is stored in the corresponding entry of the VM management table 2700 in 2001. The start address of the VM management table 2700 is also CP
It is stored in one of the control register group 1100 '(see FIG. 12) in U1000'. The start address of the control block in the HSA 2001 is stored in the control register 1100 'in the CPU 1000' as in the conventional case. If the VM that supports the IO execution method of the present invention is limited to the VM that occupies the main storage device 2002 shown in FIG. 5 as the main storage device, the upper and lower limits are defined. The conversion table 2010 (2) described above can be used as a substitute for the VM management table 2700. If the conversion table 2010 (2) of FIG. 5 is used, the upper and lower limit addresses α _i , α _{i + 1} (i = 1, 2, 3
...) is designated by the VM start instruction, and the corresponding entry of the conversion table 2010 (2) is created in the HSA 2001 by the instruction processing. FIG. 16 shows a real sub-channel control block group 2090 ', one real sub-channel control block 2091' in it, and a VM information area 2092 'in it. VM information area 209
2'includes a status field, VM #, virtual subchannel #, corresponding real subchannel #, virtual interrupt priority #, corresponding real interrupt priority #, and CCW address conversion information 2094. . In the status field, there is a flag indicating whether or not this subchannel is occupied and whether or not this subchannel is in the IO direct execution inhibiting mode. The CCW address translation information 2094 has the same contents as the conventional address translation information 2092 (see FIG. 10). The information in the VM information area 2092 'is set from the VM definition information at the time of defining the VM, at the time of designation by the VMCP command, or at the time of processing the IO instruction.

The occupancy of the real sub-channel or the occupancy of the real interrupt priority is designated at the time of defining the VM or by the VMCP command. When this designation is made, the VM information area 209
The following fields in 2'are set.

The sub-channel occupation flag in the status field 2093 The I / O direct execution mode inhibition flag is normally set to 0, and the I / O direct execution mode is set to the supported state.

-VM of exclusive source-Virtual subchannel # and real subchannel # -Address of CCW address conversion information 2094 from main memory (level 2 memory) of the exclusive source VM to level 1 memory Start address of conversion table (RAT
OR (see FIG. 4 (a)) If the exclusive source VM exclusively uses the main storage device shown in FIG. 5, its upper and lower limit α
It is also possible to set _i , α _{i + 1} (i = 1, 2, 3 ...).

In the case of shared subchannels, this information is set during IO instruction processing, if necessary. In this case, it is set in the corresponding field of the VM information area of the IO issuer VM.

FIG. 17 shows an instruction format for activating a VM. 2900 is a VM start command, and 2910 is
That is the operand. In the operand 2910,
The VM #, the PSW of the VM, the PSA address of the VM, the start address of the subchannel # conversion table 2600 (FIG. 14), the interrupt priority # conversion table 2500 (FIG. 1).
4) start address, address conversion table 201 from the main memory of the VM to the main memory of the host system
0 (FIG. 15) start address (RATOR) (FIG. 4
(See (a))), the main storage device size of the VM (this 2
Regarding one, when the VM to be started uses the continuous area of the main storage device 2002 shown in FIG. 5 as the main storage device of the VM, its upper and lower limits α _i , α _{i + 1} (i = 1, 2, ...). ) May be specified. ) Etc. are described. Among these operand information, the running PSW of the VM, the PSA address of the VM, the actual interrupt priority status, and the VMS control flag group are determined at the time of starting the VM, but much other information is described above. As described above, according to the definition information of VM, V
It is determined when M is defined. Real interrupt priority status, real interrupt priority exclusive status, and V
The MS control flag group will be described later. These operands are set by VMCP. The VM activation instruction need not necessarily be in the format shown in FIG. However, the information shown in FIG. 17 is required as an operand. FIG. 18 shows VMS control register group 1080
Represents The register 1081 includes the VM # of the current running VM and is set by the VM start command. The content of this register is the operand 2910 (FIG. 17) of the VM start instruction.
It is given in the content of one field of. FIG. 19 shows
A VMS control flag group 1090 '(see FIG. 12) is shown.
These flags are operands of the VM start instruction (see FIG.
The initial value is given by one field of 7). The meaning of each flag is as follows.

V: 1 when running in VM. It becomes 0 when running in VMCP or when in the real computer mode.

It is set to 1 by a VM start instruction and set to 0 when control is passed to VMCP for indexing or the like. This is the same as the conventional one (FIG. 7).

H: Set to 1 when a privileged instruction can be directly executed in running VM. This flag is 1
, Most of the privileged instructions in running VM are CP
It is directly executed by the instruction execution circuit of U1000 '. H
When = 1 it is called a high speed VM mode. This is also the same as before (see FIG. 7).

R: The OS on the VM is restricted, and 1 is set when the virtual subchannel # = real subchannel # and the virtual interrupt priority # = real interrupt priority # always. When this is 1, all sub-channel # conversion processing and interrupt priority # conversion processing by the μ program are excluded.
(At this time, the conversion tables 2400 and 260 shown in FIG.
0,2500 is unnecessary. D: Direct IO execution of VM (VMCP) enabled by the present invention
It means 1) does not intervene) and is 1 when it is valid. Normally, it is initialized to 1 by the VM start command of VMCP.

N: This flag is characteristic of this embodiment, and the current running VM has an interrupt hold factor related to the shared interrupt priority (actually, the VMCP holds the interrupt for that VM). Yes, if there is a virtual interrupt priority mask of the current running VM that can be interrupted (therefore, the IO mask of the PSW of the VM concerned is 0, so it cannot be interrupted), 1 Set to. This is used at the time of execution of an instruction for checking the IO interrupt request of the VM, which is interruptable with respect to the virtual interrupt priority. This is also initialized by the VMCP by the VM start instruction.

FIG. 20 shows a method of assigning the actual interrupt priority order. Consider 32 types of 0-31 as the actual interrupt priority order. Since the real interrupt priority 0 is the highest priority, it is dedicated to VMCP. From the actual interrupt priority 1 to the ascending order (the interrupt priority order is the descending order), the actual interrupt priority order that the VM exclusively owns is assigned to each exclusive source VM. The shared interrupt priority is assigned to each VM in descending order (interrupt priority is increasing) from the actual interrupt priority 31. In the example in FIG. 20, the virtual interrupt priority 0 of the VM 1 is assigned the real interrupt priority 1 and occupies the virtual interrupt priority 1 and the virtual interrupt priority 1
The actual interrupt priority 31 is assigned to ~ 7, and this is set to V
It will be shared among M. VM2 and VM3 are also allocated as shown in FIG. The virtual interrupt priority order in VM1 is actually divided into two types, 0 and (1 to 7). Therefore, the OS on the VM1 can effectively use two types of actual interrupt priorities. The restrictions on these OSs can be allowed depending on the operation. Which interrupt priority is to be
This is a problem to be decided for each VM under the plan of the entire VMS, and is managed by the VMCP. The exclusive / shared state of the real interrupt priority order thus determined is given by the operand of the VM start instruction (see FIG. 17), and the real interrupt priority order exclusive use status register 1 is processed by the instruction processing.
049 (FIG. 21).

FIG. 21 shows the real interrupt priority mask register 1041 ', the real interrupt pending register 1042', the real interrupt priority status register 1045 and the real interrupt priority exclusive status register 1049. Of these, the registers 1041 'and 1042' are conventional examples (see FIG.
It exists in 1), but the number of bits is increased. In this example, the conventional 8 bits are quadrupled to 3
It is extended to 2 bits. This is the actual interrupt priority V
This is to support the proprietary method in M. Since the meaning is the same, the description is omitted. The meaning of the actual interrupt priority level status register 1045 is as follows. That is, when the bit n (0 to 31) is 0, the actual interrupt priority order n
Indicates that the current running VM is used exclusively. Otherwise, it is set to 1. The contents of the real interrupt priority exclusive use status register 1049 are as follows. That is, when the bit c (0 to 31) is 0, it means that the actual interrupt priority c is occupied by a certain VM.
When 1 is 1, it indicates that the actual interrupt priority c is shared. The registers 1045 and 1049 are initialized by the operand of the VM start instruction. The actual interrupt priority mask register 1041 'is managed and updated by the VMCP. The actual interrupt holding register 1042 'is the IOP 300.
0 '(FIG. 12) and reset by IO interrupt processing microprogram 1060' (FIG. 2).
2).

FIG. 22 shows the IO interrupt circuit 1 according to the present invention.
It is a circuit diagram of 040 '. In this figure, for simplicity,
Although it is written that there are only 10 types of actual interrupt priorities, actually there are 32 types, and the connection at that time is exactly the same. Now, the actual interrupt priority c (c = 0 to 31)
However, a sub-channel having an interrupt request is queued in the queue of the actual interrupt priority level c of the IO interrupt request queue 2080, and the corresponding bit of the pending register 1042 'becomes 1. Suppose).
At this time, when the interrupt priority c is occupied by the current running VM, the actual interrupt priority status register 1045
Since the corresponding bit of is 0, the OR gate group 10
At the output of 48, the IO mask value of PSW appears, so P
The IO interrupt mask of SW1020 becomes effective. Therefore,
Only when the corresponding bit 1 of the corresponding real interrupt priority mask register 1041 'indicates that the IO mask of PSW is 1
The corresponding output of the D gate 1047 becomes 1 and the IO interrupt is activated, and the control is passed to the IO interrupt processing microprogram 1060 '. Interrupt priority c is shared or other V
In the case of being exclusively used by M, since the corresponding bit of the register 1045 is 1, the corresponding output of the OR gate 1048 becomes 1 and becomes irrelevant to the IO mask of the PSW 1020, and the corresponding real interrupt priority mask register 104
If the 1'bit is 1, an IO interrupt is activated.
After the interrupt processing by the microprogram 1060 ', if the interrupt request queue of the interrupt priority c becomes empty, the corresponding bit of the holding register 1042' is cleared to 0 by the microprogram.

Now, using the hardware and microprograms described above and the information on the main memory,
The following is a step-by-step description of how IO commands and IO interrupts of the OS on the YM are processed.

The VM is set to the high-speed VM mode on the premise of the following two points.

(I) The entire main memory of the VM is assumed to be resident in the main memory of the host system.

(Ii) IO direct execution of OS on VM (VM
The CP execution method without intervention, including direct execution of IO interrupts) is supported only for the dedicated sub-channel and the sub-channel having the dedicated interrupt priority.

First, when the VMCP is started up, the VMCP shown in FIG.
In addition to the setting of the operand of the VM start instruction, the bit c of the real interrupt priority mask register 1041 'is set as follows (FIG. 21).

When the actual interrupt priority c (0 to 31) is occupied by the current running VM, the virtual interrupt priority of the OS on the corresponding VM (assuming there is only one for the sake of simplicity) The same applies hereinafter) is set in bit c.

When the interrupt priority c is occupied by another VM, the logical product of the mask value of the corresponding virtual interrupt priority of the VM and the IO mask value of the PSW of the VM is calculated.
Set to bit c. Alternatively, the bit c may be set to 0 even when the delay of the interrupt having the interrupt priority level c does not matter.

When the interrupt priority c is shared between VMs, 1 is set in the bit c.

Even if the virtual interrupt priority mask is changed while the VM is running, the change is immediately reflected in the real interrupt priority mask register 1041 '(FIG. 21).
Therefore, the virtual interrupt priority mask value change instruction of the OS can be necessarily simulated through the VMCP, or the change is stored in the register 1041 ′ by the μ program processing of the CPU. It may be reflected. It is the same as before. When activating a VM in the high-speed VM mode, FIG. 17 shows the operand V of the VM activation instruction.
The PSW of the VM itself is set as the PSW for M traveling, and this is the PSW 1020 of the CPU 1000 'as it is.
(FIG. 12). Therefore, the PSW IO mask is made to match the running VM IO mask. Immediately after changing the PSW of the OS while running the VM, the PSW10
This matching condition is satisfied as reflected in 20. Therefore, by directly executing the PSW change command of the OS,
It may be reflected in the PSW 1020 of the CPU 1000 ', or may be reflected in the simulation via the VMCP. This is the same as before, after the above settings are completed, the OS on the VM is issued by the VM start command (Figure 17).
Control is passed to. Execution of this instruction causes the PS of the current running VM # register 1081 and CPU 1000 'of FIG.
W10210 (FIG. 12), corresponding entry in FIG. 13 prefix management table, translation table address management table 2 in FIG.
The corresponding entry of 400, the corresponding entry of the VM management table of FIG. 15, the actual interrupt priority status register 10 of FIG.
45, the VMS control flag group of FIG. 19 is initialized.

Now, it is assumed that an IO command is issued from the OS on the VM. IO execution circuit 103 of CPU 1000 '
0'performs the following processing under the control of the microprogram 1050 '.

(1) When not in the high-speed VM mode (VMS
The control flag H = 0 (see FIG. 19) is indexed to VMCP.

At this time, by using the prefix register 1010 of the VMCP and reflecting the interrupt in the PSA 2100 of the VMCP, it is indexed to the VMCP (FIG. 1).
2).

(2) In the high-speed VM mode (VMS control flag H = 1), it is determined whether or not the IC direct execution mode of VM (whether VMS control flag D = 1). (Fig. 1
9).

(3) When D = 0, index to VMCP.

(4) When D = 1, VMS control flag R
To judge. When R = 0, the corresponding virtual subchannel # conversion table 2600 is searched and the given virtual subchannel # is converted to the real subchannel #. If the virtual interrupt priority # is given in the instruction operand, the interrupt priority # conversion table is searched and the actual interrupt priority #
Convert to. With this, the real interrupt priority order exclusive use status register 1049 determines whether it is exclusive and writes it in the status field of the VM information area 2092 'of the sub-channel control block (FIG. 16).

The correspondence between the virtual interrupt priority level # and the real interrupt priority level # is written at this time. When R = 1, no conversion is necessary, so the same value is written.

(5) When the obtained real sub-channel control block 2091 '(FIG. 16) is a dedicated sub-channel and has a dedicated interrupt priority, the IO instruction is executed. From this point onward, the process is the same as in the real computer system. If an asynchronous IO device operation is required, I
The sub-channel is queued in the O request queue 2070 (FIG. 8). Control is returned to the IO issuer along with the condition code.

(6) If the obtained real subchannel is a shared subchannel or the interrupt priority is shared, VMCP
Index and entrust it to the simulation.

(7) An IO instruction issued by the OS on the VM issues an IO interrupt request that can be interrupted in each virtual interrupt priority order (meaning that the virtual interrupt priority mask of the OS can be interrupted). In the case of an instruction to be inspected, it is processed by a method characteristic of this embodiment as follows. That is, first, the current running VM checks the interrupt request regarding the actual exclusive interrupt priority order. At that time, if there is no IO interrupt request, it is necessary to check the shared interrupt priority, but since the VMCP manages all interrupt reservations related to the shared interrupt priority,
The need arises to pass control to the VMCP. However, since it violates the purpose of direct execution, the control flag N (FIG. 19) of the VMS is used. When N = 1, it means that the VMCP manages the IO interrupt pending (shared interrupt priority and virtual interrupt priority can be interrupted). Therefore, in this case, VMCP It will be indexed to. When N = 0, there is no IO interrupt pending, so V
There is no need to index to the MCP, and direct execution is possible.

Next, the IO interrupt processing will be described.

(1) The IO interrupt request from the IO device is I
The corresponding real sub-channel control block detected by OP3000 'is queued at the corresponding real interrupt priority of the IO interrupt request queue 2080 in the HSA 2001. (See Figure 9). This is the same as before.

(2) At this time, IOP3 shown in FIG.
000 'sets the corresponding bit of the real interrupt pending register 1042' to 1. This is the same as before.

(3) Actual interrupt priority mask register 10
41 'is set as described above. The operation method of the IO interrupt circuit in FIG. 22 is as described above. From this, it is assumed that the IO interrupt is activated and the control passes to the IO interrupt processing microprogram 1060 '.

(4) At this time, when the real interrupt priority order in which the interrupt is activated is made exclusive, the setting method of the real interrupt priority mask register 1041 'and the real interrupt priority status register 1045 causes The proprietary VM is
Regarding the corresponding virtual interrupt priority order, it is inevitable that interrupts will be possible. If the exclusive VM is not interruptable, the IO interrupt of the PSW 1020 and the registers 1041 'and 1045 do not activate the IO interrupt, and the control becomes 106.
It is never passed to 0 '. That is, it remains reserved by the hardware.

(5) IO interrupt μ program processing 106
0'performs the following processing.

(I) Actual interrupt priority c which generated an interrupt
The actual subchannel of the IO interrupt request queue 2080 (FIG. 9) above is removed from the queue.

(Ii) VMS control flag 1090 '(see FIG. 1)
Looking at the VM mode flag bit V and the high-speed VM mode flag H in 9), when V = 0, the interrupt is reflected in the PSA of the VMCP. In this case, VMCP P × R1010
(FIG. 12) is used.

(Iii) When V = 1 & H = 1, I of VM
O Direct execution mode Look at the D bit. When D =, since it is not the IO direct execution mode, the interrupt is reflected in the PSA of VMCP.

(Iv) When D = 1, the following processing is performed.

(B) From the status field (FIG. 16) in the actual sub-channel control block, it is judged whether the sub-channel is occupied or not.
Reflect the interrupt to SA.

(B) When the actual interrupt priority c which is generating an interrupt is occupied by the current running VM, that is, when the corresponding bit of the actual interrupt priority status register 1045 is 0 (FIG. 21). (Refer to), the interruption is reflected in the PSA of the current running VM, and the current running VM is continued. At this time, the VM prefix register 1070 (FIG. 12) is used. The IO interrupt information to the VM prefix reflects the virtual subchannel # or the virtual interrupt priority # in the real subchannel control block 2092 'as the interrupt information.

(C) When the actual interrupt priority c is occupied by another VM, the interrupt is reflected in the VMCP.

Then, the PS of the corresponding VM is set by VMCP.
Reflect the interrupt to A.

(D) When the real interrupt priority c is shared, the interrupt is reflected in the VMCP. After this, VMC
By P, the interruption is reflected in the corresponding VM,
In this case, there is a possibility that the relevant VM cannot be interrupted, and in that case, the VMCP suspends the IO interrupt.

As described above, when the sub-channel is occupied and has the occupied real interrupt priority,
Direct execution of the IO of the OS on the VM (execution without VMCP intervention) is supported for the sub-channel. In the case of IO interrupts, more precisely, the IO interrupts from the subchannels occupied by the current running VM are directly executed. With respect to IO interrupts from sub-channels occupied by other VMs, the need for inter-VM scheduling causes the VMCP to intervene.

The IO direct execution mode inhibition flag of the status field 2093 in the real subchannel control block of FIG. 16 is normally 0, and the IO direct execution mode of the subchannel is supported. However, in the case of the dedicated sub-channel, the IO command is not issued from the OS on the VM other than the exclusive source VM, but the IO command can be issued from the VMCP. At this time, the I / O direct execution mode inhibition flag in the status field 2093 is set to 1 until the I / O of the VMCP is completed even for the dedicated sub channel, and the IO direct execution mode of the sub channel is set. Be placed in a restrained state.

Therefore, this flag is set / reset in the VMCP management. I above
The following can be said with respect to the O execution method.

(A) In the VMS control flag group 1090 '(FIG. 19), the R bit may be omitted. That is, the conversion of the virtual subchannel # and the conversion of the virtual interrupt priority # are always performed, or when the IO direct execution method of the present invention is applied in the operation of VMS, the It is unnecessary if we assume that the values of are equal.

(B) Similarly, a method of substituting the H flag for the D flag can be considered, but the high speed VM mode flag H is
Since it also controls whether or not a privileged instruction other than the IO instruction can be directly executed, it becomes impossible to control whether or not only the IO instruction can be directly executed.

(C) In the processing of the IO interrupt, the IO interrupt from the actual interrupt priority which is exclusively used by the VM other than the current running VM has been described above so as to be reflected in the VMCP. Since the VM can be interrupted, the PSA of the VM is first reflected in the interrupt, and then the VMCP is changed to the VM.
Control may be passed in the form of a CP call. That V
The MPSA address can be obtained from the prefix management table in FIG. In this case,
A method for obtaining the PSW of the VM is required and information for that is required. However, since there are various possible methods based on the VM #, illustration thereof is omitted.

(D) Subchannel # conversion table start address, interrupt priority # conversion table start address, actual interrupt priority status register 1045, actual interrupt priority exclusive status register 1049 (FIG. 21) are all Although the initialization is performed by the operand of the VM activation instruction (see FIG. 17), the initialization may be performed by a dedicated instruction of VMCP.

[0094]

As described above, according to the present invention, V
It is possible to directly execute the IO interrupt inspection instruction issued from the OS on the M, and it is possible to significantly reduce the IO simulation overhead of VMCP.

[Brief description of drawings]

FIG. 1 is a block diagram of a real computer system using a normal OS.

FIG. 2 is a block diagram of a conventional virtual machine system (VMS).

FIG. 3 is an explanatory diagram showing a memory hierarchy in a conventional virtual machine (VM).

FIG. 4 is an explanatory diagram showing address conversion tables.

FIG. 5 is a configuration diagram of a VM that occupies a continuous area of an actual main storage device.

FIG. 6 is an explanatory diagram showing IO commands issued by the VMCP for VM IO simulation.

FIG. 7 is a block diagram of a host system.

FIG. 8 is an explanatory diagram showing an IO request queue.

FIG. 9 is an explanatory diagram showing an IO interrupt request queue.

FIG. 10 is an explanatory diagram of an actual sub-channel control block group.

FIG. 11 is a diagram showing an IO interrupt circuit.

FIG. 12 is a configuration diagram of a host system according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating a prefix management table.

FIG. 14 is a diagram illustrating a conversion table address management table.

FIG. 15 is a diagram illustrating a VM management table.

FIG. 16 is an explanatory diagram of an actual sub-channel control block group.

FIG. 17 is a diagram showing a VM start instruction.

FIG. 18 is an explanatory diagram of a VMS control register group.

FIG. 19 is a diagram showing a VMS control flag group.

FIG. 20 is an explanatory diagram of an interrupt priority assignment method.

FIG. 21 is an explanatory diagram of a VMS interrupt control register.

FIG. 22 is an explanatory diagram of a VMS IO interrupt circuit.

[Explanation of symbols]

10000 ... Real computer system, 1000 ... CPU, 1
000 '... CPU, 1000-N ... CPUNN N = 1,
2, 3, ..., 1010 ... Prefix register PXR of VMCP, 1020 ... Program status word PS
W, 1030 ... IO instruction execution circuit, 1040 ... IO interrupt circuit, 1050 ... IO instruction execution microprogram μ
P1, 1060 ... IO interrupt processing microprogram μ
P2, 1070 ... VM PXR, 1080 ... VMS control register group, 1090 ... VMS control flag group, 1100
... Basic control register group, 1030 '... IO execution circuit, 1
040 '... IO interrupt circuit, 1050' ... IO instruction execution microprogram, 1060 '... IO interrupt processing microprogram, 1100' ... Basic control register group, 1
110 ... A register including a level 2 → level 1 address conversion table start address, 1120 ... A register including a level 3 → level 2 address conversion table start address,
1041 ... Real interrupt priority mask register, 1041 '
... actual interrupt priority mask register, 1042 ... actual interrupt pending register, 1042 '... actual interrupt pending register, 104
3 ... OR gate, 1044 ... AND gate, 1081 ...
Current running VM # register, 1045 ... Actual interrupt priority order status register, 1046 ... AND gate group, 104
6 '... AND gate group, 1047 ... AND gate group, 1
048 ... OR gate group, 1049 ... Actual interrupt priority order exclusive status register, 2000 ... Main storage device, 2000
-N ... VM-N main memory (N = 1, 2, 3 ...) 2001 ... Hardware system area in main memory 2000, 2002 ... Programmable area in main memory 2000, 2010 ... Level Address conversion table from 2 memories to 1 level memory, 2010 (1)
... Adlay conversion table from level 2 memory to level 1 memory, 2010 (2) ... Address conversion table from level 2 memory to 1 level memory, 2020 ... level 1
CCW made by memory address, 2030 ... Level 2
CCW made with memory address, 2040 ... Level 3
Address conversion table from memory to level 2 memory,
2050 ... CCW made with level 3 memory address,
2060 ... 208 request queue, 208 belonging to level 3 memory in virtual space generated by OS on VM
0 ... IO interrupt request queue, 2090 ... Subchannel control block group, 2090 '... Subchannel control block group, 2100 ... VMCP prefix PSA, 211
0 ... PSA of VM1, 2120 ... PSA of VM2, 21
30 ... PSA of VM3, 2200 ... Resident area of VMCP, 2300 ... Prefix management table, 2400 ... Conversion table address management table, 2500 Interrupt priority order # conversion table group, 2600 ... Subchannel # conversion table group, 270
0 ... VM management table, 2800 ... CCW prepared by VMCP
Conversion information, 2810 ... CCW group prepared by OS on VM or VMCP, 2091 ... Subchannel control block,
2091 'Sub-channel control block, 2092 ... Address translation information in sub-channel control block, 209
2 '... Address translation information in subchannel control block, 2071 ... IO request queue queue element, 26
01 ... Pre-stage table of subchannel # conversion table, 2602
... Sub-channel # conversion table post-stage table, 2093 ... Status field in VM information area 2092 'in sub-channel control block, 2094 ... CCW in VM information area
Address conversion information, 2900 ... VM start instruction, 2910
... Operand of VM start instruction 3000 ... Input / output processor IOP, 3000 '... Input / output processor IOP, 3
000-N ... VM-N IOP (logical), 31
10 ... Sub-channel register group, 3010 '... Sub-channel register group, 3020 ... Microprogram μP3 for executing IO, 3030 ... Address conversion table in IOP 3000, 3011 ... One sub-channel register, 4000 ... Input / output control unit IOC, 4000-N
... VM-N (N = 1,2,3 ...) IOC, 100 ... C
PU-main memory interface, 110 ... CPU-
Hardware system area 2001 interface, 120 ... CPU-programmable area 2002 interface, 200 ... CPU-IOP interface, 300 ... IOP-main memory interface, 310 ... IOP-hardware system area 20
01 interface, 320 ... IOP-programmable area 2002 interface, 400 ... IOP-
Inter-IOC interface.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Sato 1 Horiyamashita, Hadano-shi, Kanagawa Hiritsu Manufacturing Co., Ltd. Kanagawa Plant (72) Inventor Hideo Sawamoto 1st Horiyamashita, Hadano, Kanagawa Hitate Manufacturing Co., Ltd. Kanagawa factory

Claims (3)

[Claims] 1. A computer that runs in parallel a plurality of operating systems (OS) under the control of a control program, a plurality of I / O devices, and an I / O instruction executed by the computer. / O
I / O processing execution means for executing processing to one of the plurality of I / O devices asynchronously with execution of instructions by the computer. A plurality of sub-channels representing one of the I / O devices of each of the I / O devices are assigned to the plurality of OSs, and each I / 0 device has at least one of the plurality of sub-channels for at least one of the plurality of OSs. And a plurality of real interrupt priorities are assigned to the plurality of sub-channels, and at least one of the plurality of real interrupt priorities is used exclusively by one of the plurality of OSs, The plurality of real interrupt priorities are pre-assigned to the plurality of sub-channels, and the computer determines whether there are pending interrupts issued by the running OS to be processed by the OS. Respond to the instruction To, whether the interrupt with a real interruption priority used exclusively in the OS is pending,
A circuit for discriminating without requiring discrimination by the control program, and when it is discriminated that there is a pending interrupt, the interrupt is taken as the execution result of the instruction and the running OS is executed.
Computer system having means for notifying the user. 2. The computer is provided with information indicating whether or not an interrupt having at least one real interrupt priority shared by the running OS and another OS is put on hold by the control program, The register set by the control program and at least one real interrupt shared by the running OS and another OS when the determination circuit determines that there is no pending interrupt. Claims further comprising means for notifying the running OS that there are no pending interrupts to process when the priority interrupt indicates that it has not been put on hold by the control program. The computer system according to item 1. 3. The computer has priority of at least one real interrupt in which the register is shared by the running OS and another OS when the judging circuit judges that there is no pending interrupt. The computer system according to claim 2, further comprising means for interrupting the control program and requesting a simulation of the instruction when the interrupt having the order indicates being held by the control program.