JPH07115592A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent distortion in a waveform of a video signal. CONSTITUTION:An H driver 4 driving a horizontal transfer section H of a CCD image sensor 1, a sample-and-hold circuit 21 receiving an output of the CCD image sensor 1 and a clamp circuit 22 are activated continuously in response to a start trigger. An S driver 3 driving a storage section S is driven in response to an output control pulse to extract video information only for a period commanded by a pulse generating circuit 25. When the sample-and-hold circuit 21 and the clamp circuit 22 are operated continuously, the video information is received to conduct proper signal processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a still camera suitable for obtaining image information captured by a computer or the like.

[0002]

2. Description of the Related Art It is well known that an image scanner that scans and reads a subject original is used when capturing image data into a device such as a computer. In recent years, a still camera that can handle a three-dimensional subject has been used. It is also considered to be used. This still camera comprises, for example, a CCD image sensor and its drive circuit,
A drive circuit responsive to an instruction from the computer is configured to transfer and output the information charges accumulated in the image pickup section of the CCD image sensor to obtain a video signal corresponding to the subject video.

FIG. 4 is a block diagram showing the structure of a still camera, and FIG. 5 is a timing chart for explaining its operation. The frame transfer type CCD image sensor 1 includes an image pickup section I, a storage section S, a horizontal transfer section H, and an output section D. The image pickup section I is composed of a plurality of shift registers which are continuous in the vertical direction and are arranged in parallel with each other, and each bit of these shift registers is potential-divided by the action of electrodes to define a plurality of light-receiving pixels. . The storage unit S is
The shift register of the image pickup unit I is composed of a plurality of continuous shift registers, and receives and accumulates the information charges from the shift register of the image pickup unit I. The horizontal transfer unit H is composed of a single shift register in which each bit is associated with the output terminal of the shift register of the storage unit S, and sequentially transfers and outputs the information charges received from the storage unit S. The output section D is provided on the output side of the horizontal transfer section H and converts the information charges output from the horizontal transfer section H into a voltage value and outputs the voltage value. The image pickup unit I, the storage unit S, and the horizontal transfer unit H of the CCD image sensor 1 have a V driver 2, an S driver 3, and an H driver 4, respectively.
Are connected. These V driver 2, S driver 3 and H driver 4 operate according to a common reference clock,
The four-phase transfer clocks φ _V and φ _S are supplied to the imaging section I and the storage section S, and the two-phase transfer clocks φ _H are supplied to the horizontal transfer section H, respectively. CCD image sensor 1
The CCD output taken out from the output section D is input to a signal processing circuit typified by a sample hold circuit 5 and a clamp circuit 6 and subjected to predetermined processing, and then output as an image signal to an external device. The timing control circuit 7 is activated in response to the activation trigger supplied from the external device side that receives the video signal, determines the operation timings of the V driver 2, the S driver 3 and the H driver 4, and the sample hold circuit 5 and the clamp. A sampling pulse and a clamp pulse are supplied to the circuit 6.

Transfer clock φ applied to the image pickup section I
_As shown in FIG. 5, _V has a discharge clock that discharges the information charges accumulated in each light receiving pixel of the image pickup unit I and a read clock that transfers the information charges to the image pickup unit I at the timing according to the activation trigger. . As a result, the exposure period of the CCD image sensor 1 is set in the period from the discharge clock to the read clock. That is, in the CCD image sensor 1 that constantly receives light, after the information charges accumulated in the image pickup unit I are discharged and reset, the newly accumulated information charges are transferred and output after a predetermined period has elapsed. Thus, the exposure period (shutter speed) of the still camera is set. Regarding the setting of the exposure period, for example, Japanese Patent Application No. 1-157369 or Japanese Patent Application No. 1-157369 by the present applicant.
No. 183976. The information charges generated and accumulated in the image pickup unit 2 during the exposure period are instantaneously transferred from the image pickup unit I to the storage unit S by the read clock. The transfer clock φ _S applied to the storage unit S has a one-shot line feed pulse generated at a constant cycle, and the information charges of the storage unit S are transferred to the horizontal transfer unit H in units of one horizontal line by this pulse. To be done. The transfer clock φ _H applied to the horizontal transfer unit H is synchronized with the line feed pulse applied to the storage unit S, has a read clock of the number of clocks corresponding to the number of bits of the horizontal transfer unit H, and The information charges are transferred to the output unit 5 side each time.

The sampling pulse supplied to the sample hold circuit 5 synchronizes with the transfer clock φ _H of the horizontal transfer section H and samples the CCD output taken out from the output section D bit by bit. The clamp pulse supplied to the clamp circuit 6 is also synchronized with the transfer clock φ _H and fixes the reference level set at the end of each horizontal scanning period to a predetermined value.

In the case of the above still camera, until the image pickup instruction is issued from the external device side which receives the video signal,
Each part stops operating and is in a standby state. And
When an imaging instruction (starting trigger) is given from the external device side, one screen of information charge is accumulated in the imaging unit I in a predetermined exposure period, and the information charge is transferred and output to form a screen image. Output a signal. The output of the video signal is continuously performed in each horizontal scanning period, and is completed in one vertical scanning period.

[0007]

The clamp circuit 6 is composed of a switch 10, a capacitor 11, a transistor 12 and a resistor 13, as shown in FIG. The change is superposed on the clamp voltage V _C given through the switch 10, and the output is obtained from the transistor 12 connected to the emitter follower. In such a clamp circuit 6, when the switch 10 is turned off and the standby state is maintained, the voltage on the output side becomes lower than the clamp voltage V _{C due} to the leak current of the capacitor 11, the base current of the transistor 12, and the like. When a video signal is input in this state, the rise of the voltage on the output side is delayed, and the output waveform is distorted as shown in FIG.

Therefore, if the still camera waits until the external device is ready to capture a video signal for one screen, the external device may capture a video signal having a distorted waveform. Therefore, the present invention provides a still camera (solid-state imaging device) that operates in response to an instruction from an external device.
The purpose is to prevent signal distortion at the time of rising.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light-receiving pixels are arranged in a matrix and correspond to an image of a subject to be illuminated. A solid-state image sensor for accumulating information charges generated by the light-receiving pixels in each light-receiving pixel; Second transfer means for transferring and outputting the information charges of the storage section in units of one horizontal line, and activating the first transfer means in response to a first instruction supplied from the outside, and further for a second instruction. In response to the control means for activating the second transfer means, and for the output taken out from the solid-state imaging device in the continuous operation state before the second transfer means starts the transfer of the information charges. As a standard for video information The in that and a clamp circuit for fixing to predetermined level.

[0010]

According to the present invention, while the information charge is stored in the storage section of the solid-state image pickup device, the clamp circuit outputs no signal while waiting to respond to the second instruction from the external device. Since the operation is continuously performed without taking in the voltage, the voltage on the output side of the clamp circuit is always maintained at the clamp voltage. Therefore, when the CCD output from the solid-state image sensor is captured by the clamp, the clamp voltage of the clamp circuit is always maintained at an appropriate value, and even for the output extracted from the solid-state image sensor after a long standby state, The clamp circuit operates normally and outputs a video signal without distortion.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a solid-state image pickup device of the present invention which constitutes a still camera, and FIG. 2 is a timing chart for explaining its operation. In this figure, the CCD image sensor 1 and each of the drivers 2, 3 and 4 are the same as those in FIG. 4, and in response to an instruction from the timing control circuit 20, the information charges accumulated in the image pickup section I are stored in the storage section S. After being transferred
It is configured to be transferred from the storage section S to the output section D via the horizontal transfer section H in units of one horizontal line.

A feature of the present invention is that the sample hold circuit 2 receives the output of the CCD image sensor 1.
1. The signal processing circuits such as the clamp circuit 22, especially the clamp circuit 22 is to be operated before the S driver 3. Further, the clamp circuit 22 is operated continuously even when the S driver 3 operates intermittently. The timing control circuit 20 includes an H counter 23, a decoder 24, and a pulse generation unit 25, and responds to a start trigger supplied from an external device, to each of the drivers 2, 3, 4, and 4.
The operation timing is determined, and the sampling pulse and the clamp pulse are supplied to the sample hold circuit 21 and the clamp circuit 22. The H counter 23 is counted by a clock having a constant cycle, and is reset when the count value reaches a value corresponding to one horizontal scanning period, and a new counting operation is started. The decoder 24 takes in the count value of the H counter 23 and gives the decoded value to the pulse generator 35. At the same time, the decoder 24 gives a reset instruction to the H counter 23. Then, the pulse generator 25 responds to the activation trigger by the timing of vertical scanning of the CCD image sensor 1,
That is, the activation timing of the V driver 2 is determined, and the horizontal scanning timing based on the decode value of the decoder 24,
That is, the activation timing of the S driver 3 and the H driver 4 is determined. Here, the pulse generator 25 and the S driver 3
Between the gate circuit 2 and the gate circuit 2 that opens and closes in response to the output control pulse supplied from the external device side together with the activation trigger.
6 is provided and is configured to transfer the information charges from the storage section S to the horizontal transfer section H and output the video information only when the video signal can be taken in by the external device.

When the activation trigger is given, the pulse generation section 25 first activates the V driver 2 to transfer the information charges of the image pickup section I to the storage section S. At the same time, a timing pulse of a horizontal scanning period for driving the S driver 3 and the H driver 4 is generated, but at the beginning, since the gate circuit 26 is closed, the timing pulse is supplied only to the H driver 4. Therefore, while the S driver 3 is stopped, the H driver 4 is driven without taking in information charges. Further, the pulse generation circuit 25 synchronizes with the operation timing of the H driver 4 to generate a sampling pulse,
Generates clamp and blanking pulses. As a result, even when the information charges are not transferred and output from the storage section S, the output section D of the CCD image sensor 1, the sample hold circuit 21 and the clamp circuit 22 continuously operate at a predetermined timing, and the CCD that does not include video information is included. A predetermined process is applied to the output to output a video signal.

The output control pulse is supplied at a timing different from the activation trigger, and the external device can receive the video signal after the information charge of the image pickup section I is transferred to the storage section S in response to the activation trigger. When the state is reached, the gate circuit 26 is opened to input the timing pulse to the S driver 3. While the gate circuit 26 is open, the timing pulse of the horizontal scanning period generated by the pulse generating circuit 25 is input to the S driver 3, so that the S driver 3 is activated in the horizontal scanning period and the information of the storage unit S is stored. The charges are transferred to the horizontal transfer unit H one horizontal line at every horizontal scanning period. Since the horizontal transfer section H continuously operates regardless of the output control pulse, when the information charge is transferred from the storage section S to the horizontal transfer section H, the information charge is immediately transferred to the output section D side. Is output. Therefore, image information is superimposed on the CCD output from the CCD image sensor 1 while the gate circuit 26 is open in response to the output control pulse.

In the above signal processing circuit, when the driving of the CCD image sensor 1 is started and the image information is taken out, the sample hold circuit 21 and the clamp circuit 22 are already in continuous operation, that is, the clamp circuit. The output side of 22 is maintained at the clamp voltage, and an appropriate reference level fixing process is performed on the video signal.

FIG. 3 shows a CCD according to the operation of an external device.
FIG. 6 is a timing chart showing an operation when the image sensor 1 is intermittently driven and a video signal for one screen is output in plural times. In an external device such as a computer that receives a video signal, a CPU that executes an operation program for signal processing, as shown in FIG.
Various processes such as screen display are repeated intermittently. Therefore, on the external device side, the period in which the operation of the CPU is interrupted is set as the image data transfer period, and an output control pulse for opening the gate circuit 26 is generated within that period. When the gate circuit 26 is opened in response to the output control pulse, the line feed pulse is applied to the storage section S at the timing synchronized with the operation of the horizontal transfer section H, so that the information charge in the storage section S is 1 horizontal. Each line is transferred to the horizontal transfer unit H.

On the other hand, the H driver 4, the sample hold circuit 21, and the clamp circuit 22 are continuously operated at a predetermined timing regardless of the output control pulse, as shown in FIG. Therefore, the information charges transferred from the storage section S to the horizontal transfer section H in response to the output control pulse are transferred as they are to the output section D side, and the sample hold circuit 21 is output from the output section D as a video signal. Given to. Therefore, as shown in FIG. 3, the video signal supplied to the external device has the video information superimposed only during the horizontal scanning period instructed by the output control pulse. The video information intermittently taken out in units of several lines is sequentially stored on the external device side, and a reproduction screen is formed when one screen is completed.

As described above, if the CCD image sensor 1 is driven intermittently in accordance with the operation of the external device side, the operation of the computer for fetching the video signal is not disturbed and the video information is efficiently transferred to the external device. become able to.

[0019]

According to the present invention, by fixing the clamp circuit to the operating state before the image information is taken out from the CCD image sensor, a proper reference level fixing process for the CCD output is performed. Therefore, the distortion of the waveform of the video signal can be prevented in the still camera that operates in units of one screen.

Further, even when the video information is intermittently taken out in accordance with the operation of the external device which receives the video signal, by continuously operating the circuit of the signal processing system, stable signal processing can be always performed, and distortion can be prevented. It is possible to supply a video signal with less noise to the external device side.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device of the present invention.

FIG. 2 is a timing diagram illustrating a first operation of the solid-state imaging device of the present invention.

FIG. 3 is a timing diagram illustrating a second operation of the solid-state imaging device of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional solid-state imaging device.

FIG. 5 is a timing diagram illustrating the operation of the conventional solid-state imaging device.

FIG. 6 is a circuit diagram of a clamp circuit.

FIG. 7 is a waveform diagram of a video signal output from the clamp.

[Explanation of symbols]

 1 CCD image sensor 2 V driver 3 S driver 4 H driver 5, 21 Sample and hold circuit 6, 22 Clamp circuit 7, 20 Timing control circuit 23 H counter 24 Decoder 25 Pulse generator 26 Gate circuit

Claims (2)

[Claims] 1. A solid-state image sensor in which a plurality of light-receiving pixels are arranged in rows and columns, and information charges generated corresponding to an image of a subject to be illuminated are accumulated in each light-receiving pixel, and in each light-receiving pixel of the solid-state image sensor. First transfer means for transferring the information charge of the storage section to the adjacent storage section in a unit of one screen, second transfer means for transferring and outputting the information charge of the storage section in a unit of one horizontal line, and the second transfer section supplied from the outside. 1 in response to the instruction of 1
Control means for activating the second transfer means in response to a second instruction, and a continuous operation state before the second transfer means starts the transfer of the information charges. A solid-state imaging device, comprising: a clamp circuit that fixes a reference level of video information to a predetermined level with respect to an output extracted from the solid-state imaging device. 2. A solid-state image sensor in which a plurality of light-receiving pixels are arranged in rows and columns, and information charges generated corresponding to an image of an object to be illuminated are accumulated in each light-receiving pixel, and in each light-receiving pixel of the solid-state image sensor. First transfer means for transferring the information charge of the storage section to the adjacent storage section in a unit of one screen, second transfer means for transferring and outputting the information charge of the storage section in a unit of one horizontal line, and the second transfer section supplied from the outside. 1 in response to the instruction of 1
Control means for activating the second transfer means in response to the second instruction supplied intermittently, and the second transfer means starts the transfer of the information charges. A clamp circuit that is in a continuous operation state from the end to the completion and that fixes a reference level of video information to a predetermined level with respect to an output extracted from the solid-state imaging device,
A solid-state imaging device comprising: