JP2001061094A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize focus control adaptable to a high-speed operation while suppressing the cost. SOLUTION: Information charges are selectively extracted from a solid-state image pickup device 11 while interleaving to provide the output of a 1st image signal x(t) in which the information quantity is reduced. The 1st image signal x(t) is obtained twice by changing the position of a lens 17 and the optimum position of the lens 17 is decided on the basis of a difference between the 1st image signals x(t). Then after the solid-state image pickup device 11 stores information charges for a prescribed period, a shutter 19 is closed to shut the light to the solid-state image pickup device 11. Then the information charges are read in a prescribed sequence from the solid-state image pickup device 11 to obtain an image signal X(t) to display a photographed image.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device having an automatic focusing function.

[0002]

2. Description of the Related Art An electronic still camera using a solid-state imaging device has been used as a means for taking image information into a computer device such as a personal computer or a word processor. This electronic still camera is configured to execute an imaging operation in response to an imaging instruction from an operator, and extract image information for one screen.

FIG. 7 is a block diagram showing an outline of an electronic still camera. An electronic still camera as a solid-state imaging device includes a CCD solid-state imaging device 1, a CCD driving circuit 2, a timing control circuit 3, and an image processing circuit 4.

The solid-state imaging device 1 includes a plurality of light-receiving pixels arranged in a matrix, a plurality of vertical shift registers associated with each of the light-receiving pixels on a column-by-column basis, and a horizontal shift register receiving the outputs of the plurality of vertical shift registers. Having. The plurality of light receiving pixels generate information charges corresponding to the subject image illuminated on the light receiving surface by a well-known lens mechanism, and accumulate information charges independently. The plurality of vertical shift registers receive the information charges accumulated in each light receiving pixel, and transfer the information charges one row at a time in the vertical direction in response to the vertical transfer clock φV. Then, the horizontal shift register takes in information charges transferred and output from the vertical shift register in units of one row, and sequentially transfers and outputs the information charges in the horizontal direction in response to the horizontal transfer clock φH. The output terminal of the horizontal shift register is provided with a capacitor for temporarily storing information charges in pixel units. The amount of information charges transferred and output is converted into a voltage value and taken out. It is output as a signal X (t).

A drive circuit 2 supplies a multi-phase vertical transfer clock φV and a horizontal transfer clock φH to each shift register of the solid-state image pickup device 1, and transfers information charges accumulated in a plurality of light receiving pixels in a predetermined order. Transfer and output. That is, in response to the frame transfer timing signal FT, the information charge of each light receiving pixel is transferred to the vertical shift register, and then each of the information charges is transferred by the vertical transfer clock φV and the horizontal transfer clock φH generated in response to the horizontal synchronization signal HD. The information charges are transferred and output via the horizontal shift register one row at a time in the horizontal scanning cycle.

[0006] The timing control circuit 3 supplies a frame transfer timing signal FT, which is activated in response to an imaging instruction, to the drive circuit 2. At the same time, a horizontal synchronizing signal HD is generated based on a reference clock having a constant period, and is supplied to the drive circuit 2 following the rise of the frame transfer timing signal FT. Thus, when the imaging operation is started by the imaging instruction, information charges corresponding to the subject image are accumulated in each light receiving pixel of the solid-state imaging device 1, and the information charges are synchronized with the horizontal scanning timing in units of one row. Transferred and output. As a result, an image signal X (t) that is continuous for each row is output from the solid-state imaging device 1.

[0007] The signal processing circuit 4 takes in the image signal X (t) output from the solid-state imaging device 1, performs various processes such as sample hold and level correction, and performs image signal Y (t) according to a predetermined format. ) Is output. The signal processing circuit 4 has a built-in A / D converter and outputs an image signal Y (t).
Is output as digital data. This signal processing circuit 4
Is supplied to a driving circuit for driving a display device such as an LCD panel,
It is recorded on a recording medium such as a semiconductor memory or a magnetic disk.

[0008]

A subject image is formed on the light receiving surface of the solid-state imaging device 1 by an optical mechanism combining a lens, an aperture, and the like. This optical mechanism is controlled so that the lens is focused on the light receiving surface of the solid-state imaging device 1 so that a subject image is correctly formed. This focusing control is configured to determine the position of the lens of the optical mechanism according to the state of the subject image captured through the lens.

However, in order to determine the state of an image captured through the lens, a light receiving unit for determination is provided separately from the solid-state image sensor 1, or the image state of the solid-state image sensor 1 is determined separately from the original imaging operation. It is necessary to repeat the imaging operation for determination. The provision of the light receiving unit for determination increases the cost of the light receiving unit. When the solid-state imaging device 1 performs the imaging operation for the determination, there is a problem that the time required for one imaging operation becomes long.

Accordingly, an object of the present invention is to realize focusing control capable of coping with high-speed operation while suppressing costs.

[0011]

Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light receiving pixels are arranged in a matrix on a light receiving surface and an object image is formed. A solid-state imaging device that accumulates information charges in each light-receiving pixel, an optical mechanism that forms a subject image on a light-receiving surface of the solid-state imaging device, and reads out information charges accumulated in each light-receiving pixel of the solid-state imaging device. A drive circuit for extracting image information from the solid-state imaging device, an image processing circuit for acquiring image information obtained from the solid-state imaging device, and generating an image signal according to a predetermined format, and an image processing circuit for acquiring image information obtained from the solid-state imaging device. A focus processing circuit for controlling the focal point of the first solid-state imaging device, and selectively reads out information charges from each light-receiving pixel of the solid-state imaging device to obtain first image information obtained by the focus processing circuit. After performing the focus control of the optical mechanism, the second image information obtained by reading out the information charge from each light receiving pixel of the solid-state imaging device is taken into the image processing circuit to generate an image signal. is there.

According to the present invention, the first image information used for the focus control is selectively read out from a part of the light receiving pixels of the solid-state image pickup device to obtain the first image information. Can be shortened. Further, since no imaging device is required other than the solid-state imaging device for obtaining an image signal, the number of elements constituting the device does not increase.

[0013]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to the present invention, and FIG. 2 is a timing chart for explaining the operation thereof.

The solid-state imaging device according to the present invention includes a CCD solid-state imaging device 11, a CCD driving circuit 12, a timing control circuit 1,
3 and an image processing circuit 14, a focusing processing circuit 15,
Lens drive mechanism 16, lens 17, shutter drive mechanism 1
8 and a shutter 19.

The solid-state image sensor 11 receives an image of a subject and accumulates information charges. The image sensor accumulates information charges accumulated in the image pickup unit and temporarily accumulates the information charges. This is a frame transfer method including a horizontal transfer unit that transfers and outputs charges one row at a time. In the imaging unit, a plurality of vertical shift registers are arranged in parallel, and each bit of the vertical shift registers constitutes a light receiving pixel. In the storage unit, a plurality of vertical shift registers continuous with the vertical shift register of the imaging unit are arranged in parallel, and each bit of the vertical shift register forms a storage pixel. The vertical shift register of this storage unit is optically shielded from light,
It is configured so that light from the outside does not enter. Here, the number of pixels in the accumulation unit in the vertical direction, that is, the number of rows is set smaller than the number of light-receiving pixels in the imaging unit. In other words, the bit number of the vertical shift register of the storage unit is set to be smaller than the bit number of the vertical shift register of the imaging unit. In the horizontal transfer unit, a horizontal shift register is arranged on the output side of the vertical shift register of the storage unit, and information charges transferred and output from the vertical shift register are received in each bit of the horizontal shift register, and the horizontal shift register receives the information charges in units of one row. Output in the direction. At the output end of the horizontal shift register, a capacitor for temporarily storing information charges in pixel units is provided, and the amount of information charges transferred and output is converted into a voltage value and extracted.

The solid-state imaging device 11 is configured so that a part of the information charges can be selectively discharged in the process of transferring the information charges from the imaging unit to the storage unit or in the process of transferring the information charges from the storage unit to the horizontal transfer unit. You. Alternatively, it is configured such that information charges can be selectively accumulated in some of the plurality of light receiving pixels of the light receiving section. Of course, it is also possible to accumulate information charges in all the light receiving pixels and transfer and output all of the information charges via the vertical shift register and the horizontal shift register. However, in this case, since some of the information charges cannot be taken into the storage unit, the information charges must be temporarily stored on the output side of the imaging unit as well as the storage unit.

The drive circuit 12 supplies a multi-phase vertical transfer clock φV and a multi-phase vertical transfer clock φS to the vertical shift register of the imaging section and the vertical shift register of the storage section of the solid-state imaging device 1, respectively. Further, a horizontal transfer clock φH is supplied to the horizontal shift register of the horizontal transfer unit. Here, the vertical transfer clock φV discharges information charges accumulated in each light receiving pixel of the imaging unit and transfers and outputs the information charges accumulated after the ejection to the accumulation unit. The storage transfer clock φS captures information charges from the imaging unit to the storage unit and transfers and outputs the information charges captured by the storage unit to the horizontal transfer unit. The horizontal transfer clock φH is output from the horizontal transfer unit. Transfers and outputs information charges. This allows
Information charges accumulated in the plurality of light receiving pixels of the imaging unit are transferred and output in a predetermined order.

The timing control circuit 13 includes a transfer timing signal FT and an ejection timing signal ST for an imaging operation.
Further, a transfer timing signal RT for the focusing operation is generated and supplied to the drive circuit 12. At the same time, the timing control circuit 13 generates a shutter drive signal SD and supplies it to the shutter drive mechanism 18.

Transfer timing signal RT for focusing operation
Is temporarily lowered when the period A1 has elapsed from the start of the imaging period T, and the drive circuit 12 is activated. At the falling timing of the transfer timing signal RT, the information charges stored in the imaging section of the solid-state imaging device 11 are selectively transferred to the storage section by the operation of the vertical transfer clock φV and the storage transfer clock φS. Here, the information charges taken into the storage section are output from the horizontal transfer section as first image information x (t). After the above-described transfer operation is completed, the transfer timing signal RT is temporarily dropped again when the period A2 has elapsed, and the drive circuit 12 is activated. The transfer operation at the falling timing of the transfer timing signal RT is the same as the operation when the period A1 has elapsed. As a result, the first image information x
(t) can be obtained twice in succession. The first image information x (t) is supplied to a focusing processing circuit 15 described later.

After the transfer operation in response to the second fall of the transfer timing signal RT is completed, the discharge timing signal ST is temporarily dropped at a timing set according to the exposure state of the solid-state imaging device 11. , Drive circuit 1
Start 2 At the falling timing of the discharge timing signal ST, information charges accumulated in each light receiving pixel of the imaging unit are transferred to a drain region for discharging excess charges arranged adjacent to the light receiving pixel by the operation of the vertical transfer clock φV. Is discharged. At this time, the vertical transfer clock φV is given in multiple phases. However, in order to prevent the information charges from being transferred to the storage section, the vertical transfer clock φV is changed to a phase that eliminates the phase difference between them. The phase is changed so that the transfer direction is opposite to that of the storage unit. When discharging the information charges of the imaging section, the potential of the drain region is controlled in accordance with the operation of the vertical transfer clock φV.

Transfer timing signal FT for imaging operation
Is temporarily dropped at a predetermined timing in the latter half of the imaging period T, and activates the drive circuit 12. At the falling timing of the transfer timing signal FT, the information charges accumulated in the imaging unit during the period L after the ejection operation in response to the ejection timing signal ST is completed are transferred to the accumulation unit side. At this time, the solid-state imaging device 11 does not selectively discharge the information charges, and all the information charges are stored in the storage unit and the storage unit side of the imaging unit. Then, the shutter drive signal S
D rises at the beginning of the imaging period T, and then falls at the falling timing of the transfer timing signal FT, that is, at the end of the period L, which is the light receiving period of the imaging unit.
The opening and closing of the shutter 19 is controlled. That is, the shutter drive signal SD is set so as to open the shutter 19 at the start of the imaging period T and close the shutter 19 at the end of the period L serving as the light receiving period of the imaging unit.
Thus, when the information charges are transferred to the storage section in response to the transfer timing FT, the shutter 19 is closed and the solid-state imaging device 11 is shielded from light. Does not occur, and the information charge amount of the imaging unit is maintained. In this state,
The information charges are transferred from the storage unit to the horizontal transfer unit in units of one row, and the information charges are transferred and output to the second image signal X.
Output as (t).

The signal processing circuit 14 performs various processes such as sample hold and level correction on the second image signal X (t) input from the solid-state imaging device 11, and performs image processing according to a predetermined format. Output as a signal Y (t). The signal processing circuit 4 includes, for example, an A / D converter,
The image signal Y (t) is output as digital data. The image signal Y (t) output from the signal processing circuit 4 is LC
The data is supplied to a drive circuit for driving a display device such as a D panel, and is recorded on a recording medium such as a semiconductor memory or a magnetic disk.

The focus processing circuit 15 generates a lens drive signal FD for focus control based on the first image signal x (t) input from the solid-state image sensor 11. For example, when the first image signal x (t) is first input, the focusing processing circuit 15 detects the high-frequency component and moves the lens 17 by a predetermined distance in any direction. And generates a lens drive signal FD. Subsequently, when the first image signal x (t) is input for the second time, the high frequency component of the first image signal x (t) is detected again and compared with the previously detected value. At this time, the first input image signal x
If the high frequency component of (t) is larger, a lens drive signal FD for moving the lens 17 in the direction of the first position is generated, and conversely, the first image signal x input second time
If the high frequency component of (t) is larger, a lens drive signal FD that does not move the position of the lens 17 is generated.
An optical mechanism is constituted by the lens driving mechanism 16, the lens 17, the lens barrel and the like.

The lens driving mechanism 16 is connected to a lens barrel that holds the lens 17, and drives the lens 17 in response to a lens driving signal FD input from the focusing processing circuit 15 for light incident on the solid-state imaging device 11. Move in a direction parallel to the optical path. The lens 17 is arranged on an optical path of light incident on the solid-state imaging device 11 and forms a subject image on an imaging unit of the solid-state imaging device 11. Incidentally, the lens 17 may be a combination of a plurality of lenses.

The shutter drive mechanism 18 is connected to the shutter 19 and opens and closes the shutter 19 in response to a shutter drive signal SD input from the timing control circuit 13. The shutter 19 is disposed, for example, between the lens 17 and the solid-state imaging device 11, and blocks light emitted to the imaging unit of the solid-state imaging device 11 through the lens 17 as necessary.

In the above solid-state imaging device, the operation for outputting the first image signal x (t) and the second image signal X (t) is completed during the imaging period T, and this operation is repeated. Thus, the image signal Y is generated at a period corresponding to the imaging period T.
(t) can be obtained. At this time, the focus control of the optical system gradually converges to an optimal state by repeating the operation during the imaging period T.

The information used for the focusing operation is obtained not only from the first image signal x (t) but also a part of the second image signal X (t) obtained by the imaging operation one cycle before. It is also possible to obtain from. In this case, the second image signal X
After the imaging operation for obtaining (t) is completed, the lens 17 may be moved in any direction to obtain the first image signal x (t). This requires a configuration for selectively extracting a part of the second image signal X (t) output one cycle before, but the first image signal x (t) is repeated twice. There is no need to output.

FIG. 3 is a schematic diagram showing the configuration of a frame transfer type CCD solid-state imaging device 11 used in the solid-state imaging device of the present invention. In this figure, for simplification of the drawing, the arrangement of the light receiving pixels is shown by 6 rows × 8 columns. Also,
Regarding the accumulation pixels, the number of rows is 1/2 of the light receiving pixels (3 rows ×
8) is shown.

CCD solid-state imaging device 1 of frame transfer system
Reference numeral 1 denotes an imaging unit 11i, a storage unit 11s, and a horizontal transfer unit 11h.
And an output unit 11d. The imaging unit 11i includes a plurality of CCD shift registers that are continuous in the vertical direction and that are parallel to each other, and each bit of these shift registers constitutes a light receiving pixel. In this embodiment, 8 columns of 6-bit shift registers are arranged, and light receiving pixels of 6 rows × 8 columns are configured. To each shift register, a multi-phase vertical transfer clock φV is applied commonly to each column, and information charges accumulated as light receiving pixels by each bit of the shift register are transferred to the storage section 11s by the operation of the vertical transfer clock φV. You. The storage unit 11s includes a plurality of shift registers connected to the shift registers of the imaging unit 11i, and each bit of these shift registers forms a storage pixel. In this embodiment, eight columns of three-bit shift registers are arranged, and storage pixels of three rows × eight columns are configured.
Each shift register is shielded so that light from the subject is not incident thereon, receives the multi-phase accumulated transfer clock φS, takes in the information charges transferred and output from the imaging unit 11i, and sequentially takes in the taken-in information charges. Horizontal transfer unit 11
h. The horizontal transfer unit 11h includes an imaging unit 11i.
And a single shift register having the number of bits corresponding to the number of columns of the shift register of the storage unit 11s, and each bit is connected to each output of the shift register of the storage unit 11s. The horizontal transfer unit 11h is shielded from light similarly to the storage unit 11s, receives the multi-phase horizontal transfer clock φH, and outputs the information charges transferred from the storage unit 11s to the output unit 1 for each row.
Transfer and output to 1d side. Then, the output unit 11d accumulates information charges transferred and output from the horizontal transfer unit 11d for each pixel, and outputs a potential that changes according to the accumulated charge amount as an image signal X (t).

Here, in the focusing operation, as shown in FIG. 4A, after the information charges are accumulated in all the light receiving pixels of the image pickup section 11i, these information charges are stored in the accumulation section 11s. Transferred to At this time, since the number of storage pixels in the storage unit 11s is set to be smaller than the number of light reception pixels in the light reception unit 11i, the information charge stored in each light reception pixel of the imaging unit 11i is equal to the number of storage pixels. Only the storage unit 1
It is taken into the 1s accumulation pixel.

In an image pickup operation for extracting an image signal for displaying an image, as shown in FIG. 4B, after information charges are accumulated in all light receiving pixels of the image pickup section 11i, these charges are accumulated. Is transferred to the storage section 11s side. At this time, since all of the information charges accumulated in each light receiving pixel of the imaging unit 11i cannot be taken into the accumulation pixels of the accumulation unit 11s, the information charges that cannot be taken into the accumulation unit 11s remain in the imaging unit 11i. become. However, in the imaging operation, the shutter 19 is closed when predetermined information charges are accumulated in the imaging unit 11i.
The light receiving pixels of the imaging unit 11i have the same function as the storage pixels of the storage unit 11s.

The thinning operation in the process of transferring the information charges from the imaging unit 11i to the storage unit 11s during the focusing operation will be described below. FIG. 5 is a waveform diagram of the vertical transfer clock φV and the accumulation transfer clock φS, and FIG. 6 is a diagram showing a change in potential at a connection portion between the imaging unit 11i and the accumulation unit 11s. In these figures, a case is shown in which, in the process of transferring information charges from the image pickup unit 11i to the storage unit 11s by using three-phase clocks, 画素 pixels are thinned out. In the image pickup unit 11i and the storage unit 11s, one bit is constituted by three transfer electrodes.

First, at a first timing T1,
It is assumed that the clocks φV1 and φV2 are at a low level, the clock φV3 is at a high level, and at the same time, the clocks φS1 and φS2 are at a low level and the clock φS3 is at a high level. At this time, a potential well is formed in a region below the transfer electrode to which the clock φV3 and the clock φS3 are applied, and information charges are accumulated in the potential well.

The clocks φV1, φV3 and the clocks φS1, φ
At the second timing T2 after the inversion of S3, the potential well moves to a region below the transfer electrode to which the clock φV1 and the clock φS1 are applied, and the information charge accumulated in the well along with the movement of the potential well. Is transferred. At this time, information charges are transferred from the imaging unit 11i to the storage unit 11s at the end of the imaging unit 11i on the storage unit 11s side. Then, at the third timing T3 after the clocks φV1, φV2 and the clocks φS1, φS2 are inverted,
The potential well moves to a region below the transfer electrode to which the clock φV2 and the clock φS2 are applied, and the information charge accumulated in the well is transferred along with the movement of the potential well.

At a fourth timing T4 after the clocks φV2 and φV3 are inverted, the potential well moves to a region below the transfer electrode to which the clock φV3 is applied, and is accumulated in the well along with the movement of the potential well. Information charges are transferred. At this time, since the clocks φS1, φS2, and φS3 are set to have twice the period of the clocks φV1, φV2, and φV3, no information charges are transferred on the side of the storage unit 11s. At the fifth timing T5 after the clocks φV1 and φV3 are inverted, the potential well moves to a region below the transfer electrode to which the clock φV1 is applied, and is accumulated in the well along with the movement of the potential well. Information charges are transferred. However, at the end of the imaging unit 11i on the side of the storage unit 11s, since no potential well is formed at the end of the storage unit 11s on the side of the imaging unit 11i, the information charges transferred from the imaging unit 11i to the storage unit 11s are: The charge is not taken in the storage portion 11s but is discharged to the drain for absorbing unnecessary charges. At the fifth timing T5, the clock φS3
Are inverted, and a potential well is formed in a region below the transfer electrode to which the clock φV2 is applied and the transfer electrode to which the clock φV3 is applied. At the sixth timing T6 after the clocks φV1, φV2 and the clock φS2 are inverted, the potential well moves to a region below the transfer electrode to which the clock φV2 and the clock φS2 are applied, and the potential well moves along with the movement of the potential well. The information charges stored in the well are transferred.

The first to sixth timings T1 to T
By repeating the operation of No. 6, only １ ／ of the information charges stored in each light receiving pixel of the imaging unit 11i are taken into the storage unit 11s. here,
By changing the ratio of the period of the vertical transfer clock φV to the period of the storage transfer clock φS, it is possible to change the ratio of the information charges taken from the imaging unit 11i to the storage unit 11s. For example,
If the cycle of the accumulation transfer clock φS is set to be four times the cycle of the vertical transfer clock φV, one-fourth of the information charges accumulated in each light receiving pixel of the imaging unit 11i is taken into the accumulation unit 11s. can do.

In the above embodiment, the case where the information charges of the imaging section of the solid-state imaging device are thinned out in units of rows has been described. However, it is also possible to thin out the image information in units of columns. In such a case, for example, the information charges are selectively accumulated in the output section at the stage of outputting the information charges from the horizontal transfer section to the output section, or the information charges of a plurality of pixels are transferred in the horizontal transfer section. To reduce the number of pixels, etc., it is possible to thin out information charges in column units. Further, by combining a plurality of thinning-out processes, it is possible to thin out in units of rows and columns, and to extract information charges only from a specific area of the screen.

Further, the solid-state image pickup device used in the image pickup apparatus of the present invention is not limited to the frame transfer method, but may be an interline method or a frame interface method as long as it can perform a thinning process in the information charge transfer process. It is possible to use even the line method.

[0039]

According to the present invention, focusing processing can be performed in a short time without using a dedicated light receiving element. In particular, in an imaging device such as an electronic still camera using a solid-state imaging device, the imaging operation does not involve winding up a film as in an optical camera, and is suitable for high-speed continuous shooting. It can respond to continuous shooting operation. Therefore, an imaging device which can operate at high speed at low cost can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the solid-state imaging device of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a frame transfer type solid-state imaging device.

FIG. 4 is a diagram illustrating a state of accumulation of information charges in a solid-state imaging device using a frame transfer method.

FIG. 5 is a waveform diagram of a vertical transfer clock and an accumulation transfer clock.

FIG. 6 is a potential diagram illustrating how charges are transferred from an imaging unit to a storage unit.

FIG. 7 is a block diagram illustrating a configuration of a conventional imaging device.

[Explanation of symbols]

 Reference Signs List 1, 11 CCD solid-state imaging device 2, 12, CCD drive circuit 3, 13, Timing control circuit 4, 14, Signal processing circuit 15, Focusing processing circuit 16, Lens drive mechanism 17, Lens 18, Shutter drive mechanism 19 Shutter 11i Image pickup unit 11s Storage unit 11h Horizontal Transfer unit 11d Output unit

Claims (5)

[Claims] 1. A solid-state imaging device in which a plurality of light-receiving pixels are arranged in a matrix on a light-receiving surface, an information charge is stored in each light-receiving pixel according to a subject image, and a subject image is formed on the light-receiving surface of the solid-state imaging device. An optical mechanism, a drive circuit for reading out information charges accumulated in each light receiving pixel of the solid-state imaging device and extracting image information, and taking in image information obtained from the solid-state imaging device and generating an image signal according to a predetermined format An image processing circuit, and a focusing processing circuit that captures image information obtained from the solid-state imaging device and controls the focus of the optical mechanism, and selectively reads out information charges from each light-receiving pixel of the solid-state imaging device. After taking the first image information obtained by the focusing processing circuit and controlling the focus of the optical mechanism, information charges are read from each light receiving pixel of the solid-state imaging device. A solid-state imaging device, wherein the obtained second image information is taken into the image processing circuit to generate an image signal. 2. The solid-state imaging device according to claim 1, wherein the first imaging operation and the second imaging operation are repeated to continuously generate an image signal. 3. The solid-state imaging device, comprising: a light receiving unit in which a plurality of light receiving pixels are arranged in a matrix; a storage unit corresponding to the light receiving unit, in which a smaller number of storage pixels than the light receiving pixels of the light receiving unit are arranged in a matrix; 2. The solid-state imaging device according to claim 1, wherein a frame transfer method is used. 4. A shutter mechanism disposed on an optical path of light emitted from the optical mechanism to a light receiving surface of the solid-state imaging device, and configured to block light emitted to the light receiving surface of the solid-state imaging device. The solid-state imaging device according to claim 3, wherein the shutter mechanism is closed at a timing at which information charges are read from the solid-state imaging device in a second imaging operation. 5. The solid-state imaging device according to claim 4, wherein the first imaging operation and the second imaging operation are repeated to generate an image signal continuously.