JPH07115157A - Semiconductor package equipped with three-dimensional printed board - Google Patents

Abstract

PURPOSE:To enable a semiconductor package to be enhanced in number of outer leads without increasing it in external size and lessening the leads in wire width and pitch and surface-mounted on a printed board without causing defective soldering. CONSTITUTION:A metal base board is composed of a metal plate 12 and copper foil layers 14 and 16 which are laminated on the metal plate 12 through the intermediary of insulating layers 13 and 15 and where circuits are provided, and a flange 18 is provided to the peripheral edge of an opening 17 of the metal base board by bending and drawing. The copper foil layers 14 and 16 are so formed as to be exposed like steps at the flange 18 to serve as a correspondent part to outer leads. A semiconductor integrated circuit device 11 is mounted on the metal base board through the opening 17 and connected to the copper layers 14 and 16 with bonding wires 19. When a semiconductor package 10 is surface-mounted on a printed board, the stepped part provided to the flange 18 is made to correspond to pads formed on the printed board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor integrated circuit device, and more particularly to a semiconductor package having a large number of outer lead portions electrically connected to the semiconductor integrated circuit device from the outer periphery.

[0002]

2. Description of the Related Art There are various types of semiconductor packages for integrated circuits such as DIP (Dual In-line Package). Particularly, as a semiconductor package for an LSI having a large number of external terminals, a QFP as shown in FIG. (Quad Flat Pa
ckage) 90. In the QFP 90, a plurality of leads connected to the semiconductor integrated circuit element (chip) are led out as outer leads 91 on the outer periphery (four directions) of the package. When packaging an integrated circuit element in a QFP, a lead frame in which a die pad, an inner lead and an outer lead are integrated is used to mount the integrated circuit element on the lead frame, and the integrated circuit element and the inner lead are bonded. They are connected with wires, and then the entire body except the outer lead parts is molded with resin. The number of outer leads tends to increase with the large-scale integration of semiconductor devices and the increase in size of semiconductor devices.

When the number of outer leads is increased, the width and pitch of the inner leads and outer leads of the lead frame must be narrowed unless the package size is changed. For example, when the package size is 28 mm square, if the outer leads are 120, the lead width is 0.35 mm and the pitch is 0.8 mm, but if the number of leads is 160, the lead width is 0.30.
mm, pitch 0.65 mm, and if the number of leads is further increased to 208, the lead width is 0.20 mm and the pitch is 0.5 mm. The increasing number of pins, that is, the narrowing of lead width and pitch, is progressing even further, and is currently 0.3 m.
It has been developed up to m pitch. If the width of the outer lead is narrowed in this way, its mechanical strength becomes insufficient, and bending or warpage of the lead portion is likely to occur, and when the semiconductor package is surface-mounted on a printed circuit board or the like, soldering failure may occur. It is easy to wake up.

As a means for solving such problems,
For example, there are a package described in Japanese Patent Laid-Open No. 1-132147 and an electronic circuit package described in Japanese Patent Laid-Open No. 4-6893 by the present inventors. The package described in Japanese Unexamined Patent Publication No. 1-132147 has aluminum or copper as a base metal and a resin layer made of an epoxy resin having a thickness of several tens of μm as an insulating layer. The bent portion is formed by. An integrated circuit element is mounted in the central part and the peripheral part is used as an outer lead.

Further, the electronic circuit package described in Japanese Patent Laid-Open No. 4-6893 is a soup dish-shaped product obtained by bending or drawing a metal base substrate. When viewed, the integrated circuit element is mounted on the bottom. Then, it is mounted on the printed circuit board with the opening surface side facing the printed circuit board.
FIG. 11 (a) is a perspective view showing an electronic circuit package in which the one disclosed in Japanese Patent Application Laid-Open No. 4-6893 is further improved to have a flange portion on the outer periphery, and FIG. 11 (b) is Figure 11 (a)
11C is a sectional view of the electronic circuit package of FIG. 11C, and FIG. 11C is a sectional view taken along the line BB ′ of FIG. 11B. This electronic circuit package 80 is of a substantially rectangular parallelepiped shape having an opening surface 85, an insulating layer 82 and a pre-patterned wiring conductor layer 83 are provided on a metal plate 81, and a flange portion 84 is provided on the outer peripheral portion. It is deep-drawn or bent to have it. The wiring conductor layer 83 corresponds to the inner lead and the outer lead, and extends to the flange portion 84. The integrated circuit element 86 is mounted in the central portion from the opening surface 85 side, and is electrically connected to the wiring conductor layer 83 by a bonding wire 87.

[0006]

The above-mentioned semiconductor device (JP-A-1-132147) and electronic circuit package (JP-A-4-6893)
Narrows the outer lead width (for example, 0.3 to 0.1).
(mm width) is effective for soldering failure due to bending or warping of the lead portion. However, when such a semiconductor device or electronic circuit package is surface-mounted on a printed circuit board as a semiconductor package, there are the following problems in addition to the problems on the semiconductor package side, and the narrowing of outer leads is limited. There is.

Usually, a semiconductor package is surface-mounted by printing solder cream on the pad portion of a printed board, mounting the semiconductor package at a predetermined position by an automatic mounting machine, and then performing reflow soldering using a reflow furnace. It If the pitch of the outer leads is narrow, it is necessary to narrow the opening of the screen printing metal mask used for solder cream printing.However, due to the relationship with the metal mask plate thickness, the opening of the metal mask is narrow. There is a limit to conversion. If this opening is narrowed, the conventional solder cream cannot be used because it has poor printing characteristics.The shape of the solder cream is changed from an irregular shape to a spherical shape, and the temperature and humidity during printing are strictly controlled. Management is required. In addition, higher accuracy is required as the alignment accuracy of the automatic mounting machine during solder cream printing and when mounting the semiconductor package on the printed circuit board. Therefore, there is a problem in terms of cost, such as a facility for optically recognizing the position.

As a solder supplying method other than the solder cream printing method, there are a method of directly plating the outer lead portion of the semiconductor package with thick solder and a method of chemically depositing the solder on the component pad portion of the printed board. The technology has not been established yet, and the process is more complicated and the cost is higher than that of the solder cream printing method.

As described above, there are many technical and cost problems in surface mounting a semiconductor package having a narrowed outer lead on a printed circuit board.

An object of the present invention is to increase the number of outer leads without increasing the outer size of the package and narrowing the line width and pitch of the outer leads, and soldering at the time of surface mounting on a printed circuit board. It is to provide a semiconductor package that does not cause a defect.

[0011]

A semiconductor package using a three-dimensional printed board of the present invention uses a metal base board in which a plurality of circuit-processed copper foil layers are laminated on a metal plate via insulating layers. Then, in the three-dimensional printed board for mounting a semiconductor integrated circuit element, which is formed into a shape having a brim portion on the peripheral edge of the opening surface by performing bending or drawing on the metal base substrate, one end side of each copper foil layer is The brim portion is formed so as to be exposed in a stepwise manner with each surface shifted through the insulating layer, and the other end side of each copper foil layer is a portion electrically connected to the semiconductor integrated circuit element and is the insulating layer. It is formed in a staircase pattern with each surface shifted through.

[0012]

In the conventional semiconductor package, the portion corresponding to the outer leads is formed of a circuit-processed copper foil layer. By laying a plurality of copper foil layers on the same area, the number of wirings on the same area can be reduced. The number of wires (the number of outer leads) can be dramatically increased without using narrowed wires. There are various conceivable three-dimensional arrangements of the wiring patterns connected from the copper foil layer, that is, the semiconductor integrated circuit element. It is possible to form three-dimensionally on the same line or alternately.

In the semiconductor package of the present invention, a metal plate having a thickness of about 0.05 to 2.0 mm is used, and preferably aluminum having a thickness of 0.1 to 1.0 mm, nickel silver or brass. Copper alloy such as copper, copper, copper clad invar, stainless steel, iron, silicon steel, electrolytically oxidized aluminum and the like can be used.

Examples of the insulating layer used in the present invention include thermosetting resins such as epoxyphenol and bismaleimide, thermoplastic resins such as polyamideimide, polysulfone, polyparabanic acid and polyphenylene sulfide, and thermoplastic polyimide. The thing obtained by heating and imidizing the polyamic-acid varnish which is a precursor can also be used. Alternatively, a heat-resistant organic polymer film, for example, polyimide, polyamide imide, aramid, polyether sulfone, both surfaces of each film such as polyether ether ketone, a polyamic acid varnish, which is a precursor of thermoplastic polyimide, is applied and heated and imidized. It is also possible to use those obtained. Further, in the case of a thermoplastic polyimide soluble in an organic solvent, a film obtained by casting or coating and drying a thermoplastic varnish in the same manner as the above film forming method, or an extrusion molded film or sheet of a thermoplastic polyimide is also used. it can. Furthermore, on the back surface of the metal plate and / or copper foil used, polyimide acid varnish,
Alternatively, thermoplastic polyimide may be applied, dried, and laminated.

It is also possible to use a combination of the above-mentioned insulating layer materials. Further, for the purpose of improving heat dissipation, an inorganic filler may be added to the insulating layer as long as the machinability such as bending is not impaired. Examples of these fillers include alumina, silica, silicon carbide, aluminum nitride, and boron nitride.

Of these insulating layers, the most preferable one in the present invention is a thermoplastic polyimide having an imide structure in its main chain and having a glass transition temperature (T _g ) of 16
0 ° C to 350 ° C, JIS (Japanese Industrial Standard)
-The elongation percentage at break measured by the method specified in C2318 is 30% or more. By defining the glass transition temperature as described above, both the adhesive strength between the metal plate and the copper foil layer and the thermal reliability during wire bonding become excellent. Further, by setting the elongation rate to 30% or more, the reliability during machining becomes excellent. In such a thermoplastic polyimide, of course, an inorganic filler can be mixed.

As the copper foil layer, commercially available electrolytic copper foil, rolled copper foil or the like, which is relatively inexpensive and easily available, is used.

As a method for connecting the metal plate, the insulating layer and the copper foil layer to each other, there are a hot roll method, a hot press method and the like. In the semiconductor package of the present invention, the copper foil layer and the insulating layer have a multi-layered structure. As a method for forming such a multi-layered structure, for example, there is a build-up method. The build-up method is a method of sequentially laminating an insulating layer and a copper foil layer on a metal plate. In the case of stacking by the build-up method, the hot pressing method may be repeatedly performed, or the formation of a conductor layer made of copper or the like by plating, vapor deposition method or the like after coating and forming an insulating layer may be repeated. You may combine the lamination method of these.

In the present invention, the circuit-processed copper foil layer corresponds to the inner lead and the outer lead, and the insulation of each layer is provided at the collar portion which is the connection portion with the printed circuit board side and the connection portion with the integrated circuit element. The layers are removed stepwise so that the end portions of the copper foil layers on each surface are formed in a staggered manner. As a method for removing the insulating layer, in the case of the build-up method, the removed portion is punched before hot pressing, or after hot pressing, cutting removal by an NC router, wet or dry etching, laser processing method, etc. Used.

When the insulating layer is made of polyimide, an alkaline solution etching is used as the wet etching. For example, an alcohol solution such as potassium hydroxide or sodium hydroxide can be used. If necessary, hydrazine may be added thereto. Compounds may be added.

As the dry etching, there are a plasma ashing method using oxygen plasma, a reactive ion etching method and the like, and a fluorocarbon type gas such as CF ₄ may be mixed if necessary.

As a laser processing method, there is a method using an excimer laser, a carbon dioxide gas laser, a YAG laser, or the like. As the excimer laser, for example, ArF type and KrF are used.
The system can be mentioned.

In the present invention, it is also possible to electrically connect the copper foil layers on each surface. As such an electrical connection method, a through hole is formed by a drill or the above etching and laser processing, and then a method such as plating, solder, or conductive paste that is generally used in a general method for manufacturing a printed circuit board. There is a method of connecting the copper foil layers with each other. It is also possible to connect the copper foil layers by wire bonding.

The drawing and bending mechanical processing in the present invention can be carried out by press processing using an ordinary die. In order to protect the circuit-processed copper foil layer during drawing, the surface of the mold may be resin-coated and used, or a concave shape may be provided in the mold according to the wiring pattern shape of the copper foil layer. Deep drawing,
In the bending process with a small radius of curvature, a process of applying heat or a process of swelling the insulating layer with a solvent or the like may be performed.

Although the cross-sectional shape of the collar portion can be selected as appropriate, it is formed in a concave shape, for example, in consideration of processing superiority or electrical connection to the printed circuit board. In order to improve the connection reliability and prevent damage to the insulating layer and the copper foil layer, it is desirable to process the collar portion with a radius of curvature of 0.1 to 5.0 mm. In the examples described below, the radius of curvature was 1.0 mm.

When each copper foil layer is thick (for example, 70 μm)
m or more) or the number of copper foil layers is three or more, the step difference between the surfaces of the copper foil layers exposed on the surface of the collar portion becomes large. Therefore, when such a semiconductor package is surface-mounted on a printed circuit board, etc., the thickness and amount of solder will differ for each copper foil layer, which requires labor to secure connection reliability and lowers workability. I have something to do. Therefore, the collar portion is folded, and one copper foil layer is exposed at each top portion of the fold on the printed circuit board side so that the surfaces of the exposed copper foil layers are arranged so as to be in contact with the same plane. Is desirable. The plane here corresponds to the surface of a printed circuit board or the like on which this semiconductor package is mounted. In other words, the cross-sectional shape of the brim portion may have a repetitive shape of unevenness so that the heights of the exposed portions of the copper foil layer are uniform. In this case, the unit of the repeating shape includes a concave shape (rectangular waveform), a triangular waveform, a U shape, and the like. It is easy to process the fold into such a folded shape by the above-mentioned drawing and bending, and a semiconductor package having a fold is formed from a flat metal base substrate by a single machining operation. Can be formed.

For bonding the semiconductor package of the present invention to the semiconductor integrated circuit element, a thermocompression bonding method using a gold-silicon eutectic as a die bonding method or a method using a conductive adhesive resin, solder plating, gold plating, silver plating, etc. Is used.

A wire bonding method or a flip chip method using bump formation is used for electrical connection between the semiconductor integrated circuit element and the copper foil layer which is a wiring pattern. As described above, the copper foil layer end portion corresponding to the bonding region on the inner lead has a staircase structure, and the cross-sectional structure thereof may be the same line or staggered structure as described above. At this time, when the wire bonding pads on the semiconductor integrated circuit element side have a narrow pitch, the tips of the copper foil layers (bonding regions) are formed in a zigzag shape so that the bonding wires Contact can be prevented.

The number of semiconductor integrated circuit elements mounted on a semiconductor package using this three-dimensional printed board is not limited to one, and a plurality of elements can be mounted. When a plurality of elements are mounted, mutual wiring between the elements is performed by connecting copper foil layers on each surface by a peer hole or the like. The mounted semiconductor integrated circuit element is generally hermetically sealed. For hermetic sealing, transfer molding or potting with an epoxy resin or the like can be used, for example. An inorganic filler (alumina, silica, aluminum nitride, boron nitride, silicon carbide, etc.) is mixed into the sealing resin as needed for reasons such as heat dissipation and matching of the thermal expansion coefficient.

When the semiconductor package of the present invention is surface-mounted on a printed circuit board, solder printing pad portions are separated and provided in parallel in a plurality of rows according to the number of copper foil layers on the semiconductor package side. Use a printed circuit board. A normal solder cream printing method is used as the surface mounting method. As the solder cream, amorphous or spherical eutectic solder (Sn 63%, Pb 37%), high temperature solder (Sn 5%, Pb 95%), or the like can be used. After printing the solder cream, a semiconductor package is mounted on a printed circuit board by an automatic mounting machine, and soldering is performed using a reflow furnace. As the reflow furnace, it is desirable to use infrared heating and air combined type, nitrogen reflow, vapor phase type using Fluorinert, and laser heating soldering type.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

<< First Embodiment >> FIG. 1A shows a first embodiment of the present invention.
It is sectional drawing of the semiconductor package using the three-dimensional printed circuit board of an Example. This semiconductor package 10 mounts a semiconductor integrated circuit element 11, and has two circuit-processed copper foil layers (wiring patterns). On the metal plate 12, the first insulating layer 13, the first copper foil layer 14 and the second
After forming a circuit pattern having a multi-layer structure by the insulating layer 15 and the second copper foil layer 16 of, a bending process or a drawing process is performed to form a box shape having an opening surface 17,
The semiconductor package 10 is used. First insulating layer 13
Is provided on the entire surface of the metal plate 12 on the opening surface 17 side. A brim portion 18 is formed on the peripheral edge of the opening surface 17 as an electrical connection portion with the printed circuit board. Brim part 18
Has a concave shape, and the radius of curvature of the bend is 1.0 m.
It has become m.

Copper having a thickness of 0.2 mm is used as the metal plate 12, thermoplastic polyimide manufactured by Mitsui Toatsu Chemicals, Inc. is used as the insulating layers 13 and 15, and the thickness of each insulating layer 13 and 15 is 20 μm. And A copper foil having a thickness of 18 μm was used as each of the copper foil layers 14 and 16, and the build-up method described above was adopted as the processing method.

Each of the copper foil layers 14 and 16 is provided so as to extend to the brim portion 18. Comparing the positions of the tip portions of the first copper foil layer 14, the second insulating layer 15, and the second copper foil layer 16 in the brim portion 18, the tip portion of the first copper foil layer 14 is the best. The second insulating layer 1 extending to the peripheral side and then the second insulating layer 1
5 and the tip of the second copper foil layer 16 is located closest to the center of the semiconductor package 10 among these. An interval is also provided between the tip of the first copper foil layer 14 and the tip of the metal plate 12 to prevent a short circuit between the first copper foil layer 14 and the metal plate 12. It is set to be 50 μm or more. That is, each insulating layer 1
3, 15 and the copper foil layers 14 and 16 form a staircase structure, and the tips of the copper foil layers 14 and 16 are exposed. Eventually, the portion of this staircase structure becomes the staircase-shaped conductor pattern 21 corresponding to the outer lead.

The semiconductor integrated circuit element 11 is mounted on the central portion of the semiconductor package 10 from the opening surface 17 side. In this case, the semiconductor integrated circuit element 11 is bonded onto a die pad (not shown) on the semiconductor package 10 with a conductive adhesive, solder, gold, silver plating or the like. Each of the copper foil layers 14 and 16 extends from the collar portion side 18 to the vicinity of the semiconductor integrated circuit element 11, and at the end portion on the semiconductor integrated circuit element 11 side, each copper foil layer is the same as the collar portion 18 side. 1
A staircase structure is constituted by 4, 16 and the second insulating layer 15. The portion of this staircase structure becomes the staircase-shaped conductor pattern 22 corresponding to the inner lead. And each copper foil layer 1
The portions of the stepped conductor patterns 22 of 4 and 16 are bonding regions, and the copper foil layers 14 and 16 and the semiconductor integrated circuit element 11 are electrically connected by the bonding wires 19.

Further, in order to hermetically seal the semiconductor element integrated circuit element 11 and the bonding wire 19, except for the collar portion 18, transfer molding is performed to
An epoxy resin 20 containing a filler (alumina, silica, aluminum nitride, boron nitride, silicon carbide, etc.) is filled. By filling the inside of the semiconductor package 10 with the epoxy resin 20, the mechanical strength of the semiconductor package 10 is also improved.

Next, the cross-sectional structure of each of the stepped conductor patterns 21 and 22 will be described. Each copper foil layer 14,16
The mutual dispositions of, for example, include a collinear structure and an alternating (alternate) structure. 1B and 1C are cross-sectional views taken along the line AA ′ of FIG. 1A, showing the cases of the collinear structure and the alternating structure, respectively.

In the case of the collinear structure, a second copper foil layer 16 is provided as a wiring pattern at a position directly above the first copper foil layer 14. In the case of the alternating structure, the second copper foil layer is provided as a wiring pattern on a position shifted by a half cycle with respect to the first copper foil layer 14.

In the stepped conductor pattern 21 corresponding to the outer leads, the distance x between the tip of the second insulating layer 15 and the tip of the second copper foil layer 16, that is, each copper foil layer 14,
The distance between the 16 exposed parts is 0.05 mm (50 μm)
That is all. The minimum value of this interval x is 0.05 mm
Thus, when the semiconductor package 10 is surface-mounted on the printed circuit board, it is possible to prevent an electrical short circuit between the adjacent soldering regions.

Next, surface mounting of the semiconductor package 10 on a printed circuit board will be described with reference to FIG.

Printed circuit board 25 and semiconductor package 10
The copper foil layers 14 and 16 exposed in the stepped conductor pattern 21 corresponding to the outer leads and the pads on the printed circuit board 25 are joined with the solder fillet 26, that is, the normal solder cream. The printing method is used. First, solder cream is printed on a predetermined pad position on a printed board, the semiconductor package 10 is mounted on the printed board by an automatic mounting machine, and reflow heating is performed by a reflow furnace, whereby surface mounting is completed.

In FIG. 2, w represents the size of the step between the exposed surface of the first copper foil layer 14 and the exposed surface of the second copper foil layer 16 in the collar portion 18. When a thick copper foil is used as the copper foil layer, the step w inevitably becomes large, but when the step w is large (for example, 50 μm or more), the connection reliability during mounting on the printed circuit board can be facilitated. In order to secure it, it is desirable that the collar portion has a fold shape as shown in the fourth embodiment.

Here, an example of the arrangement of the solder printing pads on the printed circuit board will be described with reference to FIG. FIG. 3A shows a conventional pad arrangement for the QFP, and the pads 27 are arranged in a line. FIG. 3 (b) shows a pad arrangement in the case where the above-mentioned collinear structure is adopted for the mutual arrangement of the copper foil layers 14 and 16. Compared with the conventional one, a series of pads in the same lead direction is divided into two. The pads 27 arranged in two rows are adopted. When the above-mentioned alternating structure is adopted, the pads 27 arranged in two rows as shown in FIG.
Are shifted from each other by half a cycle. This time,
It is possible to use the same outermost size, pad width, and pad pitch as the conventional QFP pads. However,
Each pad should have the minimum area required to ensure solder strength. Applying a solder resist between the divided pads is effective as a measure for preventing an electrical short circuit due to defective soldering between the divided pads. By designing the pads on the printed circuit board in this way, the conventional soldering part (solder fillet 2
6) can be formed.

The semiconductor integrated circuit element 11 and each copper foil layer 14,
Wire bonding with 16 will be described with reference to FIG. FIG. 4 (a) shows a case where the stepped conductive pattern corresponding to the inner leads is formed by the above-described collinear structure. The wire bonding pad 31 on the semiconductor integrated circuit device 11 side and the copper foil layers 14 and 16 are connected by a bonding wire 19 in a V-shape. At this time, the width y of each copper foil layer 14, 16 as a wiring pattern
Is 0.05 to 0.1 mm, respectively. Further, the pitch z as the wiring pattern is set to 0.1 to 0.2 mm. In this case, the spacing as the wiring pattern (= yz)
Is 0.05 mm or more.

When the wire bonding pad 31 is narrowed, the structure of the stepped conductive pattern 22 corresponding to the inner lead is changed to the above-mentioned alternating structure or the copper foil layers 14 and 16.
The tip end of the bonding wire 19 has a zigzag shape so that an electrical short circuit due to mutual contact of the bonding wires 19 can be prevented. FIG. 4 (b) is a diagram showing an alternating structure, and FIG. 4 (c) is a diagram showing a staggered structure.

Although the first embodiment of the present invention has been described above, the wiring lead width and pitch of the outer lead equivalent portion are the normal 120-pin type QFP (outer lead width 0.35 mm and lead pitch 0.8 mm). If the same is applied, 240 pins can be realized in the semiconductor package of this embodiment. This is the number of pins that cannot be achieved with the conventional QFP even if the pitch is 0.5 mm.
That is, since it is not necessary to reduce the wiring width and the pitch, it is possible to prevent an electrical short circuit due to a defective soldering when the surface mounting is performed on the printed board.

In the semiconductor package of this embodiment, since the area of the collar portion is larger than that of the outer lead portion of the conventional one, when the outermost size is the same as the conventional package size, the area difference is substantially the same. That is, the outer lead area is expanded inward. But,
Considering that the size of the conventional package was defined by the inability to narrow the line pitch in the outer lead part, the size of the semiconductor integrated circuit element mounted inside, the wiring density on the semiconductor package, the mechanical By selecting the optimum bending radius for processing, the large area of the collar does not cause a problem that affects the semiconductor package size.

<< Second Embodiment >> The number of copper foil layers in the semiconductor package of the present invention is not limited to two.
FIG. 5 shows a semiconductor package having three copper foil layers. This semiconductor package 40 has a third insulating layer 41 and a third copper foil layer 42 processed into a wiring pattern on the second copper foil layer 16 of the semiconductor package of the first embodiment shown in FIG. It has a structure in which layers are sequentially laminated. Of course, in each of the staircase-shaped conductor patterns 21 and 22, the third insulating layer 41 and the third copper foil layer 42 also join the above staircase structure.

When the semiconductor package 40 having the three-layer structure is surface-mounted on the printed board 25, it is necessary to divide the pads on the printed board 25 into three parts for each lead direction. In the case of a three-layer structure or a multi-layer structure having more than three layers, the step between the exposed surface of the lowermost copper foil layer and the exposed surface of the uppermost copper foil layer tends to be large in the collar portion. When there is such a large step, in order to easily improve the connection reliability in surface mounting on a printed circuit board or the like, it is desirable that the flange portion be a fold shape as shown in the fourth embodiment.

<< Third Embodiment >> FIG. 6 shows a semiconductor package 50 in which a plurality of semiconductor integrated circuit elements 11 ₁ and 11 ₂ are mounted, and these semiconductor integrated circuit elements 11 ₁ and 11 ₂ are electrically connected to each other. Is shown. This semiconductor package 50
Is of the same layer structure as the semiconductor package of the first embodiment shown in FIG. 1, a semiconductor integrated circuit device 11 _1, 11
_A through hole 51 is provided in the second insulating layer 15 for electrical connection between the two, and the first and second copper foil layers 14 and 16 are electrically connected to each other through the through hole 51. Has been done.

<Fourth Embodiment> In the semiconductor package of the present invention, the edge portion of the copper foil layer is exposed stepwise through the insulating layer at the flange portion at the peripheral edge of the opening surface. In each of the embodiments, as shown in FIG. 2 and the like, there is a step between the exposed surfaces of the copper foil layers, and the heights of the solder fillet portions when mounted on the printed circuit board are different. If the copper foil layer is thin, there is no effect of this step,
When the thickness of the copper foil layer is, for example, 70 μm or more, or when the number of layers of the copper foil layer is 3 or more, the heights of the solder fillet portions become uneven, and the solder for mounting the semiconductor package on the surface of the printed circuit board Poor connection may occur.
Therefore, in this embodiment, the collar portion is formed into a fold shape so that the height of the exposed surface of the copper foil layer is constant.

The semiconductor package 60 shown in FIG.
It has the copper foil layers 14 and 16 of the layer, and the brim portion 61 has a two-step U-shape corresponding to this. In the U-shaped portion 62 closer to the opening surface side, the second copper foil layer 16 is connected to the pad on the printed circuit board 25 side through the solder fillet 26, and in the U-shaped portion 63 on the peripheral side of the flange portion 61. The first copper foil layer 14 is connected to the pad via the solder fillet 26. In the brim portion 61, there is a difference in height of each U-shaped portion 62, 63 of the metal plate 12 by (copper foil layer + insulating layer), whereby each copper foil layer 1
All of the exposed surfaces of 4 and 16 are arranged to be in contact with the same plane. That is, the surfaces of the copper foil layers 14 and 16 are in contact with the surface of the printed board 26.

The semiconductor package 65 shown in FIG.
The case where the copper foil layers 14, 16 and 42 of the layer are provided is shown. Since the number of copper foil layers is three, the collar portion 66
Has a three-stage U-shape, and the third copper foil layer 42 is connected to the pad on the printed circuit board 25 via the solder fillet 26 at the U-shaped portion 67 on the opening surface side, and the intermediate U-shaped portion is formed. At 68, the second copper foil layer 16 is connected, and the collar portion 65
The first copper foil layer 14 is connected at the U-shaped portion 69 on the peripheral side. Also in this semiconductor package 65, the exposed surfaces of the copper foil layers 14, 16, 42 in the flange portion 66 are arranged so as to be in contact with the same plane.

In this embodiment, there are various types of folds (wavy shapes) of the brim. 9 (a)-(c)
Each shows an example of the cross-sectional shape of the collar portion when the copper foil layers have a two-layer structure, and the broken lines in the figure show the copper foil layers 14 and 16 respectively.
Both represent the plane to be touched. In the case shown in FIG. 9A, the collar portion 71 has a U-shaped repeating shape. In the structure shown in FIG. 9 (b), the collar portion 72 has a triangular wave shape, that is, a V-shaped repeating shape. Figure 9
In the case shown in (c), the collar portion 73 has a rectangular wave-like or concave shape.

[0055]

As described above, according to the present invention, a metal base substrate having a plurality of circuit-processed copper foil layers is used, and the end portions of the copper foil layers are offset from each other to form a stepped shape. By doing so, it is possible to take out the external wiring three-dimensionally, and it is possible to dramatically increase the number of outer leads without narrowing the lead wiring width corresponding to the conventional outer leads. .

For example, if the semiconductor package size is 28 m
In the case of m square, in the conventional normal QFP, the outer lead width is 0.35 mm and the lead pitch is 0.8 mm, and 120 leads are taken out. In the case of the semiconductor package of the present invention, two copper foil layers are provided. With the structure, it is possible to provide double the number of outer leads, which is 240, with the same lead width and pitch as the conventional one. Furthermore, if the copper foil layer has a three-layer structure, 360 times as many outer leads can be provided.

In the case of the semiconductor package of the present invention, the number of outer leads is drastically increased by using the same lead width and pitch as those of the conventional one, so that there is no soldering failure during surface mounting and the outer leads are narrowed. There is no need for strict control of mounting conditions in the case of commercialization and no increase in costs due to new processes and equipment. The semiconductor package using the three-dimensional printed circuit board of the present invention can be applied with the conventional die bonding and wire bonding techniques and the surface mounting technique on the printed circuit board, which contributes to the increase in the number of pins of the package for the semiconductor integrated circuit. It is a big deal.

[Brief description of drawings]

FIG. 1A is a sectional view showing the structure of a semiconductor package of a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA ′ of FIG. Diagram showing collinear structure,
FIG. 1C is a sectional view taken along the line AA ′ in FIG. 1A, in which the wiring conductors have an alternating structure.

FIG. 2 is a cross-sectional view showing a state in which the semiconductor package of FIG. 1 (a) is mounted on a printed board.

FIG. 3 is a plan view showing an arrangement of pads provided on a printed circuit board, in which (a), (b), and (c) are conventional QFs, respectively.
FIG. 6 is a diagram showing the arrangement of P, a collinear structure semiconductor package, and an alternating structure semiconductor package.

4A to 4C are plan views showing conductor patterns of inner lead portions, respectively.

FIG. 5 is a sectional view showing the structure of a semiconductor package according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing the structure of a semiconductor package according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the configuration of an example of a semiconductor package of a fourth exemplary embodiment of the present invention.

FIG. 8 is a sectional view showing the configuration of an example of a semiconductor package of a fourth exemplary embodiment of the present invention.

9A to 9C are cross-sectional views each showing an example of the shape of a collar portion in the semiconductor package of the fourth embodiment of the present invention.

FIG. 10 is a QFP which is an example of a conventional semiconductor package.
It is a perspective view explaining.

11A is a perspective view showing a configuration of a conventional electronic circuit package, FIG. 11B is a sectional view of the electronic circuit package of FIG. 11A, and FIG. 11C is a cross-sectional view taken along the line BB of FIG. 11B. It is sectional drawing in a line.

[Explanation of symbols]

10, 40, 50, 60, 65 Semiconductor package 11, 11 ₁ , 11 ₂ Semiconductor integrated circuit element 12 Metal plate 13 First insulating layer 14 First copper foil layer 15 Second insulating layer 16 Second copper foil Layer 17 Opening surface 18,61,66,71-73 Collar 19 Bonding wire 20 Epoxy resin 21,22 Stepped conductor pattern 25 Printed circuit board 26 Solder fillet 27 Pad 31 Wire bonding pad 41 Third insulating layer 42 Third Copper foil layer 51 Through hole 62, 63, 67 to 69 U-shaped portion

Front page continuation (72) Inventor Kyoichi Ishigaki 1190 Kasama-cho, Sakae-ku, Yokohama, Kanagawa Mitsui Toatsu Chemical Co., Ltd. (72) Inventor Hoshino ▲ Tatsumi 1190, Kasama-cho, Sakae-ku, Yokohama, Kanagawa Mitsui Toatsu Chemical Within the corporation

Claims (7)

[Claims] 1. A metal base substrate in which a plurality of circuit-processed copper foil layers are laminated on a metal plate with an insulating layer interposed therebetween, and the metal base substrate is bent or drawn to form an opening. In a three-dimensional printed circuit board for mounting a semiconductor integrated circuit element having a shape with a brim portion on the peripheral edge of the surface, one end side of each of the copper foil layers is staggered for each surface in the brim portion via the insulating layer. And the other end side of each of the copper foil layers is a portion electrically connected to the semiconductor integrated circuit element and is formed in a staircase pattern with each surface shifted through the insulating layer. A semiconductor package using a three-dimensional printed circuit board. 2. The cross-sectional structure at a position corresponding to the vicinity of the end of each copper foil layer is such that each copper foil layer is three-dimensionally formed on the same line when viewed from the normal direction of the metal plate. A semiconductor package using the three-dimensional printed board according to claim 1. 3. The cross-sectional structure at a position corresponding to the vicinity of the end of each copper foil layer is such that the copper foil layers are alternately formed three-dimensionally when viewed from the normal direction of the metal plate. A semiconductor package using the stereoscopic printed board according to claim 1. 4. The three-dimensional printed circuit board according to claim 1, wherein at least two layers of the copper foil layers are electrically connected alternately and a plurality of semiconductor integrated circuit elements can be mounted. Semiconductor package using. 5. The insulating layer according to claim 1, wherein the insulating layer is made of a thermoplastic polyimide having an elongation of 30% or more and a glass transition temperature of 160 ° C. or higher and 350 ° C. or lower. Semiconductor package using the 3D printed circuit board. 6. The tip of each of the copper foil layers on the one end side is separated from the end of the collar by 50 μm or more, and the circuit pattern spacing in the copper foil layer on the same plane is 50 μm or more in the vicinity of the end of the copper foil layer. 5. The semiconductor using the three-dimensional printed circuit board according to claim 1, wherein the distance between exposed portions of the copper foil layers on adjacent surfaces is 50 μm or more in the vicinity of the end portions of the copper foil layers. package. 7. The collar portion has a folded shape, and the surfaces of the copper foil layers exposed in the collar portion are arranged so as to be in contact with the same plane.
A semiconductor package using the stereoscopic printed board according to claim 1.